Mercurial > audlegacy-plugins
annotate src/sexypsf/PsxInterpreter.c @ 3047:4434b4c4a715
ported EsounD plugin
author | Andrew O. Shadoura <bugzilla@tut.by> |
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date | Fri, 17 Apr 2009 16:17:10 +0300 |
parents | 3da1b8942b8b |
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rev | line source |
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1 /* Pcsx - Pc Psx Emulator |
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2 * Copyright (C) 1999-2002 Pcsx Team |
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3 * |
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4 * This program is free software; you can redistribute it and/or modify |
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5 * it under the terms of the GNU General Public License as published by |
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6 * the Free Software Foundation; either version 2 of the License, or |
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7 * (at your option) any later version. |
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8 * |
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9 * This program is distributed in the hope that it will be useful, |
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10 * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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12 * GNU General Public License for more details. |
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13 * |
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14 * You should have received a copy of the GNU General Public License |
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15 * along with this program; if not, write to the Free Software |
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16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA |
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17 */ |
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18 |
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19 #include <stdlib.h> |
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20 |
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21 #include "PsxCommon.h" |
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22 |
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23 static int branch; |
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24 static int branch2; |
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25 static u32 branchPC; |
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26 |
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27 // These macros are used to assemble the repassembler functions |
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28 |
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29 // if(!PSXM(psxRegs.pc)) puts("Whoops"); |
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30 // Fix this... |
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31 |
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32 // printf("%08x ", psxRegs.pc); |
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33 |
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34 #define execI() { \ |
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35 psxRegs.code = BFLIP32(PSXMu32(psxRegs.pc)); \ |
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36 \ |
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37 psxRegs.pc+= 4; psxRegs.cycle++; \ |
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38 psxBSC[psxRegs.code >> 26](); \ |
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39 } |
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40 |
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41 // Subsets |
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42 static void (*psxBSC[64])(); |
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43 static void (*psxSPC[64])(); |
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44 static void (*psxREG[32])(); |
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45 static void (*psxCP0[32])(); |
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46 |
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47 static void delayRead(int reg, u32 bpc) { |
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48 u32 rold, rnew; |
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49 |
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50 // SysPrintf("delayRead at %x!\n", psxRegs.pc); |
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51 |
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52 rold = psxRegs.GPR.r[reg]; |
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53 psxBSC[psxRegs.code >> 26](); // branch delay load |
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54 rnew = psxRegs.GPR.r[reg]; |
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55 |
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56 psxRegs.pc = bpc; |
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57 |
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58 psxBranchTest(); |
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59 |
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60 psxRegs.GPR.r[reg] = rold; |
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61 execI(); // first branch opcode |
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62 psxRegs.GPR.r[reg] = rnew; |
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63 |
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64 branch = 0; |
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65 } |
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66 |
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67 static void delayWrite(int reg, u32 bpc) { |
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68 |
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69 /* SysPrintf("delayWrite at %x!\n", psxRegs.pc); |
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70 |
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71 // SysPrintf("%s\n", disR3000AF(psxRegs.code, psxRegs.pc-4)); |
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72 // SysPrintf("%s\n", disR3000AF(PSXMu32(bpc), bpc));*/ |
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73 |
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74 // no changes from normal behavior |
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75 |
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76 psxBSC[psxRegs.code >> 26](); |
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77 |
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78 branch = 0; |
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79 psxRegs.pc = bpc; |
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80 |
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81 psxBranchTest(); |
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82 } |
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83 |
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84 static void delayReadWrite(int reg, u32 bpc) { |
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85 |
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86 // SysPrintf("delayReadWrite at %x!\n", psxRegs.pc); |
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87 |
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88 // the branch delay load is skipped |
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89 |
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90 branch = 0; |
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91 psxRegs.pc = bpc; |
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92 |
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93 psxBranchTest(); |
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94 } |
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95 |
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96 // this defines shall be used with the tmp |
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97 // of the next func (instead of _Funct_...) |
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98 #define _tFunct_ ((tmp ) & 0x3F) // The funct part of the instruction register |
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99 #define _tRd_ ((tmp >> 11) & 0x1F) // The rd part of the instruction register |
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100 #define _tRt_ ((tmp >> 16) & 0x1F) // The rt part of the instruction register |
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101 #define _tRs_ ((tmp >> 21) & 0x1F) // The rs part of the instruction register |
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102 #define _tSa_ ((tmp >> 6) & 0x1F) // The sa part of the instruction register |
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103 |
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104 static void psxDelayTest(u32 reg, u32 bpc) { |
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105 u32 tmp; |
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106 |
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107 tmp = BFLIP32(PSXMu32(bpc)); |
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108 branch = 1; |
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109 |
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110 switch (tmp >> 26) { |
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111 case 0x00: // SPECIAL |
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112 switch (_tFunct_) { |
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113 case 0x00: // SLL |
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114 if (!tmp) break; // NOP |
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115 case 0x02: case 0x03: // SRL/SRA |
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116 if (_tRd_ == reg && _tRt_ == reg) { |
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117 delayReadWrite(reg, bpc); return; |
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118 } else if (_tRt_ == reg) { |
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119 delayRead(reg, bpc); return; |
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120 } else if (_tRd_ == reg) { |
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121 delayWrite(reg, bpc); return; |
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122 } |
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123 break; |
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124 |
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125 case 0x08: // JR |
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126 if (_tRs_ == reg) { |
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127 delayRead(reg, bpc); return; |
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128 } |
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129 break; |
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130 case 0x09: // JALR |
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131 if (_tRd_ == reg && _tRs_ == reg) { |
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132 delayReadWrite(reg, bpc); return; |
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133 } else if (_tRs_ == reg) { |
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134 delayRead(reg, bpc); return; |
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135 } else if (_tRd_ == reg) { |
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136 delayWrite(reg, bpc); return; |
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137 } |
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138 break; |
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139 |
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140 // SYSCALL/BREAK just a break; |
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141 |
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142 case 0x20: case 0x21: case 0x22: case 0x23: |
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143 case 0x24: case 0x25: case 0x26: case 0x27: |
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144 case 0x2a: case 0x2b: // ADD/ADDU... |
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145 case 0x04: case 0x06: case 0x07: // SLLV... |
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146 if (_tRd_ == reg && (_tRt_ == reg || _tRs_ == reg)) { |
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147 delayReadWrite(reg, bpc); return; |
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148 } else if (_tRt_ == reg || _tRs_ == reg) { |
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149 delayRead(reg, bpc); return; |
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150 } else if (_tRd_ == reg) { |
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151 delayWrite(reg, bpc); return; |
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152 } |
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153 break; |
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154 |
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155 case 0x10: case 0x12: // MFHI/MFLO |
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156 if (_tRd_ == reg) { |
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157 delayWrite(reg, bpc); return; |
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158 } |
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159 break; |
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160 case 0x11: case 0x13: // MTHI/MTLO |
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161 if (_tRs_ == reg) { |
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162 delayRead(reg, bpc); return; |
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163 } |
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164 break; |
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165 |
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166 case 0x18: case 0x19: |
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167 case 0x1a: case 0x1b: // MULT/DIV... |
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168 if (_tRt_ == reg || _tRs_ == reg) { |
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169 delayRead(reg, bpc); return; |
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170 } |
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171 break; |
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172 } |
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173 break; |
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174 |
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175 case 0x01: // REGIMM |
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176 switch (_tRt_) { |
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177 case 0x00: case 0x02: |
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178 case 0x10: case 0x12: // BLTZ/BGEZ... |
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179 if (_tRs_ == reg) { |
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180 delayRead(reg, bpc); return; |
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181 } |
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182 break; |
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183 } |
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184 break; |
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185 |
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186 // J would be just a break; |
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187 case 0x03: // JAL |
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188 if (31 == reg) { |
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189 delayWrite(reg, bpc); return; |
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190 } |
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191 break; |
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192 |
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193 case 0x04: case 0x05: // BEQ/BNE |
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194 if (_tRs_ == reg || _tRt_ == reg) { |
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195 delayRead(reg, bpc); return; |
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196 } |
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197 break; |
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198 |
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199 case 0x06: case 0x07: // BLEZ/BGTZ |
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200 if (_tRs_ == reg) { |
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201 delayRead(reg, bpc); return; |
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202 } |
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203 break; |
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204 |
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205 case 0x08: case 0x09: case 0x0a: case 0x0b: |
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206 case 0x0c: case 0x0d: case 0x0e: // ADDI/ADDIU... |
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207 if (_tRt_ == reg && _tRs_ == reg) { |
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208 delayReadWrite(reg, bpc); return; |
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209 } else if (_tRs_ == reg) { |
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210 delayRead(reg, bpc); return; |
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211 } else if (_tRt_ == reg) { |
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212 delayWrite(reg, bpc); return; |
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213 } |
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214 break; |
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215 |
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216 case 0x0f: // LUI |
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217 if (_tRt_ == reg) { |
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218 delayWrite(reg, bpc); return; |
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219 } |
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220 break; |
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221 |
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222 case 0x10: // COP0 |
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223 switch (_tFunct_) { |
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224 case 0x00: // MFC0 |
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225 if (_tRt_ == reg) { delayWrite(reg, bpc); return; } |
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226 break; |
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227 case 0x02: // CFC0 |
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228 if (_tRt_ == reg) { delayWrite(reg, bpc); return; } |
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229 break; |
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230 case 0x04: // MTC0 |
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231 if (_tRt_ == reg) { delayRead(reg, bpc); return; } |
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232 break; |
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233 case 0x06: // CTC0 |
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234 if (_tRt_ == reg) { delayRead(reg, bpc); return; } |
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235 break; |
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236 // RFE just a break; |
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237 } |
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238 break; |
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239 |
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240 case 0x22: case 0x26: // LWL/LWR |
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241 if (_tRt_ == reg) { |
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242 delayReadWrite(reg, bpc); return; |
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243 } else if (_tRs_ == reg) { |
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244 delayRead(reg, bpc); return; |
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245 } |
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246 break; |
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247 |
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248 case 0x20: case 0x21: case 0x23: |
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249 case 0x24: case 0x25: // LB/LH/LW/LBU/LHU |
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250 if (_tRt_ == reg && _tRs_ == reg) { |
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251 delayReadWrite(reg, bpc); return; |
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252 } else if (_tRs_ == reg) { |
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253 delayRead(reg, bpc); return; |
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254 } else if (_tRt_ == reg) { |
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255 delayWrite(reg, bpc); return; |
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256 } |
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257 break; |
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258 |
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259 case 0x28: case 0x29: case 0x2a: |
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260 case 0x2b: case 0x2e: // SB/SH/SWL/SW/SWR |
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261 if (_tRt_ == reg || _tRs_ == reg) { |
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262 delayRead(reg, bpc); return; |
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263 } |
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264 break; |
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265 |
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266 case 0x32: case 0x3a: // LWC2/SWC2 |
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267 if (_tRs_ == reg) { |
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268 delayRead(reg, bpc); return; |
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269 } |
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270 break; |
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271 } |
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272 psxBSC[psxRegs.code >> 26](); |
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273 |
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274 branch = 0; |
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275 psxRegs.pc = bpc; |
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276 |
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277 psxBranchTest(); |
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278 } |
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279 |
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280 static void psxNULL(void); |
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281 |
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282 static INLINE void doBranch(u32 tar) { |
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283 u32 tmp; |
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284 |
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285 branch2 = branch = 1; |
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286 branchPC = tar; |
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287 |
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288 psxRegs.code = BFLIP32(PSXMu32(psxRegs.pc)); |
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289 |
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290 psxRegs.pc+= 4; psxRegs.cycle++; |
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291 |
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292 // check for load delay |
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293 tmp = psxRegs.code >> 26; |
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294 switch (tmp) { |
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295 case 0x10: // COP0 |
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296 switch (_Rs_) { |
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297 case 0x00: // MFC0 |
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298 case 0x02: // CFC0 |
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299 psxDelayTest(_Rt_, branchPC); |
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300 return; |
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301 } |
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302 break; |
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303 case 0x32: // LWC2 |
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304 psxDelayTest(_Rt_, branchPC); |
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305 return; |
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306 default: |
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307 if (tmp >= 0x20 && tmp <= 0x26) { // LB/LH/LWL/LW/LBU/LHU/LWR |
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308 psxDelayTest(_Rt_, branchPC); |
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309 return; |
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310 } |
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311 break; |
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312 } |
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313 |
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314 psxBSC[psxRegs.code >> 26](); |
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315 |
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316 if((psxRegs.pc-8)==branchPC && !(psxRegs.code>>26)) |
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317 { |
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318 //printf("%08x\n",psxRegs.code>>26); |
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319 CounterDeadLoopSkip(); |
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320 } |
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321 branch = 0; |
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322 psxRegs.pc = branchPC; |
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323 |
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324 psxBranchTest(); |
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325 } |
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326 |
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327 /********************************************************* |
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328 * Arithmetic with immediate operand * |
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329 * Format: OP rt, rs, immediate * |
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330 *********************************************************/ |
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331 static void psxADDI() { if (!_Rt_) return; _rRt_ = _u32(_rRs_) + _Imm_ ; } // Rt = Rs + Im (Exception on Integer Overflow) |
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332 static void psxADDIU() { if (!_Rt_) return; _rRt_ = _u32(_rRs_) + _Imm_ ; } // Rt = Rs + Im |
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333 static void psxANDI() { if (!_Rt_) return; _rRt_ = _u32(_rRs_) & _ImmU_; } // Rt = Rs And Im |
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334 static void psxORI() { if (!_Rt_) return; _rRt_ = _u32(_rRs_) | _ImmU_; } // Rt = Rs Or Im |
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335 static void psxXORI() { if (!_Rt_) return; _rRt_ = _u32(_rRs_) ^ _ImmU_; } // Rt = Rs Xor Im |
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336 static void psxSLTI() { if (!_Rt_) return; _rRt_ = _i32(_rRs_) < _Imm_ ; } // Rt = Rs < Im (Signed) |
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337 static void psxSLTIU() { if (!_Rt_) return; _rRt_ = _u32(_rRs_) < ((u32)_ImmU_); } // Rt = Rs < Im (Unsigned) |
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338 |
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339 /********************************************************* |
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340 * Register arithmetic * |
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341 * Format: OP rd, rs, rt * |
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342 *********************************************************/ |
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343 static void psxADD() { if (!_Rd_) return; _rRd_ = _u32(_rRs_) + _u32(_rRt_); } // Rd = Rs + Rt (Exception on Integer Overflow) |
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344 static void psxADDU() { if (!_Rd_) return; _rRd_ = _u32(_rRs_) + _u32(_rRt_); } // Rd = Rs + Rt |
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345 static void psxSUB() { if (!_Rd_) return; _rRd_ = _u32(_rRs_) - _u32(_rRt_); } // Rd = Rs - Rt (Exception on Integer Overflow) |
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346 static void psxSUBU() { if (!_Rd_) return; _rRd_ = _u32(_rRs_) - _u32(_rRt_); } // Rd = Rs - Rt |
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347 static void psxAND() { if (!_Rd_) return; _rRd_ = _u32(_rRs_) & _u32(_rRt_); } // Rd = Rs And Rt |
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348 static void psxOR() { if (!_Rd_) return; _rRd_ = _u32(_rRs_) | _u32(_rRt_); } // Rd = Rs Or Rt |
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349 static void psxXOR() { if (!_Rd_) return; _rRd_ = _u32(_rRs_) ^ _u32(_rRt_); } // Rd = Rs Xor Rt |
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350 static void psxNOR() { if (!_Rd_) return; _rRd_ =~(_u32(_rRs_) | _u32(_rRt_)); }// Rd = Rs Nor Rt |
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351 static void psxSLT() { if (!_Rd_) return; _rRd_ = _i32(_rRs_) < _i32(_rRt_); } // Rd = Rs < Rt (Signed) |
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352 static void psxSLTU() { if (!_Rd_) return; _rRd_ = _u32(_rRs_) < _u32(_rRt_); } // Rd = Rs < Rt (Unsigned) |
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353 |
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354 /********************************************************* |
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355 * Register mult/div & Register trap logic * |
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356 * Format: OP rs, rt * |
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357 *********************************************************/ |
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358 static void psxDIV() { |
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359 if (_i32(_rRt_) != 0) { |
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360 _rLo_ = _i32(_rRs_) / _i32(_rRt_); |
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361 _rHi_ = _i32(_rRs_) % _i32(_rRt_); |
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362 } |
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363 } |
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364 |
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365 static void psxDIVU() { |
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366 if (_rRt_ != 0) { |
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367 _rLo_ = _rRs_ / _rRt_; |
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368 _rHi_ = _rRs_ % _rRt_; |
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369 } |
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370 } |
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371 |
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372 static void psxMULT() { |
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373 u64 res = (s64)((s64)_i32(_rRs_) * (s64)_i32(_rRt_)); |
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374 |
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375 psxRegs.GPR.n.lo = (u32)(res & 0xffffffff); |
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376 psxRegs.GPR.n.hi = (u32)((res >> 32) & 0xffffffff); |
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377 } |
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378 |
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379 static void psxMULTU() { |
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380 u64 res = (u64)((u64)_u32(_rRs_) * (u64)_u32(_rRt_)); |
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381 |
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382 psxRegs.GPR.n.lo = (u32)(res & 0xffffffff); |
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383 psxRegs.GPR.n.hi = (u32)((res >> 32) & 0xffffffff); |
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384 } |
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385 |
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386 /********************************************************* |
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387 * Register branch logic * |
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388 * Format: OP rs, offset * |
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389 *********************************************************/ |
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390 #define RepZBranchi32(op) if(_i32(_rRs_) op 0) doBranch(_BranchTarget_); |
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391 #define RepZBranchLinki32(op) if(_i32(_rRs_) op 0) { _SetLink(31); doBranch(_BranchTarget_); } |
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392 |
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393 static void psxBGEZ() { RepZBranchi32(>=) } // Branch if Rs >= 0 |
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394 static void psxBGEZAL() { RepZBranchLinki32(>=) } // Branch if Rs >= 0 and link |
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395 static void psxBGTZ() { RepZBranchi32(>) } // Branch if Rs > 0 |
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396 static void psxBLEZ() { RepZBranchi32(<=) } // Branch if Rs <= 0 |
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397 static void psxBLTZ() { RepZBranchi32(<) } // Branch if Rs < 0 |
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398 static void psxBLTZAL() { RepZBranchLinki32(<) } // Branch if Rs < 0 and link |
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399 |
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400 /********************************************************* |
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401 * Shift arithmetic with constant shift * |
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402 * Format: OP rd, rt, sa * |
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403 *********************************************************/ |
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404 static void psxSLL() { if (!_Rd_) return; _rRd_ = _u32(_rRt_) << _Sa_; } // Rd = Rt << sa |
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405 static void psxSRA() { if (!_Rd_) return; _rRd_ = _i32(_rRt_) >> _Sa_; } // Rd = Rt >> sa (arithmetic) |
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406 static void psxSRL() { if (!_Rd_) return; _rRd_ = _u32(_rRt_) >> _Sa_; } // Rd = Rt >> sa (logical) |
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407 |
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408 /********************************************************* |
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409 * Shift arithmetic with variant register shift * |
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410 * Format: OP rd, rt, rs * |
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411 *********************************************************/ |
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412 static void psxSLLV() { if (!_Rd_) return; _rRd_ = _u32(_rRt_) << _u32(_rRs_); } // Rd = Rt << rs |
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413 static void psxSRAV() { if (!_Rd_) return; _rRd_ = _i32(_rRt_) >> _u32(_rRs_); } // Rd = Rt >> rs (arithmetic) |
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414 static void psxSRLV() { if (!_Rd_) return; _rRd_ = _u32(_rRt_) >> _u32(_rRs_); } // Rd = Rt >> rs (logical) |
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415 |
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416 /********************************************************* |
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417 * Load higher 16 bits of the first word in GPR with imm * |
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418 * Format: OP rt, immediate * |
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419 *********************************************************/ |
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420 static void psxLUI() { if (!_Rt_) return; _rRt_ = psxRegs.code << 16; } // Upper halfword of Rt = Im |
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421 |
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422 /********************************************************* |
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423 * Move from HI/LO to GPR * |
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424 * Format: OP rd * |
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425 *********************************************************/ |
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426 static void psxMFHI() { if (!_Rd_) return; _rRd_ = _rHi_; } // Rd = Hi |
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427 static void psxMFLO() { if (!_Rd_) return; _rRd_ = _rLo_; } // Rd = Lo |
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428 |
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429 /********************************************************* |
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430 * Move to GPR to HI/LO & Register jump * |
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431 * Format: OP rs * |
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432 *********************************************************/ |
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433 static void psxMTHI() { _rHi_ = _rRs_; } // Hi = Rs |
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434 static void psxMTLO() { _rLo_ = _rRs_; } // Lo = Rs |
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435 |
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436 /********************************************************* |
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437 * Special purpose instructions * |
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438 * Format: OP * |
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439 *********************************************************/ |
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440 static void psxBREAK() { |
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441 // Break exception - psx rom doens't handles this |
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442 } |
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443 |
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444 static void psxSYSCALL() { |
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445 psxRegs.pc -= 4; |
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446 psxException(0x20, branch); |
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447 } |
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448 |
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449 static void psxRFE() { |
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450 psxRegs.CP0.n.Status = (psxRegs.CP0.n.Status & 0xfffffff0) | |
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451 ((psxRegs.CP0.n.Status & 0x3c) >> 2); |
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452 } |
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453 |
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454 /********************************************************* |
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455 * Register branch logic * |
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456 * Format: OP rs, rt, offset * |
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457 *********************************************************/ |
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458 #define RepBranchi32(op) if(_i32(_rRs_) op _i32(_rRt_)) { doBranch(_BranchTarget_); } |
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459 |
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460 static void psxBEQ() { RepBranchi32(==) } // Branch if Rs == Rt |
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461 static void psxBNE() { RepBranchi32(!=) } // Branch if Rs != Rt |
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462 |
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463 /********************************************************* |
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464 * Jump to target * |
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465 * Format: OP target * |
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466 *********************************************************/ |
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467 static void psxJ() { doBranch(_JumpTarget_); } |
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468 static void psxJAL() { _SetLink(31); doBranch(_JumpTarget_); } |
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469 |
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470 /********************************************************* |
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471 * Register jump * |
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472 * Format: OP rs, rd * |
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473 *********************************************************/ |
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474 static void psxJR() { doBranch(_u32(_rRs_)); } |
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475 static void psxJALR() { if (_Rd_) { _SetLink(_Rd_); } doBranch(_u32(_rRs_)); } |
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476 |
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477 /********************************************************* |
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478 * Load and store for GPR * |
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479 * Format: OP rt, offset(base) * |
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480 *********************************************************/ |
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481 |
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482 #define _oB_ (_u32(_rRs_) + _Imm_) |
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483 |
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484 static void psxLB() { |
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485 if (_Rt_) { |
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486 _rRt_ = (s8)psxMemRead8(_oB_); |
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487 } else { |
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488 psxMemRead8(_oB_); |
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489 } |
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490 } |
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491 |
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492 static void psxLBU() { |
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493 if (_Rt_) { |
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494 _rRt_ = psxMemRead8(_oB_); |
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495 } else { |
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496 psxMemRead8(_oB_); |
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497 } |
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498 } |
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499 |
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500 static void psxLH() { |
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501 if (_Rt_) { |
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502 _rRt_ = (s16)psxMemRead16(_oB_); |
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503 } else { |
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504 psxMemRead16(_oB_); |
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505 } |
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506 } |
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507 |
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508 static void psxLHU() { |
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509 if (_Rt_) { |
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510 _rRt_ = psxMemRead16(_oB_); |
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511 } else { |
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512 psxMemRead16(_oB_); |
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513 } |
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514 } |
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515 |
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516 static void psxLW() { |
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517 if (_Rt_) { |
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518 _rRt_ = psxMemRead32(_oB_); |
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519 } else { |
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520 psxMemRead32(_oB_); |
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521 } |
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522 } |
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523 |
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524 static u32 LWL_MASK[4] = { 0xffffff, 0xffff, 0xff, 0 }; |
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525 static u32 LWL_SHIFT[4] = { 24, 16, 8, 0 }; |
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526 |
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527 static void psxLWL() { |
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528 u32 addr = _oB_; |
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529 u32 shift = addr & 3; |
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530 u32 mem = psxMemRead32(addr & ~3); |
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531 |
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532 if (!_Rt_) return; |
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533 _rRt_ = ( _u32(_rRt_) & LWL_MASK[shift]) | |
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534 ( mem << LWL_SHIFT[shift]); |
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535 |
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536 /* |
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537 Mem = 1234. Reg = abcd |
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538 |
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539 0 4bcd (mem << 24) | (reg & 0x00ffffff) |
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540 1 34cd (mem << 16) | (reg & 0x0000ffff) |
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541 2 234d (mem << 8) | (reg & 0x000000ff) |
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542 3 1234 (mem ) | (reg & 0x00000000) |
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543 */ |
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544 } |
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545 |
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546 static u32 LWR_MASK[4] = { 0, 0xff000000, 0xffff0000, 0xffffff00 }; |
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547 static u32 LWR_SHIFT[4] = { 0, 8, 16, 24 }; |
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548 |
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549 static void psxLWR() { |
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550 u32 addr = _oB_; |
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551 u32 shift = addr & 3; |
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552 u32 mem = psxMemRead32(addr & ~3); |
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553 |
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554 if (!_Rt_) return; |
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555 _rRt_ = ( _u32(_rRt_) & LWR_MASK[shift]) | |
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556 ( mem >> LWR_SHIFT[shift]); |
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557 |
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558 /* |
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559 Mem = 1234. Reg = abcd |
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560 |
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561 0 1234 (mem ) | (reg & 0x00000000) |
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562 1 a123 (mem >> 8) | (reg & 0xff000000) |
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563 2 ab12 (mem >> 16) | (reg & 0xffff0000) |
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564 3 abc1 (mem >> 24) | (reg & 0xffffff00) |
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565 */ |
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566 } |
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567 |
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568 static void psxSB() { psxMemWrite8 (_oB_, _u8 (_rRt_)); } |
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569 static void psxSH() { psxMemWrite16(_oB_, _u16(_rRt_)); } |
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570 static void psxSW() { psxMemWrite32(_oB_, _u32(_rRt_)); } |
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571 |
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572 static const u32 SWL_MASK[4] = { 0xffffff00, 0xffff0000, 0xff000000, 0 }; |
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573 static const u32 SWL_SHIFT[4] = { 24, 16, 8, 0 }; |
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574 |
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575 static void psxSWL() { |
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576 u32 addr = _oB_; |
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577 u32 shift = addr & 3; |
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578 u32 mem = psxMemRead32(addr & ~3); |
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579 |
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580 psxMemWrite32(addr & ~3, (_u32(_rRt_) >> SWL_SHIFT[shift]) | |
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581 ( mem & SWL_MASK[shift]) ); |
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582 /* |
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583 Mem = 1234. Reg = abcd |
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584 |
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585 0 123a (reg >> 24) | (mem & 0xffffff00) |
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586 1 12ab (reg >> 16) | (mem & 0xffff0000) |
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587 2 1abc (reg >> 8) | (mem & 0xff000000) |
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588 3 abcd (reg ) | (mem & 0x00000000) |
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589 */ |
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590 } |
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591 |
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592 static const u32 SWR_MASK[4] = { 0, 0xff, 0xffff, 0xffffff }; |
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593 static const u32 SWR_SHIFT[4] = { 0, 8, 16, 24 }; |
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594 |
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595 static void psxSWR() { |
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596 u32 addr = _oB_; |
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597 u32 shift = addr & 3; |
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598 u32 mem = psxMemRead32(addr & ~3); |
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599 |
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600 psxMemWrite32(addr & ~3, (_u32(_rRt_) << SWR_SHIFT[shift]) | |
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601 ( mem & SWR_MASK[shift]) ); |
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602 |
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603 /* |
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604 Mem = 1234. Reg = abcd |
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605 |
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606 0 abcd (reg ) | (mem & 0x00000000) |
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607 1 bcd4 (reg << 8) | (mem & 0x000000ff) |
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608 2 cd34 (reg << 16) | (mem & 0x0000ffff) |
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609 3 d234 (reg << 24) | (mem & 0x00ffffff) |
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610 */ |
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611 } |
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612 |
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613 /********************************************************* |
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614 * Moves between GPR and COPx * |
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615 * Format: OP rt, fs * |
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616 *********************************************************/ |
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617 static void psxMFC0() { if (!_Rt_) return; _rRt_ = (int)_rFs_; } |
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618 static void psxCFC0() { if (!_Rt_) return; _rRt_ = (int)_rFs_; } |
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619 |
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620 static INLINE void MTC0(int reg, u32 val) { |
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621 switch (reg) { |
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622 case 13: // Cause |
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623 psxRegs.CP0.n.Cause = val & ~(0xfc00); |
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624 |
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625 // the next code is untested, if u know please |
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626 // tell me if it works ok or not (linuzappz) |
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627 if (psxRegs.CP0.n.Cause & psxRegs.CP0.n.Status & 0x0300 && |
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628 psxRegs.CP0.n.Status & 0x1) { |
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629 psxException(psxRegs.CP0.n.Cause, 0); |
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630 } |
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631 break; |
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632 |
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633 default: |
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634 psxRegs.CP0.r[reg] = val; |
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635 break; |
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636 } |
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637 } |
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638 |
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639 static void psxMTC0() { MTC0(_Rd_, _u32(_rRt_)); } |
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640 static void psxCTC0() { MTC0(_Rd_, _u32(_rRt_)); } |
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641 |
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642 /********************************************************* |
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643 * Unknow instruction (would generate an exception) * |
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644 * Format: ? * |
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645 *********************************************************/ |
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646 static void psxNULL() { |
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647 #ifdef PSXCPU_LOG |
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648 PSXCPU_LOG("psx: Unimplemented op %x\n", psxRegs.code); |
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649 #endif |
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650 } |
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651 |
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652 static void psxSPECIAL() { |
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653 psxSPC[_Funct_](); |
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654 } |
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655 |
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656 static void psxREGIMM() { |
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657 psxREG[_Rt_](); |
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658 } |
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659 |
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660 static void psxCOP0() { |
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661 psxCP0[_Rs_](); |
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662 } |
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663 |
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664 static void psxHLE() { |
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665 psxHLEt[psxRegs.code & 0xff](); |
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666 } |
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667 |
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668 static void (*psxBSC[64])() = { |
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669 psxSPECIAL, psxREGIMM, psxJ , psxJAL , psxBEQ , psxBNE , psxBLEZ, psxBGTZ, |
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670 psxADDI , psxADDIU , psxSLTI, psxSLTIU, psxANDI, psxORI , psxXORI, psxLUI , |
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671 psxCOP0 , psxNULL , psxNULL, psxNULL , psxNULL, psxNULL, psxNULL, psxNULL, |
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672 psxNULL , psxNULL , psxNULL, psxNULL , psxNULL, psxNULL, psxNULL, psxNULL, |
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673 psxLB , psxLH , psxLWL , psxLW , psxLBU , psxLHU , psxLWR , psxNULL, |
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674 psxSB , psxSH , psxSWL , psxSW , psxNULL, psxNULL, psxSWR , psxNULL, |
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675 psxNULL , psxNULL , psxNULL, psxNULL , psxNULL, psxNULL, psxNULL, psxNULL, |
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676 psxNULL , psxNULL , psxNULL, psxHLE , psxNULL, psxNULL, psxNULL, psxNULL |
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677 }; |
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678 |
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679 |
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680 static void (*psxSPC[64])() = { |
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681 psxSLL , psxNULL , psxSRL , psxSRA , psxSLLV , psxNULL , psxSRLV, psxSRAV, |
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682 psxJR , psxJALR , psxNULL, psxNULL, psxSYSCALL, psxBREAK, psxNULL, psxNULL, |
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683 psxMFHI, psxMTHI , psxMFLO, psxMTLO, psxNULL , psxNULL , psxNULL, psxNULL, |
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684 psxMULT, psxMULTU, psxDIV , psxDIVU, psxNULL , psxNULL , psxNULL, psxNULL, |
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685 psxADD , psxADDU , psxSUB , psxSUBU, psxAND , psxOR , psxXOR , psxNOR , |
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686 psxNULL, psxNULL , psxSLT , psxSLTU, psxNULL , psxNULL , psxNULL, psxNULL, |
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687 psxNULL, psxNULL , psxNULL, psxNULL, psxNULL , psxNULL , psxNULL, psxNULL, |
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688 psxNULL, psxNULL , psxNULL, psxNULL, psxNULL , psxNULL , psxNULL, psxNULL |
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689 }; |
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690 |
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691 static void (*psxREG[32])() = { |
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692 psxBLTZ , psxBGEZ , psxNULL, psxNULL, psxNULL, psxNULL, psxNULL, psxNULL, |
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693 psxNULL , psxNULL , psxNULL, psxNULL, psxNULL, psxNULL, psxNULL, psxNULL, |
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694 psxBLTZAL, psxBGEZAL, psxNULL, psxNULL, psxNULL, psxNULL, psxNULL, psxNULL, |
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695 psxNULL , psxNULL , psxNULL, psxNULL, psxNULL, psxNULL, psxNULL, psxNULL |
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696 }; |
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697 |
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698 static void (*psxCP0[32])() = { |
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699 psxMFC0, psxNULL, psxCFC0, psxNULL, psxMTC0, psxNULL, psxCTC0, psxNULL, |
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700 psxNULL, psxNULL, psxNULL, psxNULL, psxNULL, psxNULL, psxNULL, psxNULL, |
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701 psxRFE , psxNULL, psxNULL, psxNULL, psxNULL, psxNULL, psxNULL, psxNULL, |
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702 psxNULL, psxNULL, psxNULL, psxNULL, psxNULL, psxNULL, psxNULL, psxNULL |
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703 }; |
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704 |
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705 |
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706 /////////////////////////////////////////// |
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707 |
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708 static int intInit() { |
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709 return 0; |
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710 } |
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711 |
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712 static void intReset() { |
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713 branch=branch2=0; |
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714 } |
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715 |
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716 static void intExecute() { |
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717 for (;;) |
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718 { |
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719 if(!CounterSPURun()) |
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720 { |
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721 psxShutdown(); |
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722 return; |
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723 } |
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724 SPUendflush(); |
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725 execI(); |
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726 } |
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727 } |
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728 |
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729 static void intExecuteBlock() { |
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730 branch2 = 0; |
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731 while (!branch2) execI(); |
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732 } |
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733 |
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734 static void intClear(u32 Addr, u32 Size) { |
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735 } |
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736 |
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737 static void intShutdown() { |
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738 } |
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739 |
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740 R3000Acpu psxInt = { |
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741 intInit, |
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742 intReset, |
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743 intExecute, |
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744 intExecuteBlock, |
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745 intClear, |
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746 intShutdown |
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747 }; |