Mercurial > audlegacy-plugins
annotate src/console/Spc_Cpu.h @ 2499:4d6045c20cc5
Include cleanups, part #4.
author | Matti Hamalainen <ccr@tnsp.org> |
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date | Mon, 31 Mar 2008 15:18:05 +0300 |
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1 // snes_spc 0.9.0. http://www.slack.net/~ant/ |
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2 |
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3 /* Copyright (C) 2004-2007 Shay Green. This module is free software; you |
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4 can redistribute it and/or modify it under the terms of the GNU Lesser |
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5 General Public License as published by the Free Software Foundation; either |
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6 version 2.1 of the License, or (at your option) any later version. This |
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7 module is distributed in the hope that it will be useful, but WITHOUT ANY |
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8 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS |
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9 FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more |
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10 details. You should have received a copy of the GNU Lesser General Public |
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11 License along with this module; if not, write to the Free Software Foundation, |
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12 Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ |
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13 |
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14 //// Memory access |
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15 |
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16 #if SPC_MORE_ACCURACY |
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17 #define SUSPICIOUS_OPCODE( name ) ((void) 0) |
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18 #else |
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19 #define SUSPICIOUS_OPCODE( name ) dprintf( "SPC: suspicious opcode: " name "\n" ) |
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20 #endif |
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21 |
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22 #define CPU_READ( time, offset, addr )\ |
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23 cpu_read( addr, time + offset ) |
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24 |
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25 #define CPU_WRITE( time, offset, addr, data )\ |
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26 cpu_write( data, addr, time + offset ) |
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27 |
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28 #if SPC_MORE_ACCURACY |
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29 #define CPU_READ_TIMER( time, offset, addr, out )\ |
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30 { out = CPU_READ( time, offset, addr ); } |
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31 |
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32 #else |
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33 // timers are by far the most common thing read from dp |
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34 #define CPU_READ_TIMER( time, offset, addr_, out )\ |
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35 {\ |
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36 rel_time_t adj_time = time + offset;\ |
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37 int dp_addr = addr_;\ |
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38 int ti = dp_addr - (r_t0out + 0xF0);\ |
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39 if ( (unsigned) ti < timer_count )\ |
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40 {\ |
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41 Timer* t = &m.timers [ti];\ |
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42 if ( adj_time >= t->next_time )\ |
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43 t = run_timer_( t, adj_time );\ |
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44 out = t->counter;\ |
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45 t->counter = 0;\ |
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46 }\ |
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47 else\ |
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48 {\ |
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49 out = ram [dp_addr];\ |
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50 int i = dp_addr - 0xF0;\ |
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51 if ( (unsigned) i < 0x10 )\ |
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52 out = cpu_read_smp_reg( i, adj_time );\ |
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53 }\ |
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54 } |
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55 #endif |
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56 |
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57 #define TIME_ADJ( n ) (n) |
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58 |
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59 #define READ_TIMER( time, addr, out ) CPU_READ_TIMER( rel_time, TIME_ADJ(time), (addr), out ) |
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60 #define READ( time, addr ) CPU_READ ( rel_time, TIME_ADJ(time), (addr) ) |
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61 #define WRITE( time, addr, data ) CPU_WRITE( rel_time, TIME_ADJ(time), (addr), (data) ) |
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62 |
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63 #define DP_ADDR( addr ) (dp + (addr)) |
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64 |
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65 #define READ_DP_TIMER( time, addr, out ) CPU_READ_TIMER( rel_time, TIME_ADJ(time), DP_ADDR( addr ), out ) |
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66 #define READ_DP( time, addr ) READ ( time, DP_ADDR( addr ) ) |
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67 #define WRITE_DP( time, addr, data ) WRITE( time, DP_ADDR( addr ), data ) |
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68 |
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69 #define READ_PROG16( addr ) GET_LE16( ram + (addr) ) |
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70 |
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71 #define SET_PC( n ) (pc = ram + (n)) |
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72 #define GET_PC() (pc - ram) |
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73 #define READ_PC( pc ) (*(pc)) |
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74 #define READ_PC16( pc ) GET_LE16( pc ) |
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75 |
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76 // TODO: remove non-wrapping versions? |
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77 #define SPC_NO_SP_WRAPAROUND 0 |
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78 |
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79 #define SET_SP( v ) (sp = ram + 0x101 + (v)) |
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80 #define GET_SP() (sp - 0x101 - ram) |
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81 |
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82 #if SPC_NO_SP_WRAPAROUND |
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83 #define PUSH16( v ) (sp -= 2, SET_LE16( sp, v )) |
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84 #define PUSH( v ) (void) (*--sp = (uint8_t) (v)) |
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85 #define POP( out ) (void) ((out) = *sp++) |
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86 |
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87 #else |
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88 #define PUSH16( data )\ |
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89 {\ |
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90 int addr = (sp -= 2) - ram;\ |
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91 if ( addr > 0x100 )\ |
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92 {\ |
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93 SET_LE16( sp, data );\ |
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94 }\ |
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95 else\ |
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96 {\ |
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97 ram [(uint8_t) addr + 0x100] = (uint8_t) data;\ |
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98 sp [1] = (uint8_t) (data >> 8);\ |
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99 sp += 0x100;\ |
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100 }\ |
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101 } |
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102 |
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103 #define PUSH( data )\ |
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104 {\ |
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105 *--sp = (uint8_t) (data);\ |
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106 if ( sp - ram == 0x100 )\ |
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107 sp += 0x100;\ |
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108 } |
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109 |
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110 #define POP( out )\ |
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111 {\ |
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112 out = *sp++;\ |
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113 if ( sp - ram == 0x201 )\ |
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114 {\ |
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115 out = sp [-0x101];\ |
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116 sp -= 0x100;\ |
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117 }\ |
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118 } |
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119 |
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120 #endif |
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121 |
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122 #define MEM_BIT( rel ) CPU_mem_bit( pc, rel_time + rel ) |
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123 |
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124 unsigned Snes_Spc::CPU_mem_bit( uint8_t const* pc, rel_time_t rel_time ) |
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125 { |
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126 unsigned addr = READ_PC16( pc ); |
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127 unsigned t = READ( 0, addr & 0x1FFF ) >> (addr >> 13); |
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128 return t << 8 & 0x100; |
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129 } |
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130 |
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131 //// Status flag handling |
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132 |
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133 // Hex value in name to clarify code and bit shifting. |
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134 // Flag stored in indicated variable during emulation |
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135 int const n80 = 0x80; // nz |
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136 int const v40 = 0x40; // psw |
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137 int const p20 = 0x20; // dp |
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138 int const b10 = 0x10; // psw |
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139 int const h08 = 0x08; // psw |
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140 int const i04 = 0x04; // psw |
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141 int const z02 = 0x02; // nz |
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142 int const c01 = 0x01; // c |
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143 |
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144 int const nz_neg_mask = 0x880; // either bit set indicates N flag set |
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145 |
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146 #define GET_PSW( out )\ |
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147 {\ |
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148 out = psw & ~(n80 | p20 | z02 | c01);\ |
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149 out |= c >> 8 & c01;\ |
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150 out |= dp >> 3 & p20;\ |
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151 out |= ((nz >> 4) | nz) & n80;\ |
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152 if ( !(uint8_t) nz ) out |= z02;\ |
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153 } |
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154 |
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155 #define SET_PSW( in )\ |
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156 {\ |
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157 psw = in;\ |
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158 c = in << 8;\ |
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159 dp = in << 3 & 0x100;\ |
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160 nz = (in << 4 & 0x800) | (~in & z02);\ |
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161 } |
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162 |
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163 SPC_CPU_RUN_FUNC |
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164 { |
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165 uint8_t* const ram = RAM; |
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166 int a = m.cpu_regs.a; |
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167 int x = m.cpu_regs.x; |
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168 int y = m.cpu_regs.y; |
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169 uint8_t const* pc; |
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170 uint8_t* sp; |
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171 int psw; |
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172 int c; |
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173 int nz; |
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174 int dp; |
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175 |
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176 SET_PC( m.cpu_regs.pc ); |
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177 SET_SP( m.cpu_regs.sp ); |
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178 SET_PSW( m.cpu_regs.psw ); |
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179 |
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180 goto loop; |
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181 |
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182 |
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183 // Main loop |
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184 |
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185 cbranch_taken_loop: |
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186 pc += *(BOOST::int8_t const*) pc; |
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187 inc_pc_loop: |
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188 pc++; |
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189 loop: |
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190 { |
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191 unsigned opcode; |
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192 unsigned data; |
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193 |
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194 check( (unsigned) a < 0x100 ); |
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195 check( (unsigned) x < 0x100 ); |
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196 check( (unsigned) y < 0x100 ); |
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197 |
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198 opcode = *pc; |
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199 if ( (rel_time += m.cycle_table [opcode]) > 0 ) |
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200 goto out_of_time; |
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201 |
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202 #ifdef SPC_CPU_OPCODE_HOOK |
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203 SPC_CPU_OPCODE_HOOK( GET_PC(), opcode ); |
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204 #endif |
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205 /* |
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206 //SUB_CASE_COUNTER( 1 ); |
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207 #define PROFILE_TIMER_LOOP( op, addr, len )\ |
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208 if ( opcode == op )\ |
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209 {\ |
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210 int cond = (unsigned) ((addr) - 0xFD) < 3 &&\ |
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211 pc [len] == 0xF0 && pc [len+1] == 0xFE - len;\ |
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212 SUB_CASE_COUNTER( op && cond );\ |
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213 } |
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214 |
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215 PROFILE_TIMER_LOOP( 0xEC, GET_LE16( pc + 1 ), 3 ); |
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216 PROFILE_TIMER_LOOP( 0xEB, pc [1], 2 ); |
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217 PROFILE_TIMER_LOOP( 0xE4, pc [1], 2 ); |
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218 */ |
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219 |
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220 // TODO: if PC is at end of memory, this will get wrong operand (very obscure) |
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221 data = *++pc; |
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222 switch ( opcode ) |
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223 { |
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224 |
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225 // Common instructions |
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226 |
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227 #define BRANCH( cond )\ |
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228 {\ |
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229 pc++;\ |
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230 pc += (BOOST::int8_t) data;\ |
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231 if ( cond )\ |
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232 goto loop;\ |
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233 pc -= (BOOST::int8_t) data;\ |
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234 rel_time -= 2;\ |
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235 goto loop;\ |
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236 } |
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237 |
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238 case 0xF0: // BEQ |
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239 BRANCH( !(uint8_t) nz ) // 89% taken |
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240 |
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241 case 0xD0: // BNE |
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242 BRANCH( (uint8_t) nz ) |
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243 |
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244 case 0x3F:{// CALL |
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245 int old_addr = GET_PC() + 2; |
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246 SET_PC( READ_PC16( pc ) ); |
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247 PUSH16( old_addr ); |
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248 goto loop; |
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249 } |
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250 |
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251 case 0x6F:// RET |
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252 #if SPC_NO_SP_WRAPAROUND |
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253 { |
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254 SET_PC( GET_LE16( sp ) ); |
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255 sp += 2; |
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256 } |
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257 #else |
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258 { |
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259 int addr = sp - ram; |
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260 SET_PC( GET_LE16( sp ) ); |
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261 sp += 2; |
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262 if ( addr < 0x1FF ) |
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263 goto loop; |
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264 |
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265 SET_PC( sp [-0x101] * 0x100 + ram [(uint8_t) addr + 0x100] ); |
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266 sp -= 0x100; |
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267 } |
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268 #endif |
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269 goto loop; |
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270 |
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271 case 0xE4: // MOV a,dp |
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272 ++pc; |
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273 // 80% from timer |
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274 READ_DP_TIMER( 0, data, a = nz ); |
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275 goto loop; |
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276 |
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277 case 0xFA:{// MOV dp,dp |
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278 int temp; |
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279 READ_DP_TIMER( -2, data, temp ); |
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280 data = temp + no_read_before_write ; |
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281 } |
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282 // fall through |
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283 case 0x8F:{// MOV dp,#imm |
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284 int temp = READ_PC( pc + 1 ); |
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285 pc += 2; |
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286 |
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287 #if !SPC_MORE_ACCURACY |
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288 { |
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289 int i = dp + temp; |
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290 ram [i] = (uint8_t) data; |
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291 i -= 0xF0; |
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292 if ( (unsigned) i < 0x10 ) // 76% |
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293 { |
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294 REGS [i] = (uint8_t) data; |
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295 |
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296 // Registers other than $F2 and $F4-$F7 |
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297 //if ( i != 2 && i != 4 && i != 5 && i != 6 && i != 7 ) |
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298 if ( ((~0x2F00 << (bits_in_int - 16)) << i) < 0 ) // 12% |
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299 cpu_write_smp_reg( data, rel_time, i ); |
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300 } |
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301 } |
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302 #else |
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303 WRITE_DP( 0, temp, data ); |
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304 #endif |
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305 goto loop; |
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306 } |
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307 |
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308 case 0xC4: // MOV dp,a |
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309 ++pc; |
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310 #if !SPC_MORE_ACCURACY |
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311 { |
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312 int i = dp + data; |
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313 ram [i] = (uint8_t) a; |
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314 i -= 0xF0; |
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315 if ( (unsigned) i < 0x10 ) // 39% |
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316 { |
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317 unsigned sel = i - 2; |
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318 REGS [i] = (uint8_t) a; |
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319 |
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320 if ( sel == 1 ) // 51% $F3 |
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321 dsp_write( a, rel_time ); |
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322 else if ( sel > 1 ) // 1% not $F2 or $F3 |
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323 cpu_write_smp_reg_( a, rel_time, i ); |
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324 } |
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325 } |
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326 #else |
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327 WRITE_DP( 0, data, a ); |
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328 #endif |
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329 goto loop; |
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330 |
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331 #define CASE( n ) case n: |
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332 |
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333 // Define common address modes based on opcode for immediate mode. Execution |
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334 // ends with data set to the address of the operand. |
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335 #define ADDR_MODES_( op )\ |
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336 CASE( op - 0x02 ) /* (X) */\ |
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337 data = x + dp;\ |
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338 pc--;\ |
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339 goto end_##op;\ |
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340 CASE( op + 0x0F ) /* (dp)+Y */\ |
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341 data = READ_PROG16( data + dp ) + y;\ |
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342 goto end_##op;\ |
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343 CASE( op - 0x01 ) /* (dp+X) */\ |
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344 data = READ_PROG16( ((uint8_t) (data + x)) + dp );\ |
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345 goto end_##op;\ |
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346 CASE( op + 0x0E ) /* abs+Y */\ |
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347 data += y;\ |
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348 goto abs_##op;\ |
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349 CASE( op + 0x0D ) /* abs+X */\ |
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350 data += x;\ |
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351 CASE( op - 0x03 ) /* abs */\ |
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352 abs_##op:\ |
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353 data += 0x100 * READ_PC( ++pc );\ |
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354 goto end_##op;\ |
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355 CASE( op + 0x0C ) /* dp+X */\ |
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356 data = (uint8_t) (data + x); |
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357 |
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358 #define ADDR_MODES_NO_DP( op )\ |
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359 ADDR_MODES_( op )\ |
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360 data += dp;\ |
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|
361 end_##op: |
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|
362 |
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363 #define ADDR_MODES( op )\ |
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364 ADDR_MODES_( op )\ |
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365 CASE( op - 0x04 ) /* dp */\ |
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366 data += dp;\ |
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367 end_##op: |
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|
368 |
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369 // 1. 8-bit Data Transmission Commands. Group I |
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370 |
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371 ADDR_MODES_NO_DP( 0xE8 ) // MOV A,addr |
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372 a = nz = READ( 0, data ); |
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373 goto inc_pc_loop; |
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|
374 |
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375 case 0xBF:{// MOV A,(X)+ |
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376 int temp = x + dp; |
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377 x = (uint8_t) (x + 1); |
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378 a = nz = READ( -1, temp ); |
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379 goto loop; |
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|
380 } |
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381 |
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382 case 0xE8: // MOV A,imm |
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383 a = data; |
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384 nz = data; |
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385 goto inc_pc_loop; |
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386 |
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387 case 0xF9: // MOV X,dp+Y |
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388 data = (uint8_t) (data + y); |
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389 case 0xF8: // MOV X,dp |
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390 READ_DP_TIMER( 0, data, x = nz ); |
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391 goto inc_pc_loop; |
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392 |
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393 case 0xE9: // MOV X,abs |
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394 data = READ_PC16( pc ); |
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395 ++pc; |
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396 data = READ( 0, data ); |
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397 case 0xCD: // MOV X,imm |
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398 x = data; |
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399 nz = data; |
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400 goto inc_pc_loop; |
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401 |
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402 case 0xFB: // MOV Y,dp+X |
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403 data = (uint8_t) (data + x); |
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404 case 0xEB: // MOV Y,dp |
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405 // 70% from timer |
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406 pc++; |
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407 READ_DP_TIMER( 0, data, y = nz ); |
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408 goto loop; |
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409 |
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410 case 0xEC:{// MOV Y,abs |
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411 int temp = READ_PC16( pc ); |
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412 pc += 2; |
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413 READ_TIMER( 0, temp, y = nz ); |
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414 //y = nz = READ( 0, temp ); |
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415 goto loop; |
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416 } |
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417 |
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418 case 0x8D: // MOV Y,imm |
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419 y = data; |
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420 nz = data; |
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421 goto inc_pc_loop; |
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422 |
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423 // 2. 8-BIT DATA TRANSMISSION COMMANDS, GROUP 2 |
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424 |
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425 ADDR_MODES_NO_DP( 0xC8 ) // MOV addr,A |
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426 WRITE( 0, data, a ); |
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427 goto inc_pc_loop; |
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428 |
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429 { |
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430 int temp; |
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431 case 0xCC: // MOV abs,Y |
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432 temp = y; |
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433 goto mov_abs_temp; |
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434 case 0xC9: // MOV abs,X |
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435 temp = x; |
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436 mov_abs_temp: |
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437 WRITE( 0, READ_PC16( pc ), temp ); |
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438 pc += 2; |
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439 goto loop; |
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440 } |
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441 |
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442 case 0xD9: // MOV dp+Y,X |
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443 data = (uint8_t) (data + y); |
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444 case 0xD8: // MOV dp,X |
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445 WRITE( 0, data + dp, x ); |
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446 goto inc_pc_loop; |
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447 |
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448 case 0xDB: // MOV dp+X,Y |
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449 data = (uint8_t) (data + x); |
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450 case 0xCB: // MOV dp,Y |
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451 WRITE( 0, data + dp, y ); |
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452 goto inc_pc_loop; |
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453 |
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454 // 3. 8-BIT DATA TRANSMISSIN COMMANDS, GROUP 3. |
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455 |
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456 case 0x7D: // MOV A,X |
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457 a = x; |
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458 nz = x; |
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459 goto loop; |
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|
460 |
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461 case 0xDD: // MOV A,Y |
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462 a = y; |
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463 nz = y; |
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464 goto loop; |
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|
465 |
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466 case 0x5D: // MOV X,A |
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467 x = a; |
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468 nz = a; |
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469 goto loop; |
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|
470 |
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471 case 0xFD: // MOV Y,A |
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472 y = a; |
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473 nz = a; |
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|
474 goto loop; |
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|
475 |
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476 case 0x9D: // MOV X,SP |
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|
477 x = nz = GET_SP(); |
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|
478 goto loop; |
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|
479 |
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480 case 0xBD: // MOV SP,X |
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|
481 SET_SP( x ); |
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|
482 goto loop; |
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|
483 |
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484 //case 0xC6: // MOV (X),A (handled by MOV addr,A in group 2) |
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|
485 |
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486 case 0xAF: // MOV (X)+,A |
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487 WRITE_DP( 0, x, a + no_read_before_write ); |
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|
488 x++; |
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|
489 goto loop; |
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|
490 |
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|
491 // 5. 8-BIT LOGIC OPERATION COMMANDS |
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492 |
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493 #define LOGICAL_OP( op, func )\ |
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494 ADDR_MODES( op ) /* addr */\ |
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|
495 data = READ( 0, data );\ |
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496 case op: /* imm */\ |
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497 nz = a func##= data;\ |
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|
498 goto inc_pc_loop;\ |
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|
499 { unsigned addr;\ |
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500 case op + 0x11: /* X,Y */\ |
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501 data = READ_DP( -2, y );\ |
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|
502 addr = x + dp;\ |
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503 goto addr_##op;\ |
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504 case op + 0x01: /* dp,dp */\ |
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505 data = READ_DP( -3, data );\ |
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506 case op + 0x10:{/*dp,imm*/\ |
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507 uint8_t const* addr2 = pc + 1;\ |
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508 pc += 2;\ |
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509 addr = READ_PC( addr2 ) + dp;\ |
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|
510 }\ |
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511 addr_##op:\ |
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512 nz = data func READ( -1, addr );\ |
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513 WRITE( 0, addr, nz );\ |
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|
514 goto loop;\ |
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|
515 } |
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|
516 |
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517 LOGICAL_OP( 0x28, & ); // AND |
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|
518 |
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519 LOGICAL_OP( 0x08, | ); // OR |
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520 |
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521 LOGICAL_OP( 0x48, ^ ); // EOR |
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522 |
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523 // 4. 8-BIT ARITHMETIC OPERATION COMMANDS |
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|
524 |
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525 ADDR_MODES( 0x68 ) // CMP addr |
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|
526 data = READ( 0, data ); |
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527 case 0x68: // CMP imm |
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528 nz = a - data; |
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529 c = ~nz; |
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530 nz &= 0xFF; |
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531 goto inc_pc_loop; |
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532 |
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533 case 0x79: // CMP (X),(Y) |
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534 data = READ_DP( -2, y ); |
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535 nz = READ_DP( -1, x ) - data; |
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536 c = ~nz; |
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537 nz &= 0xFF; |
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538 goto loop; |
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539 |
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540 case 0x69: // CMP dp,dp |
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541 data = READ_DP( -3, data ); |
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542 case 0x78: // CMP dp,imm |
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543 nz = READ_DP( -1, READ_PC( ++pc ) ) - data; |
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544 c = ~nz; |
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545 nz &= 0xFF; |
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546 goto inc_pc_loop; |
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547 |
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548 case 0x3E: // CMP X,dp |
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549 data += dp; |
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550 goto cmp_x_addr; |
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551 case 0x1E: // CMP X,abs |
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552 data = READ_PC16( pc ); |
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553 pc++; |
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554 cmp_x_addr: |
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555 data = READ( 0, data ); |
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556 case 0xC8: // CMP X,imm |
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557 nz = x - data; |
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558 c = ~nz; |
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559 nz &= 0xFF; |
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560 goto inc_pc_loop; |
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|
561 |
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562 case 0x7E: // CMP Y,dp |
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563 data += dp; |
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564 goto cmp_y_addr; |
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565 case 0x5E: // CMP Y,abs |
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566 data = READ_PC16( pc ); |
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567 pc++; |
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568 cmp_y_addr: |
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569 data = READ( 0, data ); |
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570 case 0xAD: // CMP Y,imm |
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571 nz = y - data; |
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572 c = ~nz; |
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573 nz &= 0xFF; |
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574 goto inc_pc_loop; |
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|
575 |
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|
576 { |
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577 int addr; |
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578 case 0xB9: // SBC (x),(y) |
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579 case 0x99: // ADC (x),(y) |
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580 pc--; // compensate for inc later |
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581 data = READ_DP( -2, y ); |
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582 addr = x + dp; |
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583 goto adc_addr; |
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584 case 0xA9: // SBC dp,dp |
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585 case 0x89: // ADC dp,dp |
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586 data = READ_DP( -3, data ); |
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587 case 0xB8: // SBC dp,imm |
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588 case 0x98: // ADC dp,imm |
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589 addr = READ_PC( ++pc ) + dp; |
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590 adc_addr: |
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591 nz = READ( -1, addr ); |
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|
592 goto adc_data; |
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|
593 |
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|
594 // catch ADC and SBC together, then decode later based on operand |
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|
595 #undef CASE |
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596 #define CASE( n ) case n: case (n) + 0x20: |
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597 ADDR_MODES( 0x88 ) // ADC/SBC addr |
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598 data = READ( 0, data ); |
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599 case 0xA8: // SBC imm |
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|
600 case 0x88: // ADC imm |
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601 addr = -1; // A |
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|
602 nz = a; |
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|
603 adc_data: { |
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|
604 int flags; |
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605 if ( opcode >= 0xA0 ) // SBC |
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606 data ^= 0xFF; |
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|
607 |
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|
608 flags = data ^ nz; |
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609 nz += data + (c >> 8 & 1); |
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|
610 flags ^= nz; |
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|
611 |
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|
612 psw = (psw & ~(v40 | h08)) | |
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|
613 (flags >> 1 & h08) | |
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|
614 ((flags + 0x80) >> 2 & v40); |
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|
615 c = nz; |
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|
616 if ( addr < 0 ) |
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|
617 { |
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|
618 a = (uint8_t) nz; |
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|
619 goto inc_pc_loop; |
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|
620 } |
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|
621 WRITE( 0, addr, /*(uint8_t)*/ nz ); |
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|
622 goto inc_pc_loop; |
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|
623 } |
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|
624 |
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|
625 } |
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|
626 |
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|
627 // 6. ADDITION & SUBTRACTION COMMANDS |
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|
628 |
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|
629 #define INC_DEC_REG( reg, op )\ |
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|
630 nz = reg op;\ |
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|
631 reg = (uint8_t) nz;\ |
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|
632 goto loop; |
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|
633 |
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634 case 0xBC: INC_DEC_REG( a, + 1 ) // INC A |
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635 case 0x3D: INC_DEC_REG( x, + 1 ) // INC X |
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636 case 0xFC: INC_DEC_REG( y, + 1 ) // INC Y |
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|
637 |
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638 case 0x9C: INC_DEC_REG( a, - 1 ) // DEC A |
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639 case 0x1D: INC_DEC_REG( x, - 1 ) // DEC X |
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640 case 0xDC: INC_DEC_REG( y, - 1 ) // DEC Y |
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|
641 |
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|
642 case 0x9B: // DEC dp+X |
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|
643 case 0xBB: // INC dp+X |
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644 data = (uint8_t) (data + x); |
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|
645 case 0x8B: // DEC dp |
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|
646 case 0xAB: // INC dp |
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|
647 data += dp; |
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|
648 goto inc_abs; |
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|
649 case 0x8C: // DEC abs |
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|
650 case 0xAC: // INC abs |
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|
651 data = READ_PC16( pc ); |
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|
652 pc++; |
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|
653 inc_abs: |
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654 nz = (opcode >> 4 & 2) - 1; |
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|
655 nz += READ( -1, data ); |
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656 WRITE( 0, data, /*(uint8_t)*/ nz ); |
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|
657 goto inc_pc_loop; |
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|
658 |
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659 // 7. SHIFT, ROTATION COMMANDS |
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660 |
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661 case 0x5C: // LSR A |
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662 c = 0; |
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663 case 0x7C:{// ROR A |
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664 nz = (c >> 1 & 0x80) | (a >> 1); |
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665 c = a << 8; |
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666 a = nz; |
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667 goto loop; |
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668 } |
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669 |
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670 case 0x1C: // ASL A |
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671 c = 0; |
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672 case 0x3C:{// ROL A |
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673 int temp = c >> 8 & 1; |
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674 c = a << 1; |
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675 nz = c | temp; |
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676 a = (uint8_t) nz; |
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677 goto loop; |
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678 } |
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|
679 |
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680 case 0x0B: // ASL dp |
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681 c = 0; |
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682 data += dp; |
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683 goto rol_mem; |
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684 case 0x1B: // ASL dp+X |
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685 c = 0; |
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686 case 0x3B: // ROL dp+X |
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687 data = (uint8_t) (data + x); |
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688 case 0x2B: // ROL dp |
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689 data += dp; |
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690 goto rol_mem; |
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|
691 case 0x0C: // ASL abs |
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692 c = 0; |
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693 case 0x2C: // ROL abs |
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|
694 data = READ_PC16( pc ); |
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|
695 pc++; |
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|
696 rol_mem: |
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|
697 nz = c >> 8 & 1; |
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|
698 nz |= (c = READ( -1, data ) << 1); |
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699 WRITE( 0, data, /*(uint8_t)*/ nz ); |
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|
700 goto inc_pc_loop; |
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|
701 |
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|
702 case 0x4B: // LSR dp |
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|
703 c = 0; |
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|
704 data += dp; |
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|
705 goto ror_mem; |
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|
706 case 0x5B: // LSR dp+X |
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|
707 c = 0; |
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708 case 0x7B: // ROR dp+X |
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709 data = (uint8_t) (data + x); |
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|
710 case 0x6B: // ROR dp |
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|
711 data += dp; |
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|
712 goto ror_mem; |
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|
713 case 0x4C: // LSR abs |
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|
714 c = 0; |
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|
715 case 0x6C: // ROR abs |
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|
716 data = READ_PC16( pc ); |
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|
717 pc++; |
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|
718 ror_mem: { |
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|
719 int temp = READ( -1, data ); |
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720 nz = (c >> 1 & 0x80) | (temp >> 1); |
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721 c = temp << 8; |
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|
722 WRITE( 0, data, nz ); |
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|
723 goto inc_pc_loop; |
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|
724 } |
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|
725 |
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|
726 case 0x9F: // XCN |
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|
727 nz = a = (a >> 4) | (uint8_t) (a << 4); |
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|
728 goto loop; |
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diff
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|
729 |
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|
730 // 8. 16-BIT TRANSMISION COMMANDS |
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|
731 |
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|
732 case 0xBA: // MOVW YA,dp |
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|
733 a = READ_DP( -2, data ); |
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|
734 nz = (a & 0x7F) | (a >> 1); |
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|
735 y = READ_DP( 0, (uint8_t) (data + 1) ); |
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|
736 nz |= y; |
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|
737 goto inc_pc_loop; |
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|
738 |
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|
739 case 0xDA: // MOVW dp,YA |
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|
740 WRITE_DP( -1, data, a ); |
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|
741 WRITE_DP( 0, (uint8_t) (data + 1), y + no_read_before_write ); |
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|
742 goto inc_pc_loop; |
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|
743 |
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|
744 // 9. 16-BIT OPERATION COMMANDS |
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|
745 |
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|
746 case 0x3A: // INCW dp |
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|
747 case 0x1A:{// DECW dp |
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|
748 int temp; |
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|
749 // low byte |
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|
750 data += dp; |
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diff
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|
751 temp = READ( -3, data ); |
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|
752 temp += (opcode >> 4 & 2) - 1; // +1 for INCW, -1 for DECW |
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|
753 nz = ((temp >> 1) | temp) & 0x7F; |
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754 WRITE( -2, data, /*(uint8_t)*/ temp ); |
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|
755 |
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|
756 // high byte |
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|
757 data = (uint8_t) (data + 1) + dp; |
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|
758 temp = (uint8_t) ((temp >> 8) + READ( -1, data )); |
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|
759 nz |= temp; |
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|
760 WRITE( 0, data, temp ); |
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|
761 |
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|
762 goto inc_pc_loop; |
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|
763 } |
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|
764 |
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|
765 case 0x7A: // ADDW YA,dp |
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|
766 case 0x9A:{// SUBW YA,dp |
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|
767 int lo = READ_DP( -2, data ); |
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|
768 int hi = READ_DP( 0, (uint8_t) (data + 1) ); |
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|
769 int result; |
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changeset
|
770 int flags; |
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|
771 |
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|
772 if ( opcode == 0x9A ) // SUBW |
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|
773 { |
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|
774 lo = (lo ^ 0xFF) + 1; |
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|
775 hi ^= 0xFF; |
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|
776 } |
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|
777 |
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|
778 lo += a; |
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|
779 result = y + hi + (lo >> 8); |
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|
780 flags = hi ^ y ^ result; |
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diff
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|
781 |
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|
782 psw = (psw & ~(v40 | h08)) | |
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|
783 (flags >> 1 & h08) | |
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|
784 ((flags + 0x80) >> 2 & v40); |
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|
785 c = result; |
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|
786 a = (uint8_t) lo; |
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|
787 result = (uint8_t) result; |
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|
788 y = result; |
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|
789 nz = (((lo >> 1) | lo) & 0x7F) | result; |
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|
790 |
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|
791 goto inc_pc_loop; |
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792 } |
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|
793 |
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794 case 0x5A: { // CMPW YA,dp |
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795 int temp = a - READ_DP( -1, data ); |
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796 nz = ((temp >> 1) | temp) & 0x7F; |
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797 temp = y + (temp >> 8); |
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798 temp -= READ_DP( 0, (uint8_t) (data + 1) ); |
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799 nz |= temp; |
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800 c = ~temp; |
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|
801 nz &= 0xFF; |
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|
802 goto inc_pc_loop; |
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|
803 } |
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804 |
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805 // 10. MULTIPLICATION & DIVISON COMMANDS |
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806 |
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807 case 0xCF: { // MUL YA |
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|
808 unsigned temp = y * a; |
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|
809 a = (uint8_t) temp; |
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810 nz = ((temp >> 1) | temp) & 0x7F; |
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811 y = temp >> 8; |
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|
812 nz |= y; |
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|
813 goto loop; |
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|
814 } |
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|
815 |
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816 case 0x9E: // DIV YA,X |
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817 { |
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818 unsigned ya = y * 0x100 + a; |
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|
819 |
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820 psw &= ~(h08 | v40); |
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|
821 |
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|
822 if ( y >= x ) |
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|
823 psw |= v40; |
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|
824 |
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825 if ( (y & 15) >= (x & 15) ) |
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826 psw |= h08; |
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|
827 |
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|
828 if ( y < x * 2 ) |
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|
829 { |
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|
830 a = ya / x; |
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|
831 y = ya - a * x; |
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|
832 } |
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|
833 else |
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|
834 { |
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835 a = 255 - (ya - x * 0x200) / (256 - x); |
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836 y = x + (ya - x * 0x200) % (256 - x); |
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|
837 } |
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|
838 |
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|
839 nz = (uint8_t) a; |
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|
840 a = (uint8_t) a; |
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|
841 |
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|
842 goto loop; |
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|
843 } |
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|
844 |
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|
845 // 11. DECIMAL COMPENSATION COMMANDS |
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|
846 |
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|
847 case 0xDF: // DAA |
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|
848 SUSPICIOUS_OPCODE( "DAA" ); |
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849 if ( a > 0x99 || c & 0x100 ) |
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|
850 { |
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|
851 a += 0x60; |
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|
852 c = 0x100; |
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|
853 } |
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|
854 |
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|
855 if ( (a & 0x0F) > 9 || psw & h08 ) |
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|
856 a += 0x06; |
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diff
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|
857 |
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|
858 nz = a; |
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|
859 a = (uint8_t) a; |
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|
860 goto loop; |
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diff
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|
861 |
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|
862 case 0xBE: // DAS |
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|
863 SUSPICIOUS_OPCODE( "DAS" ); |
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|
864 if ( a > 0x99 || !(c & 0x100) ) |
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|
865 { |
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|
866 a -= 0x60; |
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|
867 c = 0; |
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|
868 } |
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diff
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|
869 |
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|
870 if ( (a & 0x0F) > 9 || !(psw & h08) ) |
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|
871 a -= 0x06; |
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diff
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|
872 |
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|
873 nz = a; |
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|
874 a = (uint8_t) a; |
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|
875 goto loop; |
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diff
changeset
|
876 |
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|
877 // 12. BRANCHING COMMANDS |
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|
878 |
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|
879 case 0x2F: // BRA rel |
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|
880 pc += (BOOST::int8_t) data; |
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|
881 goto inc_pc_loop; |
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diff
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|
882 |
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|
883 case 0x30: // BMI |
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|
884 BRANCH( (nz & nz_neg_mask) ) |
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|
885 |
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|
886 case 0x10: // BPL |
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|
887 BRANCH( !(nz & nz_neg_mask) ) |
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|
888 |
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|
889 case 0xB0: // BCS |
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|
890 BRANCH( c & 0x100 ) |
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|
891 |
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|
892 case 0x90: // BCC |
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|
893 BRANCH( !(c & 0x100) ) |
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|
894 |
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|
895 case 0x70: // BVS |
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|
896 BRANCH( psw & v40 ) |
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|
897 |
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|
898 case 0x50: // BVC |
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|
899 BRANCH( !(psw & v40) ) |
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|
900 |
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|
901 #define CBRANCH( cond )\ |
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|
902 {\ |
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|
903 pc++;\ |
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|
904 if ( cond )\ |
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|
905 goto cbranch_taken_loop;\ |
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|
906 rel_time -= 2;\ |
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|
907 goto inc_pc_loop;\ |
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|
908 } |
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|
909 |
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|
910 case 0x03: // BBS dp.bit,rel |
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|
911 case 0x23: |
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|
912 case 0x43: |
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|
913 case 0x63: |
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|
914 case 0x83: |
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|
915 case 0xA3: |
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|
916 case 0xC3: |
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|
917 case 0xE3: |
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|
918 CBRANCH( READ_DP( -4, data ) >> (opcode >> 5) & 1 ) |
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|
919 |
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|
920 case 0x13: // BBC dp.bit,rel |
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|
921 case 0x33: |
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|
922 case 0x53: |
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|
923 case 0x73: |
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|
924 case 0x93: |
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|
925 case 0xB3: |
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|
926 case 0xD3: |
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|
927 case 0xF3: |
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928 CBRANCH( !(READ_DP( -4, data ) >> (opcode >> 5) & 1) ) |
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|
929 |
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|
930 case 0xDE: // CBNE dp+X,rel |
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|
931 data = (uint8_t) (data + x); |
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|
932 // fall through |
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|
933 case 0x2E:{// CBNE dp,rel |
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diff
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|
934 int temp; |
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diff
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|
935 // 61% from timer |
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|
936 READ_DP_TIMER( -4, data, temp ); |
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|
937 CBRANCH( temp != a ) |
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|
938 } |
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|
939 |
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|
940 case 0x6E: { // DBNZ dp,rel |
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|
941 unsigned temp = READ_DP( -4, data ) - 1; |
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942 WRITE_DP( -3, (uint8_t) data, /*(uint8_t)*/ temp + no_read_before_write ); |
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|
943 CBRANCH( temp ) |
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|
944 } |
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|
945 |
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|
946 case 0xFE: // DBNZ Y,rel |
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|
947 y = (uint8_t) (y - 1); |
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|
948 BRANCH( y ) |
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|
949 |
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|
950 case 0x1F: // JMP [abs+X] |
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|
951 SET_PC( READ_PC16( pc ) + x ); |
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|
952 // fall through |
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|
953 case 0x5F: // JMP abs |
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|
954 SET_PC( READ_PC16( pc ) ); |
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|
955 goto loop; |
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|
956 |
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|
957 // 13. SUB-ROUTINE CALL RETURN COMMANDS |
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|
958 |
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|
959 case 0x0F:{// BRK |
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|
960 int temp; |
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|
961 int ret_addr = GET_PC(); |
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|
962 SUSPICIOUS_OPCODE( "BRK" ); |
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|
963 SET_PC( READ_PROG16( 0xFFDE ) ); // vector address verified |
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|
964 PUSH16( ret_addr ); |
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|
965 GET_PSW( temp ); |
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|
966 psw = (psw | b10) & ~i04; |
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|
967 PUSH( temp ); |
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diff
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|
968 goto loop; |
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diff
changeset
|
969 } |
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|
970 |
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|
971 case 0x4F:{// PCALL offset |
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|
972 int ret_addr = GET_PC() + 1; |
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|
973 SET_PC( 0xFF00 | data ); |
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|
974 PUSH16( ret_addr ); |
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|
975 goto loop; |
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|
976 } |
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|
977 |
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|
978 case 0x01: // TCALL n |
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diff
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|
979 case 0x11: |
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|
980 case 0x21: |
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|
981 case 0x31: |
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|
982 case 0x41: |
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|
983 case 0x51: |
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|
984 case 0x61: |
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|
985 case 0x71: |
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|
986 case 0x81: |
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|
987 case 0x91: |
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|
988 case 0xA1: |
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|
989 case 0xB1: |
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|
990 case 0xC1: |
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|
991 case 0xD1: |
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|
992 case 0xE1: |
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|
993 case 0xF1: { |
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diff
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|
994 int ret_addr = GET_PC(); |
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|
995 SET_PC( READ_PROG16( 0xFFDE - (opcode >> 3) ) ); |
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[svn] - upstream updates regarding handling of SPC700 instructions and runtime
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|
996 PUSH16( ret_addr ); |
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[svn] - upstream updates regarding handling of SPC700 instructions and runtime
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|
997 goto loop; |
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|
998 } |
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|
999 |
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|
1000 // 14. STACK OPERATION COMMANDS |
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|
1001 |
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|
1002 { |
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|
1003 int temp; |
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|
1004 case 0x7F: // RET1 |
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|
1005 temp = *sp; |
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|
1006 SET_PC( GET_LE16( sp + 1 ) ); |
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|
1007 sp += 3; |
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|
1008 goto set_psw; |
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|
1009 case 0x8E: // POP PSW |
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|
1010 POP( temp ); |
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|
1011 set_psw: |
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[svn] - upstream updates regarding handling of SPC700 instructions and runtime
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|
1012 SET_PSW( temp ); |
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[svn] - upstream updates regarding handling of SPC700 instructions and runtime
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|
1013 goto loop; |
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|
1014 } |
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|
1015 |
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|
1016 case 0x0D: { // PUSH PSW |
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|
1017 int temp; |
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|
1018 GET_PSW( temp ); |
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|
1019 PUSH( temp ); |
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|
1020 goto loop; |
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|
1021 } |
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|
1022 |
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|
1023 case 0x2D: // PUSH A |
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|
1024 PUSH( a ); |
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|
1025 goto loop; |
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|
1026 |
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|
1027 case 0x4D: // PUSH X |
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|
1028 PUSH( x ); |
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diff
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|
1029 goto loop; |
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|
1030 |
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|
1031 case 0x6D: // PUSH Y |
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|
1032 PUSH( y ); |
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diff
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|
1033 goto loop; |
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|
1034 |
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diff
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|
1035 case 0xAE: // POP A |
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diff
changeset
|
1036 POP( a ); |
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diff
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|
1037 goto loop; |
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diff
changeset
|
1038 |
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341
diff
changeset
|
1039 case 0xCE: // POP X |
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parents:
341
diff
changeset
|
1040 POP( x ); |
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diff
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|
1041 goto loop; |
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diff
changeset
|
1042 |
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diff
changeset
|
1043 case 0xEE: // POP Y |
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diff
changeset
|
1044 POP( y ); |
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diff
changeset
|
1045 goto loop; |
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diff
changeset
|
1046 |
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diff
changeset
|
1047 // 15. BIT OPERATION COMMANDS |
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diff
changeset
|
1048 |
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diff
changeset
|
1049 case 0x02: // SET1 |
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341
diff
changeset
|
1050 case 0x22: |
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[svn] - upstream updates regarding handling of SPC700 instructions and runtime
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341
diff
changeset
|
1051 case 0x42: |
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[svn] - upstream updates regarding handling of SPC700 instructions and runtime
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341
diff
changeset
|
1052 case 0x62: |
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[svn] - upstream updates regarding handling of SPC700 instructions and runtime
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341
diff
changeset
|
1053 case 0x82: |
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[svn] - upstream updates regarding handling of SPC700 instructions and runtime
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parents:
341
diff
changeset
|
1054 case 0xA2: |
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[svn] - upstream updates regarding handling of SPC700 instructions and runtime
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341
diff
changeset
|
1055 case 0xC2: |
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[svn] - upstream updates regarding handling of SPC700 instructions and runtime
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parents:
341
diff
changeset
|
1056 case 0xE2: |
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[svn] - upstream updates regarding handling of SPC700 instructions and runtime
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diff
changeset
|
1057 case 0x12: // CLR1 |
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diff
changeset
|
1058 case 0x32: |
c31e94fefd2a
[svn] - upstream updates regarding handling of SPC700 instructions and runtime
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341
diff
changeset
|
1059 case 0x52: |
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diff
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|
1060 case 0x72: |
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|
1061 case 0x92: |
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|
1062 case 0xB2: |
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|
1063 case 0xD2: |
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|
1064 case 0xF2: { |
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|
1065 int bit = 1 << (opcode >> 5); |
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|
1066 int mask = ~bit; |
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diff
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|
1067 if ( opcode & 0x10 ) |
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|
1068 bit = 0; |
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|
1069 data += dp; |
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|
1070 WRITE( 0, data, (READ( -1, data ) & mask) | bit ); |
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|
1071 goto inc_pc_loop; |
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|
1072 } |
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|
1073 |
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|
1074 case 0x0E: // TSET1 abs |
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|
1075 case 0x4E: // TCLR1 abs |
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|
1076 data = READ_PC16( pc ); |
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|
1077 pc += 2; |
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|
1078 { |
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|
1079 unsigned temp = READ( -2, data ); |
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|
1080 nz = (uint8_t) (a - temp); |
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|
1081 temp &= ~a; |
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diff
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|
1082 if ( opcode == 0x0E ) |
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|
1083 temp |= a; |
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diff
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|
1084 WRITE( 0, data, temp ); |
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diff
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|
1085 } |
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diff
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|
1086 goto loop; |
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diff
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|
1087 |
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diff
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|
1088 case 0x4A: // AND1 C,mem.bit |
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|
1089 c &= MEM_BIT( 0 ); |
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diff
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|
1090 pc += 2; |
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diff
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|
1091 goto loop; |
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diff
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|
1092 |
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diff
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|
1093 case 0x6A: // AND1 C,/mem.bit |
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|
1094 c &= ~MEM_BIT( 0 ); |
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diff
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|
1095 pc += 2; |
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341
diff
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|
1096 goto loop; |
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diff
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|
1097 |
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diff
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|
1098 case 0x0A: // OR1 C,mem.bit |
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|
1099 c |= MEM_BIT( -1 ); |
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diff
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|
1100 pc += 2; |
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diff
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|
1101 goto loop; |
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diff
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|
1102 |
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|
1103 case 0x2A: // OR1 C,/mem.bit |
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|
1104 c |= ~MEM_BIT( -1 ); |
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diff
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|
1105 pc += 2; |
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diff
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|
1106 goto loop; |
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diff
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|
1107 |
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|
1108 case 0x8A: // EOR1 C,mem.bit |
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|
1109 c ^= MEM_BIT( -1 ); |
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|
1110 pc += 2; |
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diff
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|
1111 goto loop; |
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diff
changeset
|
1112 |
c31e94fefd2a
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|
1113 case 0xEA: // NOT1 mem.bit |
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diff
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|
1114 data = READ_PC16( pc ); |
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341
diff
changeset
|
1115 pc += 2; |
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diff
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|
1116 { |
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|
1117 unsigned temp = READ( -1, data & 0x1FFF ); |
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diff
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|
1118 temp ^= 1 << (data >> 13); |
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|
1119 WRITE( 0, data & 0x1FFF, temp ); |
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diff
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|
1120 } |
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341
diff
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|
1121 goto loop; |
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parents:
341
diff
changeset
|
1122 |
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341
diff
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|
1123 case 0xCA: // MOV1 mem.bit,C |
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diff
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|
1124 data = READ_PC16( pc ); |
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341
diff
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|
1125 pc += 2; |
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diff
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|
1126 { |
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diff
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|
1127 unsigned temp = READ( -2, data & 0x1FFF ); |
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diff
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|
1128 unsigned bit = data >> 13; |
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diff
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|
1129 temp = (temp & ~(1 << bit)) | ((c >> 8 & 1) << bit); |
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|
1130 WRITE( 0, data & 0x1FFF, temp + no_read_before_write ); |
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341
diff
changeset
|
1131 } |
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341
diff
changeset
|
1132 goto loop; |
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341
diff
changeset
|
1133 |
c31e94fefd2a
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341
diff
changeset
|
1134 case 0xAA: // MOV1 C,mem.bit |
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341
diff
changeset
|
1135 c = MEM_BIT( 0 ); |
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parents:
341
diff
changeset
|
1136 pc += 2; |
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parents:
341
diff
changeset
|
1137 goto loop; |
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parents:
341
diff
changeset
|
1138 |
c31e94fefd2a
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341
diff
changeset
|
1139 // 16. PROGRAM PSW FLAG OPERATION COMMANDS |
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341
diff
changeset
|
1140 |
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parents:
341
diff
changeset
|
1141 case 0x60: // CLRC |
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parents:
341
diff
changeset
|
1142 c = 0; |
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parents:
341
diff
changeset
|
1143 goto loop; |
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parents:
341
diff
changeset
|
1144 |
c31e94fefd2a
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parents:
341
diff
changeset
|
1145 case 0x80: // SETC |
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parents:
341
diff
changeset
|
1146 c = ~0; |
c31e94fefd2a
[svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents:
341
diff
changeset
|
1147 goto loop; |
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parents:
341
diff
changeset
|
1148 |
c31e94fefd2a
[svn] - upstream updates regarding handling of SPC700 instructions and runtime
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parents:
341
diff
changeset
|
1149 case 0xED: // NOTC |
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parents:
341
diff
changeset
|
1150 c ^= 0x100; |
c31e94fefd2a
[svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents:
341
diff
changeset
|
1151 goto loop; |
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[svn] - upstream updates regarding handling of SPC700 instructions and runtime
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parents:
341
diff
changeset
|
1152 |
c31e94fefd2a
[svn] - upstream updates regarding handling of SPC700 instructions and runtime
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parents:
341
diff
changeset
|
1153 case 0xE0: // CLRV |
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341
diff
changeset
|
1154 psw &= ~(v40 | h08); |
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[svn] - upstream updates regarding handling of SPC700 instructions and runtime
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parents:
341
diff
changeset
|
1155 goto loop; |
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[svn] - upstream updates regarding handling of SPC700 instructions and runtime
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parents:
341
diff
changeset
|
1156 |
c31e94fefd2a
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parents:
341
diff
changeset
|
1157 case 0x20: // CLRP |
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341
diff
changeset
|
1158 dp = 0; |
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parents:
341
diff
changeset
|
1159 goto loop; |
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parents:
341
diff
changeset
|
1160 |
c31e94fefd2a
[svn] - upstream updates regarding handling of SPC700 instructions and runtime
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parents:
341
diff
changeset
|
1161 case 0x40: // SETP |
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parents:
341
diff
changeset
|
1162 dp = 0x100; |
c31e94fefd2a
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parents:
341
diff
changeset
|
1163 goto loop; |
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parents:
341
diff
changeset
|
1164 |
c31e94fefd2a
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parents:
341
diff
changeset
|
1165 case 0xA0: // EI |
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341
diff
changeset
|
1166 SUSPICIOUS_OPCODE( "EI" ); |
c31e94fefd2a
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341
diff
changeset
|
1167 psw |= i04; |
c31e94fefd2a
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parents:
341
diff
changeset
|
1168 goto loop; |
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parents:
341
diff
changeset
|
1169 |
c31e94fefd2a
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parents:
341
diff
changeset
|
1170 case 0xC0: // DI |
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341
diff
changeset
|
1171 SUSPICIOUS_OPCODE( "DI" ); |
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[svn] - upstream updates regarding handling of SPC700 instructions and runtime
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parents:
341
diff
changeset
|
1172 psw &= ~i04; |
c31e94fefd2a
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nenolod
parents:
341
diff
changeset
|
1173 goto loop; |
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[svn] - upstream updates regarding handling of SPC700 instructions and runtime
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parents:
341
diff
changeset
|
1174 |
c31e94fefd2a
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parents:
341
diff
changeset
|
1175 // 17. OTHER COMMANDS |
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parents:
341
diff
changeset
|
1176 |
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parents:
341
diff
changeset
|
1177 case 0x00: // NOP |
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parents:
341
diff
changeset
|
1178 goto loop; |
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[svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents:
341
diff
changeset
|
1179 |
c31e94fefd2a
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nenolod
parents:
341
diff
changeset
|
1180 case 0xFF:{// STOP |
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parents:
341
diff
changeset
|
1181 // handle PC wrap-around |
c31e94fefd2a
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parents:
341
diff
changeset
|
1182 unsigned addr = GET_PC() - 1; |
c31e94fefd2a
[svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents:
341
diff
changeset
|
1183 if ( addr >= 0x10000 ) |
c31e94fefd2a
[svn] - upstream updates regarding handling of SPC700 instructions and runtime
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parents:
341
diff
changeset
|
1184 { |
c31e94fefd2a
[svn] - upstream updates regarding handling of SPC700 instructions and runtime
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parents:
341
diff
changeset
|
1185 addr &= 0xFFFF; |
c31e94fefd2a
[svn] - upstream updates regarding handling of SPC700 instructions and runtime
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parents:
341
diff
changeset
|
1186 SET_PC( addr ); |
c31e94fefd2a
[svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents:
341
diff
changeset
|
1187 dprintf( "SPC: PC wrapped around\n" ); |
c31e94fefd2a
[svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents:
341
diff
changeset
|
1188 goto loop; |
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[svn] - upstream updates regarding handling of SPC700 instructions and runtime
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parents:
341
diff
changeset
|
1189 } |
c31e94fefd2a
[svn] - upstream updates regarding handling of SPC700 instructions and runtime
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parents:
341
diff
changeset
|
1190 } |
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341
diff
changeset
|
1191 // fall through |
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parents:
341
diff
changeset
|
1192 case 0xEF: // SLEEP |
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parents:
341
diff
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|
1193 SUSPICIOUS_OPCODE( "STOP/SLEEP" ); |
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[svn] - upstream updates regarding handling of SPC700 instructions and runtime
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1194 --pc; |
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1195 rel_time = 0; |
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1196 m.cpu_error = "SPC emulation error"; |
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1197 goto stop; |
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1198 } // switch |
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1199 |
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1200 assert( 0 ); // catch any unhandled instructions |
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1201 } |
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1202 out_of_time: |
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1203 rel_time -= m.cycle_table [*pc]; // undo partial execution of opcode |
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1204 stop: |
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1205 |
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1206 // Uncache registers |
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1207 if ( GET_PC() >= 0x10000 ) |
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1208 dprintf( "SPC: PC wrapped around\n" ); |
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1209 m.cpu_regs.pc = (uint16_t) GET_PC(); |
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1210 m.cpu_regs.sp = ( uint8_t) GET_SP(); |
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1211 m.cpu_regs.a = ( uint8_t) a; |
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1212 m.cpu_regs.x = ( uint8_t) x; |
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1213 m.cpu_regs.y = ( uint8_t) y; |
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1214 { |
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1215 int temp; |
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1216 GET_PSW( temp ); |
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1217 m.cpu_regs.psw = (uint8_t) temp; |
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1218 } |
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1219 } |
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1220 SPC_CPU_RUN_FUNC_END |