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2961
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1 /* Copyright (C) 2006 yopyop
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2 yopyop156@ifrance.com
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3 yopyop156.ifrance.com
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4
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5 This file is part of DeSmuME
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6
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7 DeSmuME is free software; you can redistribute it and/or modify
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8 it under the terms of the GNU General Public License as published by
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9 the Free Software Foundation; either version 2 of the License, or
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10 (at your option) any later version.
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11
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12 DeSmuME is distributed in the hope that it will be useful,
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13 but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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15 GNU General Public License for more details.
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16
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17 You should have received a copy of the GNU General Public License
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18 along with DeSmuME; if not, write to the Free Software
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19 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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20 */
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21
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22 #ifndef __CP15_H__
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23 #define __CP15_H__
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24
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25 #include "armcpu.h"
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26
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27 typedef struct
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28 {
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29 u32 IDCode;
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30 u32 cacheType;
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31 u32 TCMSize;
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32 u32 ctrl;
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33 u32 DCConfig;
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34 u32 ICConfig;
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35 u32 writeBuffCtrl;
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36 u32 und;
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37 u32 DaccessPerm;
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38 u32 IaccessPerm;
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39 u32 protectBaseSize0;
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40 u32 protectBaseSize1;
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41 u32 protectBaseSize2;
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42 u32 protectBaseSize3;
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43 u32 protectBaseSize4;
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44 u32 protectBaseSize5;
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45 u32 protectBaseSize6;
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46 u32 protectBaseSize7;
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47 u32 cacheOp;
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48 u32 DcacheLock;
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49 u32 IcacheLock;
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50 u32 ITCMRegion;
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51 u32 DTCMRegion;
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52 u32 processID;
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53 u32 RAM_TAG;
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54 u32 testState;
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55 u32 cacheDbg;
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56 /* calculated bitmasks for the regions to decide rights uppon */
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57 /* calculation is done in the MCR instead of on mem access for performance */
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58 u32 regionWriteMask_USR[8] ;
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59 u32 regionWriteMask_SYS[8] ;
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60 u32 regionReadMask_USR[8] ;
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61 u32 regionReadMask_SYS[8] ;
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62 u32 regionExecuteMask_USR[8] ;
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63 u32 regionExecuteMask_SYS[8] ;
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64 u32 regionWriteSet_USR[8] ;
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65 u32 regionWriteSet_SYS[8] ;
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66 u32 regionReadSet_USR[8] ;
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67 u32 regionReadSet_SYS[8] ;
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68 u32 regionExecuteSet_USR[8] ;
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69 u32 regionExecuteSet_SYS[8] ;
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70
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71 armcpu_t * cpu;
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72
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73 } armcp15_t;
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74
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75 armcp15_t *armcp15_new(armcpu_t *c);
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76 BOOL armcp15_dataProcess(armcp15_t *armcp15, u8 CRd, u8 CRn, u8 CRm, u8 opcode1, u8 opcode2);
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77 BOOL armcp15_load(armcp15_t *armcp15, u8 CRd, u8 adr);
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78 BOOL armcp15_store(armcp15_t *armcp15, u8 CRd, u8 adr);
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79 BOOL armcp15_moveCP2ARM(armcp15_t *armcp15, u32 * R, u8 CRn, u8 CRm, u8 opcode1, u8 opcode2);
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80 BOOL armcp15_moveARM2CP(armcp15_t *armcp15, u32 val, u8 CRn, u8 CRm, u8 opcode1, u8 opcode2);
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81 INLINE BOOL armcp15_isAccessAllowed(armcp15_t *armcp15,u32 address,u32 access) ;
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82
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83
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84 #define CP15_ACCESS_WRITE 0
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85 #define CP15_ACCESS_READ 2
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86 #define CP15_ACCESS_EXECUTE 4
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87 #define CP15_ACCESS_WRITEUSR CP15_ACCESS_WRITE
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88 #define CP15_ACCESS_WRITESYS 1
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89 #define CP15_ACCESS_READUSR CP15_ACCESS_READ
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90 #define CP15_ACCESS_READSYS 3
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91 #define CP15_ACCESS_EXECUSR CP15_ACCESS_EXECUTE
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92 #define CP15_ACCESS_EXECSYS 5
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93
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94 #endif /* __CP15_H__*/
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