Mercurial > audlegacy-plugins
annotate src/console/Spc_Cpu.cxx @ 3030:c442f8407dcb
Show playlist popup information reliably (Debian bug #460802)
author | John Lindgren <john.lindgren@tds.net> |
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date | Fri, 10 Apr 2009 01:46:08 -0400 |
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1 // Core SPC emulation: CPU, timers, SMP registers, memory |
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2 |
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3 // snes_spc 0.9.0. http://www.slack.net/~ant/ |
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4 |
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5 #include "Snes_Spc.h" |
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6 |
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7 #include <string.h> |
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8 |
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9 /* Copyright (C) 2004-2007 Shay Green. This module is free software; you |
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10 can redistribute it and/or modify it under the terms of the GNU Lesser |
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11 General Public License as published by the Free Software Foundation; either |
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12 version 2.1 of the License, or (at your option) any later version. This |
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13 module is distributed in the hope that it will be useful, but WITHOUT ANY |
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14 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS |
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15 FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more |
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16 details. You should have received a copy of the GNU Lesser General Public |
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17 License along with this module; if not, write to the Free Software Foundation, |
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18 Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ |
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19 |
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20 #include "blargg_source.h" |
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21 |
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22 #define RAM (m.ram.ram) |
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23 #define REGS (m.smp_regs [0]) |
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24 #define REGS_IN (m.smp_regs [1]) |
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25 |
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26 // (n ? n : 256) |
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27 #define IF_0_THEN_256( n ) ((uint8_t) ((n) - 1) + 1) |
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28 |
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29 // Note: SPC_MORE_ACCURACY exists mainly so I can run my validation tests, which |
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30 // do crazy echo buffer accesses. |
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31 #ifndef SPC_MORE_ACCURACY |
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32 #define SPC_MORE_ACCURACY 0 |
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33 #endif |
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34 |
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35 #ifdef BLARGG_ENABLE_OPTIMIZER |
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36 #include BLARGG_ENABLE_OPTIMIZER |
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37 #endif |
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38 |
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39 |
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40 //// Timers |
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41 |
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42 #if SPC_DISABLE_TEMPO |
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43 #define TIMER_DIV( t, n ) ((n) >> t->prescaler) |
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44 #define TIMER_MUL( t, n ) ((n) << t->prescaler) |
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45 #else |
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46 #define TIMER_DIV( t, n ) ((n) / t->prescaler) |
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47 #define TIMER_MUL( t, n ) ((n) * t->prescaler) |
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48 #endif |
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49 |
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50 Snes_Spc::Timer* Snes_Spc::run_timer_( Timer* t, rel_time_t time ) |
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51 { |
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52 int elapsed = TIMER_DIV( t, time - t->next_time ) + 1; |
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53 t->next_time += TIMER_MUL( t, elapsed ); |
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54 |
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55 if ( t->enabled ) |
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56 { |
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57 int remain = IF_0_THEN_256( t->period - t->divider ); |
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58 int divider = t->divider + elapsed; |
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59 int over = elapsed - remain; |
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60 if ( over >= 0 ) |
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61 { |
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62 int n = over / t->period; |
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63 t->counter = (t->counter + 1 + n) & 0x0F; |
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64 divider = over - n * t->period; |
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65 } |
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66 t->divider = (uint8_t) divider; |
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67 } |
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68 return t; |
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69 } |
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70 |
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71 inline Snes_Spc::Timer* Snes_Spc::run_timer( Timer* t, rel_time_t time ) |
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72 { |
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73 if ( time >= t->next_time ) |
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74 t = run_timer_( t, time ); |
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75 return t; |
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76 } |
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77 |
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78 |
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79 //// ROM |
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80 |
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81 void Snes_Spc::enable_rom( int enable ) |
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82 { |
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83 if ( m.rom_enabled != enable ) |
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84 { |
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85 m.rom_enabled = enable; |
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86 if ( enable ) |
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87 memcpy( m.hi_ram, &RAM [rom_addr], sizeof m.hi_ram ); |
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88 memcpy( &RAM [rom_addr], (enable ? m.rom : m.hi_ram), rom_size ); |
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89 // TODO: ROM can still get overwritten when DSP writes to echo buffer |
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90 } |
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91 } |
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92 |
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93 |
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94 //// DSP |
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95 |
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96 #if SPC_LESS_ACCURATE |
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97 int const max_reg_time = 29; |
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98 |
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99 signed char const Snes_Spc::reg_times_ [256] = |
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100 { |
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101 -1, 0,-11,-10,-15,-11, -2, -2, 4, 3, 14, 14, 26, 26, 14, 22, |
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102 2, 3, 0, 1,-12, 0, 1, 1, 7, 6, 14, 14, 27, 14, 14, 23, |
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103 5, 6, 3, 4, -1, 3, 4, 4, 10, 9, 14, 14, 26, -5, 14, 23, |
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104 8, 9, 6, 7, 2, 6, 7, 7, 13, 12, 14, 14, 27, -4, 14, 24, |
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105 11, 12, 9, 10, 5, 9, 10, 10, 16, 15, 14, 14, -2, -4, 14, 24, |
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106 14, 15, 12, 13, 8, 12, 13, 13, 19, 18, 14, 14, -2,-36, 14, 24, |
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107 17, 18, 15, 16, 11, 15, 16, 16, 22, 21, 14, 14, 28, -3, 14, 25, |
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108 20, 21, 18, 19, 14, 18, 19, 19, 25, 24, 14, 14, 14, 29, 14, 25, |
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109 |
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110 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, |
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111 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, |
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112 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, |
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113 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, |
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114 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, |
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115 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, |
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116 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, |
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117 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, |
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118 }; |
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119 |
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120 #define RUN_DSP( time, offset ) \ |
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121 int count = (time) - (offset) - m.dsp_time;\ |
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122 if ( count >= 0 )\ |
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123 {\ |
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124 int clock_count = (count & ~(clocks_per_sample - 1)) + clocks_per_sample;\ |
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125 m.dsp_time += clock_count;\ |
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126 dsp.run( clock_count );\ |
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127 } |
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128 #else |
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129 #define RUN_DSP( time, offset ) \ |
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130 {\ |
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131 int count = (time) - m.dsp_time;\ |
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132 if ( !SPC_MORE_ACCURACY || count )\ |
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133 {\ |
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134 assert( count > 0 );\ |
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135 m.dsp_time = (time);\ |
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136 dsp.run( count );\ |
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137 }\ |
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138 } |
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139 #endif |
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140 |
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141 int Snes_Spc::dsp_read( rel_time_t time ) |
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142 { |
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143 RUN_DSP( time, reg_times [REGS [r_dspaddr] & 0x7F] ); |
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144 |
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145 int result = dsp.read( REGS [r_dspaddr] & 0x7F ); |
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146 |
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147 #ifdef SPC_DSP_READ_HOOK |
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148 SPC_DSP_READ_HOOK( spc_time + time, (REGS [r_dspaddr] & 0x7F), result ); |
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149 #endif |
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150 |
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151 return result; |
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152 } |
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153 |
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154 inline void Snes_Spc::dsp_write( int data, rel_time_t time ) |
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155 { |
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156 RUN_DSP( time, reg_times [REGS [r_dspaddr]] ) |
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157 #if SPC_LESS_ACCURATE |
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158 else if ( m.dsp_time == skipping_time ) |
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159 { |
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160 int r = REGS [r_dspaddr]; |
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161 if ( r == Spc_Dsp::r_kon ) |
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162 m.skipped_kon |= data & ~dsp.read( Spc_Dsp::r_koff ); |
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163 |
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164 if ( r == Spc_Dsp::r_koff ) |
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165 { |
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166 m.skipped_koff |= data; |
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167 m.skipped_kon &= ~data; |
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168 } |
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169 } |
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170 #endif |
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171 |
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172 #ifdef SPC_DSP_WRITE_HOOK |
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173 SPC_DSP_WRITE_HOOK( m.spc_time + time, REGS [r_dspaddr], (uint8_t) data ); |
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174 #endif |
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175 |
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176 if ( REGS [r_dspaddr] <= 0x7F ) |
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177 dsp.write( REGS [r_dspaddr], data ); |
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178 else if ( !SPC_MORE_ACCURACY ) |
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179 dprintf( "SPC wrote to DSP register > $7F\n" ); |
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180 } |
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181 |
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182 |
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183 //// Memory access extras |
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184 |
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185 #if SPC_MORE_ACCURACY |
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186 #define MEM_ACCESS( time, addr ) \ |
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187 {\ |
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188 if ( time >= m.dsp_time )\ |
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189 {\ |
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190 RUN_DSP( time, max_reg_time );\ |
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191 }\ |
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192 } |
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193 #elif !defined (NDEBUG) |
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194 // Debug-only check for read/write within echo buffer, since this might result in |
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195 // inaccurate emulation due to the DSP not being caught up to the present. |
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196 |
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197 bool Snes_Spc::check_echo_access( int addr ) |
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198 { |
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199 if ( !(dsp.read( Spc_Dsp::r_flg ) & 0x20) ) |
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200 { |
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201 int start = 0x100 * dsp.read( Spc_Dsp::r_esa ); |
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202 int size = 0x800 * (dsp.read( Spc_Dsp::r_edl ) & 0x0F); |
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203 int end = start + (size ? size : 4); |
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204 if ( start <= addr && addr < end ) |
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205 { |
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206 if ( !m.echo_accessed ) |
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207 { |
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208 m.echo_accessed = 1; |
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209 return true; |
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210 } |
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211 } |
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212 } |
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213 return false; |
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214 } |
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215 |
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216 #define MEM_ACCESS( time, addr ) check( !check_echo_access( (uint16_t) addr ) ); |
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217 #else |
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218 #define MEM_ACCESS( time, addr ) |
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219 #endif |
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220 |
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221 |
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222 //// CPU write |
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223 |
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224 #if SPC_MORE_ACCURACY |
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225 static unsigned char const glitch_probs [3] [256] = |
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226 { |
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227 0xC3,0x92,0x5B,0x1C,0xD1,0x92,0x5B,0x1C,0xDB,0x9C,0x72,0x18,0xCD,0x5C,0x38,0x0B, |
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228 0xE1,0x9C,0x74,0x17,0xCF,0x75,0x45,0x0C,0xCF,0x6E,0x4A,0x0D,0xA3,0x3A,0x1D,0x08, |
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229 0xDB,0xA0,0x82,0x19,0xD9,0x73,0x3C,0x0E,0xCB,0x76,0x52,0x0B,0xA5,0x46,0x1D,0x09, |
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230 0xDA,0x74,0x55,0x0F,0xA2,0x3F,0x21,0x05,0x9A,0x40,0x20,0x07,0x63,0x1E,0x10,0x01, |
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231 0xDF,0xA9,0x85,0x1D,0xD3,0x84,0x4B,0x0E,0xCF,0x6F,0x49,0x0F,0xB3,0x48,0x1E,0x05, |
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232 0xD8,0x77,0x52,0x12,0xB7,0x49,0x23,0x06,0xAA,0x45,0x28,0x07,0x7D,0x28,0x0F,0x07, |
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233 0xCC,0x7B,0x4A,0x0E,0xB2,0x4F,0x24,0x07,0xAD,0x43,0x2C,0x06,0x86,0x29,0x11,0x07, |
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234 0xAE,0x48,0x1F,0x0A,0x76,0x21,0x19,0x05,0x76,0x21,0x14,0x05,0x44,0x11,0x0B,0x01, |
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235 0xE7,0xAD,0x96,0x23,0xDC,0x86,0x59,0x0E,0xDC,0x7C,0x5F,0x15,0xBB,0x53,0x2E,0x09, |
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236 0xD6,0x7C,0x4A,0x16,0xBB,0x4A,0x25,0x08,0xB3,0x4F,0x28,0x0B,0x8E,0x23,0x15,0x08, |
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237 0xCF,0x7F,0x57,0x11,0xB5,0x4A,0x23,0x0A,0xAA,0x42,0x28,0x05,0x7D,0x22,0x12,0x03, |
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238 0xA6,0x49,0x28,0x09,0x82,0x2B,0x0D,0x04,0x7A,0x20,0x0F,0x04,0x3D,0x0F,0x09,0x03, |
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239 0xD1,0x7C,0x4C,0x0F,0xAF,0x4E,0x21,0x09,0xA8,0x46,0x2A,0x07,0x85,0x1F,0x0E,0x07, |
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240 0xA6,0x3F,0x26,0x07,0x7C,0x24,0x14,0x07,0x78,0x22,0x16,0x04,0x46,0x12,0x0A,0x02, |
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241 0xA6,0x41,0x2C,0x0A,0x7E,0x28,0x11,0x05,0x73,0x1B,0x14,0x05,0x3D,0x11,0x0A,0x02, |
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242 0x70,0x22,0x17,0x05,0x48,0x13,0x08,0x03,0x3C,0x07,0x0D,0x07,0x26,0x07,0x06,0x01, |
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243 |
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244 0xE0,0x9F,0xDA,0x7C,0x4F,0x18,0x28,0x0D,0xE9,0x9F,0xDA,0x7C,0x4F,0x18,0x1F,0x07, |
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245 0xE6,0x97,0xD8,0x72,0x64,0x13,0x26,0x09,0xDC,0x67,0xA9,0x38,0x21,0x07,0x15,0x06, |
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246 0xE9,0x91,0xD2,0x6B,0x63,0x14,0x2B,0x0E,0xD6,0x61,0xB7,0x41,0x2B,0x0E,0x10,0x09, |
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247 0xCF,0x59,0xB0,0x2F,0x35,0x08,0x0F,0x07,0xB6,0x30,0x7A,0x21,0x17,0x07,0x09,0x03, |
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248 0xE7,0xA3,0xE5,0x6B,0x65,0x1F,0x34,0x09,0xD8,0x6B,0xBE,0x45,0x27,0x07,0x10,0x07, |
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249 0xDA,0x54,0xB1,0x39,0x2E,0x0E,0x17,0x08,0xA9,0x3C,0x86,0x22,0x16,0x06,0x07,0x03, |
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250 0xD4,0x51,0xBC,0x3D,0x38,0x0A,0x13,0x06,0xB2,0x37,0x79,0x1C,0x17,0x05,0x0E,0x06, |
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251 0xA7,0x31,0x74,0x1C,0x11,0x06,0x0C,0x02,0x6D,0x1A,0x38,0x10,0x0B,0x05,0x06,0x03, |
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252 0xEB,0x9A,0xE1,0x7A,0x6F,0x13,0x34,0x0E,0xE6,0x75,0xC5,0x45,0x3E,0x0B,0x1A,0x05, |
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253 0xD8,0x63,0xC1,0x40,0x3C,0x1B,0x19,0x06,0xB3,0x42,0x83,0x29,0x18,0x0A,0x08,0x04, |
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254 0xD4,0x58,0xBA,0x43,0x3F,0x0A,0x1F,0x09,0xB1,0x33,0x8A,0x1F,0x1F,0x06,0x0D,0x05, |
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255 0xAF,0x3C,0x7A,0x1F,0x16,0x08,0x0A,0x01,0x72,0x1B,0x52,0x0D,0x0B,0x09,0x06,0x01, |
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256 0xCF,0x63,0xB7,0x47,0x40,0x10,0x14,0x06,0xC0,0x41,0x96,0x20,0x1C,0x09,0x10,0x05, |
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257 0xA6,0x35,0x82,0x1A,0x20,0x0C,0x0E,0x04,0x80,0x1F,0x53,0x0F,0x0B,0x02,0x06,0x01, |
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258 0xA6,0x31,0x81,0x1B,0x1D,0x01,0x08,0x08,0x7B,0x20,0x4D,0x19,0x0E,0x05,0x07,0x03, |
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259 0x6B,0x17,0x49,0x07,0x0E,0x03,0x0A,0x05,0x37,0x0B,0x1F,0x06,0x04,0x02,0x07,0x01, |
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260 |
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261 0xF0,0xD6,0xED,0xAD,0xEC,0xB1,0xEB,0x79,0xAC,0x22,0x47,0x1E,0x6E,0x1B,0x32,0x0A, |
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262 0xF0,0xD6,0xEA,0xA4,0xED,0xC4,0xDE,0x82,0x98,0x1F,0x50,0x13,0x52,0x15,0x2A,0x0A, |
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263 0xF1,0xD1,0xEB,0xA2,0xEB,0xB7,0xD8,0x69,0xA2,0x1F,0x5B,0x18,0x55,0x18,0x2C,0x0A, |
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264 0xED,0xB5,0xDE,0x7E,0xE6,0x85,0xD3,0x59,0x59,0x0F,0x2C,0x09,0x24,0x07,0x15,0x09, |
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265 0xF1,0xD6,0xEA,0xA0,0xEC,0xBB,0xDA,0x77,0xA9,0x23,0x58,0x14,0x5D,0x12,0x2F,0x09, |
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266 0xF1,0xC1,0xE3,0x86,0xE4,0x87,0xD2,0x4E,0x68,0x15,0x26,0x0B,0x27,0x09,0x15,0x02, |
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267 0xEE,0xA6,0xE0,0x5C,0xE0,0x77,0xC3,0x41,0x67,0x1B,0x3C,0x07,0x2A,0x06,0x19,0x07, |
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268 0xE4,0x75,0xC6,0x43,0xCC,0x50,0x95,0x23,0x35,0x09,0x14,0x04,0x15,0x05,0x0B,0x04, |
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269 0xEE,0xD6,0xED,0xAD,0xEC,0xB1,0xEB,0x79,0xAC,0x22,0x56,0x14,0x5A,0x12,0x26,0x0A, |
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270 0xEE,0xBB,0xE7,0x7E,0xE9,0x8D,0xCB,0x49,0x67,0x11,0x34,0x07,0x2B,0x0B,0x14,0x07, |
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271 0xED,0xA7,0xE5,0x76,0xE3,0x7E,0xC4,0x4B,0x77,0x14,0x34,0x08,0x27,0x07,0x14,0x04, |
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272 0xE7,0x8B,0xD2,0x4C,0xCA,0x56,0x9E,0x31,0x36,0x0C,0x11,0x07,0x14,0x04,0x0A,0x02, |
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273 0xF0,0x9B,0xEA,0x6F,0xE5,0x81,0xC4,0x43,0x74,0x10,0x30,0x0B,0x2D,0x08,0x1B,0x06, |
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274 0xE6,0x83,0xCA,0x48,0xD9,0x56,0xA7,0x23,0x3B,0x09,0x12,0x09,0x15,0x07,0x0A,0x03, |
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275 0xE5,0x5F,0xCB,0x3C,0xCF,0x48,0x91,0x22,0x31,0x0A,0x17,0x08,0x15,0x04,0x0D,0x02, |
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276 0xD1,0x43,0x91,0x20,0xA9,0x2D,0x54,0x12,0x17,0x07,0x09,0x02,0x0C,0x04,0x05,0x03, |
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277 }; |
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278 #endif |
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279 |
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280 // divided into multiple functions to keep rarely-used functionality separate |
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281 // so often-used functionality can be optimized better by compiler |
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282 |
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283 // If write isn't preceded by read, data has this added to it |
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284 int const no_read_before_write = 0x2000; |
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285 |
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286 void Snes_Spc::cpu_write_smp_reg_( int data, rel_time_t time, int addr ) |
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287 { |
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288 switch ( addr ) |
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289 { |
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290 case r_t0target: |
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291 case r_t1target: |
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292 case r_t2target: { |
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293 Timer* t = &m.timers [addr - r_t0target]; |
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294 int period = IF_0_THEN_256( data ); |
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295 if ( t->period != period ) |
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296 { |
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297 t = run_timer( t, time ); |
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298 #if SPC_MORE_ACCURACY |
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299 // Insane behavior when target is written just after counter is |
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300 // clocked and counter matches new period and new period isn't 1, 2, 4, or 8 |
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301 if ( t->divider == (period & 0xFF) && |
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302 t->next_time == time + TIMER_MUL( t, 1 ) && |
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303 ((period - 1) | ~0x0F) & period ) |
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304 { |
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305 //dprintf( "SPC pathological timer target write\n" ); |
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306 |
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307 // If the period is 3, 5, or 9, there's a probability this behavior won't occur, |
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308 // based on the previous period |
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309 int prob = 0xFF; |
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310 int old_period = t->period & 0xFF; |
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311 if ( period == 3 ) prob = glitch_probs [0] [old_period]; |
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312 if ( period == 5 ) prob = glitch_probs [1] [old_period]; |
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313 if ( period == 9 ) prob = glitch_probs [2] [old_period]; |
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314 |
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315 // The glitch suppresses incrementing of one of the counter bits, based on |
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316 // the lowest set bit in the new period |
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317 int b = 1; |
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318 while ( !(period & b) ) |
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319 b <<= 1; |
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320 |
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321 if ( (rand() >> 4 & 0xFF) <= prob ) |
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322 t->divider = (t->divider - b) & 0xFF; |
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323 } |
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324 #endif |
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325 t->period = period; |
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326 } |
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327 break; |
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328 } |
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329 |
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330 case r_t0out: |
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331 case r_t1out: |
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332 case r_t2out: |
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333 if ( !SPC_MORE_ACCURACY ) |
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334 dprintf( "SPC wrote to counter %d\n", (int) addr - r_t0out ); |
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335 |
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336 if ( data < no_read_before_write / 2 ) |
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337 run_timer( &m.timers [addr - r_t0out], time - 1 )->counter = 0; |
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338 break; |
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339 |
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340 // Registers that act like RAM |
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341 case 0x8: |
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342 case 0x9: |
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343 REGS_IN [addr] = (uint8_t) data; |
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344 break; |
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345 |
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346 case r_test: |
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347 if ( (uint8_t) data != 0x0A ) |
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348 dprintf( "SPC wrote to test register\n" ); |
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349 break; |
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350 |
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351 case r_control: |
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352 // port clears |
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353 if ( data & 0x10 ) |
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354 { |
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355 REGS_IN [r_cpuio0] = 0; |
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356 REGS_IN [r_cpuio1] = 0; |
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357 } |
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358 if ( data & 0x20 ) |
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359 { |
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360 REGS_IN [r_cpuio2] = 0; |
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361 REGS_IN [r_cpuio3] = 0; |
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362 } |
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363 |
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364 // timers |
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365 { |
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366 for ( int i = 0; i < timer_count; i++ ) |
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367 { |
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368 Timer* t = &m.timers [i]; |
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369 int enabled = data >> i & 1; |
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370 if ( t->enabled != enabled ) |
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371 { |
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372 t = run_timer( t, time ); |
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373 t->enabled = enabled; |
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374 if ( enabled ) |
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375 { |
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376 t->divider = 0; |
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377 t->counter = 0; |
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378 } |
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379 } |
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380 } |
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381 } |
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382 enable_rom( data & 0x80 ); |
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383 break; |
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384 } |
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385 } |
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386 |
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387 void Snes_Spc::cpu_write_smp_reg( int data, rel_time_t time, int addr ) |
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388 { |
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389 if ( addr == r_dspdata ) // 99% |
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390 dsp_write( data, time ); |
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391 else |
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392 cpu_write_smp_reg_( data, time, addr ); |
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393 } |
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394 |
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395 void Snes_Spc::cpu_write_high( int data, int i, rel_time_t time ) |
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396 { |
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397 if ( i < rom_size ) |
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398 { |
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399 m.hi_ram [i] = (uint8_t) data; |
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400 if ( m.rom_enabled ) |
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401 RAM [i + rom_addr] = m.rom [i]; // restore overwritten ROM |
341 | 402 } |
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403 else |
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404 { |
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405 assert( RAM [i + rom_addr] == (uint8_t) data ); |
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406 RAM [i + rom_addr] = cpu_pad_fill; // restore overwritten padding |
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407 cpu_write( data, i + rom_addr - 0x10000, time ); |
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408 } |
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409 } |
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410 |
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411 int const bits_in_int = CHAR_BIT * sizeof (int); |
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412 |
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413 void Snes_Spc::cpu_write( int data, int addr, rel_time_t time ) |
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414 { |
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415 MEM_ACCESS( time, addr ) |
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416 |
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417 // RAM |
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418 RAM [addr] = (uint8_t) data; |
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419 int reg = addr - 0xF0; |
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420 if ( reg >= 0 ) // 64% |
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421 { |
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422 // $F0-$FF |
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423 if ( reg < reg_count ) // 87% |
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424 { |
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425 REGS [reg] = (uint8_t) data; |
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426 |
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427 // Ports |
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428 #ifdef SPC_PORT_WRITE_HOOK |
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429 if ( (unsigned) (reg - r_cpuio0) < port_count ) |
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430 SPC_PORT_WRITE_HOOK( m.spc_time + time, (reg - r_cpuio0), |
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431 (uint8_t) data, ®S [r_cpuio0] ); |
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432 #endif |
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433 |
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434 // Registers other than $F2 and $F4-$F7 |
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435 //if ( reg != 2 && reg != 4 && reg != 5 && reg != 6 && reg != 7 ) |
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436 // TODO: this is a bit on the fragile side |
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437 if ( ((~0x2F00 << (bits_in_int - 16)) << reg) < 0 ) // 36% |
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438 cpu_write_smp_reg( data, time, reg ); |
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439 } |
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440 // High mem/address wrap-around |
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441 else |
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442 { |
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443 reg -= rom_addr - 0xF0; |
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444 if ( reg >= 0 ) // 1% in IPL ROM area or address wrapped around |
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445 cpu_write_high( data, reg, time ); |
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446 } |
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447 } |
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448 } |
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449 |
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450 |
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451 //// CPU read |
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452 |
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453 inline int Snes_Spc::cpu_read_smp_reg( int reg, rel_time_t time ) |
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454 { |
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455 int result = REGS_IN [reg]; |
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456 reg -= r_dspaddr; |
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457 // DSP addr and data |
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458 if ( (unsigned) reg <= 1 ) // 4% 0xF2 and 0xF3 |
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459 { |
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460 result = REGS [r_dspaddr]; |
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461 if ( (unsigned) reg == 1 ) |
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462 result = dsp_read( time ); // 0xF3 |
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463 } |
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464 return result; |
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465 } |
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466 |
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467 int Snes_Spc::cpu_read( int addr, rel_time_t time ) |
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468 { |
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469 MEM_ACCESS( time, addr ) |
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470 |
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471 // RAM |
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472 int result = RAM [addr]; |
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473 int reg = addr - 0xF0; |
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474 if ( reg >= 0 ) // 40% |
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475 { |
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476 reg -= 0x10; |
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477 if ( (unsigned) reg >= 0xFF00 ) // 21% |
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478 { |
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479 reg += 0x10 - r_t0out; |
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480 |
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481 // Timers |
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482 if ( (unsigned) reg < timer_count ) // 90% |
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483 { |
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484 Timer* t = &m.timers [reg]; |
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485 if ( time >= t->next_time ) |
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486 t = run_timer_( t, time ); |
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487 result = t->counter; |
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488 t->counter = 0; |
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489 } |
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490 // Other registers |
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491 else if ( reg < 0 ) // 10% |
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492 { |
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493 result = cpu_read_smp_reg( reg + r_t0out, time ); |
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494 } |
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495 else // 1% |
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496 { |
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497 assert( reg + (r_t0out + 0xF0 - 0x10000) < 0x100 ); |
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498 result = cpu_read( reg + (r_t0out + 0xF0 - 0x10000), time ); |
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499 } |
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500 } |
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501 } |
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502 |
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503 return result; |
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504 } |
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505 |
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506 |
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507 //// Run |
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508 |
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509 // Prefix and suffix for CPU emulator function |
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510 #define SPC_CPU_RUN_FUNC \ |
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511 BOOST::uint8_t* Snes_Spc::run_until_( time_t end_time )\ |
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512 {\ |
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513 rel_time_t rel_time = m.spc_time - end_time;\ |
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514 assert( rel_time <= 0 );\ |
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515 m.spc_time = end_time;\ |
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516 m.dsp_time += rel_time;\ |
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517 m.timers [0].next_time += rel_time;\ |
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518 m.timers [1].next_time += rel_time;\ |
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519 m.timers [2].next_time += rel_time; |
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520 |
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521 #define SPC_CPU_RUN_FUNC_END \ |
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522 m.spc_time += rel_time;\ |
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523 m.dsp_time -= rel_time;\ |
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524 m.timers [0].next_time -= rel_time;\ |
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525 m.timers [1].next_time -= rel_time;\ |
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526 m.timers [2].next_time -= rel_time;\ |
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527 assert( m.spc_time <= end_time );\ |
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528 return ®S [r_cpuio0];\ |
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529 } |
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530 |
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531 int const cpu_lag_max = 12 - 1; // DIV YA,X takes 12 clocks |
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532 |
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533 void Snes_Spc::end_frame( time_t end_time ) |
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534 { |
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535 // Catch CPU up to as close to end as possible. If final instruction |
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536 // would exceed end, does NOT execute it and leaves m.spc_time < end. |
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537 if ( end_time > m.spc_time ) |
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538 run_until_( end_time ); |
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539 |
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540 m.spc_time -= end_time; |
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541 m.extra_clocks += end_time; |
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542 |
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543 // Greatest number of clocks early that emulation can stop early due to |
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544 // not being able to execute current instruction without going over |
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545 // allowed time. |
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546 assert( -cpu_lag_max <= m.spc_time && m.spc_time <= 0 ); |
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547 |
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548 // Catch timers up to CPU |
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549 for ( int i = 0; i < timer_count; i++ ) |
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550 run_timer( &m.timers [i], 0 ); |
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551 |
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552 // Catch DSP up to CPU |
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553 if ( m.dsp_time < 0 ) |
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554 { |
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555 RUN_DSP( 0, max_reg_time ); |
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556 } |
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557 |
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558 // Save any extra samples beyond what should be generated |
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559 if ( m.buf_begin ) |
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560 save_extra(); |
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561 } |
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562 |
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563 // Inclusion here allows static memory access functions and better optimization |
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564 #include "Spc_Cpu.h" |