Mercurial > audlegacy-plugins
annotate src/sexypsf/PsxHw.c @ 2128:feb0e916f8bc
adapted SexyPSF timeout to the method nenolod introduced in UPSE
author | mf0102 <0102@gmx.at> |
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date | Wed, 24 Oct 2007 15:46:20 +0200 |
parents | 3da1b8942b8b |
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rev | line source |
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1 /* Pcsx - Pc Psx Emulator |
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2 * Copyright (C) 1999-2002 Pcsx Team |
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3 * |
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4 * This program is free software; you can redistribute it and/or modify |
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5 * it under the terms of the GNU General Public License as published by |
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6 * the Free Software Foundation; either version 2 of the License, or |
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7 * (at your option) any later version. |
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8 * |
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9 * This program is distributed in the hope that it will be useful, |
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10 * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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12 * GNU General Public License for more details. |
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13 * |
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14 * You should have received a copy of the GNU General Public License |
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15 * along with this program; if not, write to the Free Software |
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16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA |
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17 */ |
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18 |
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19 #include <stdio.h> |
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20 #include <string.h> |
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21 |
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22 #include "PsxCommon.h" |
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23 |
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24 #define HW_DMA4_MADR (psxHu32(0x10c0)) // SPU DMA |
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25 #define HW_DMA4_BCR (psxHu32(0x10c4)) |
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26 #define HW_DMA4_CHCR (psxHu32(0x10c8)) |
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27 |
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28 #define HW_DMA_PCR (psxHu32(0x10f0)) |
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29 #define HW_DMA_ICR (psxHu32(0x10f4)) |
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30 |
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31 void psxHwReset() { |
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32 memset(psxH, 0, 0x10000); |
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33 psxRcntInit(); |
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34 } |
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35 |
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36 u8 psxHwRead8(u32 add) { |
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37 u8 hard; |
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38 |
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39 switch (add) { |
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40 default: |
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41 hard = psxHu8(add); |
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42 return hard; |
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43 } |
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44 return hard; |
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45 } |
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46 |
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47 u16 psxHwRead16(u32 add) { |
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48 u16 hard; |
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49 |
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50 switch (add) { |
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51 case 0x1f801100: |
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52 hard = psxRcntRcount(0); |
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53 return hard; |
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54 case 0x1f801104: |
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55 hard = psxCounters[0].mode; |
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56 return hard; |
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57 case 0x1f801108: |
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58 hard = psxCounters[0].target; |
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59 return hard; |
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60 case 0x1f801110: |
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61 hard = psxRcntRcount(1); |
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62 return hard; |
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63 case 0x1f801114: |
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64 hard = psxCounters[1].mode; |
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65 return hard; |
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66 case 0x1f801118: |
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67 hard = psxCounters[1].target; |
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68 return hard; |
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69 case 0x1f801120: |
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70 hard = psxRcntRcount(2); |
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71 return hard; |
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72 case 0x1f801124: |
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73 hard = psxCounters[2].mode; |
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74 return hard; |
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75 case 0x1f801128: |
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76 hard = psxCounters[2].target; |
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77 return hard; |
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78 |
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79 default: |
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80 if (add>=0x1f801c00 && add<0x1f801e00) { |
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81 hard = SPUreadRegister(add); |
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82 } else { |
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83 hard = BFLIP16(psxHu16(add)); |
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84 } |
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85 return hard; |
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86 } |
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87 return hard; |
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88 } |
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89 |
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90 u32 psxHwRead32(u32 add) { |
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91 u32 hard; |
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92 |
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93 switch (add) { |
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94 // time for rootcounters :) |
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95 case 0x1f801100: |
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96 hard = psxRcntRcount(0); |
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97 return hard; |
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98 case 0x1f801104: |
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99 hard = psxCounters[0].mode; |
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100 return hard; |
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101 case 0x1f801108: |
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102 hard = psxCounters[0].target; |
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103 return hard; |
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104 case 0x1f801110: |
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105 hard = psxRcntRcount(1); |
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106 return hard; |
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107 case 0x1f801114: |
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108 hard = psxCounters[1].mode; |
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109 return hard; |
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110 case 0x1f801118: |
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111 hard = psxCounters[1].target; |
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112 return hard; |
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113 case 0x1f801120: |
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114 hard = psxRcntRcount(2); |
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115 return hard; |
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116 case 0x1f801124: |
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117 hard = psxCounters[2].mode; |
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118 return hard; |
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119 case 0x1f801128: |
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120 hard = psxCounters[2].target; |
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121 return hard; |
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122 |
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123 default: |
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124 hard = BFLIP32(psxHu32(add)); |
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125 return hard; |
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126 } |
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127 return hard; |
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128 } |
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129 |
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130 void psxHwWrite8(u32 add, u8 value) { |
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131 switch (add) { |
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132 default: |
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133 psxHu8(add) = value; |
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134 return; |
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135 } |
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136 psxHu8(add) = value; |
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137 } |
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138 |
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139 void psxHwWrite16(u32 add, u16 value) { |
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140 switch (add) { |
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141 |
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142 case 0x1f801070: |
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143 psxHu16(0x1070) &= BFLIP16( BFLIP16(psxHu16(0x1074)) & value); |
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144 return; |
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145 case 0x1f801100: |
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146 psxRcntWcount(0, value); return; |
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147 case 0x1f801104: |
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148 psxRcntWmode(0, value); return; |
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149 case 0x1f801108: |
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150 psxRcntWtarget(0, value); return; |
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151 |
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152 case 0x1f801110: |
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153 psxRcntWcount(1, value); return; |
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154 case 0x1f801114: |
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155 psxRcntWmode(1, value); return; |
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156 case 0x1f801118: |
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157 psxRcntWtarget(1, value); return; |
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158 |
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159 case 0x1f801120: |
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160 psxRcntWcount(2, value); return; |
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161 case 0x1f801124: |
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162 psxRcntWmode(2, value); return; |
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163 case 0x1f801128: |
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164 psxRcntWtarget(2, value); return; |
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165 |
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166 default: |
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167 if (add>=0x1f801c00 && add<0x1f801e00) { |
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168 SPUwriteRegister(add, value); |
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169 return; |
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170 } |
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171 |
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172 psxHu16(add) = BFLIP16(value); |
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173 return; |
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174 } |
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175 psxHu16(add) = BFLIP16(value); |
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176 } |
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177 |
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178 #define DMA_INTERRUPT(n) \ |
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179 if (BFLIP32(HW_DMA_ICR) & (1 << (16 + n))) { \ |
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180 HW_DMA_ICR|= BFLIP32(1 << (24 + n)); \ |
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181 psxHu32(0x1070) |= BFLIP32(8); \ |
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182 } |
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183 |
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184 #define DmaExec(n) { \ |
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185 if (BFLIP32(HW_DMA##n##_CHCR) & 0x01000000 && BFLIP32(HW_DMA_PCR) & (8 << (n * 4))) { \ |
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186 psxDma##n(BFLIP32(HW_DMA##n##_MADR), BFLIP32(HW_DMA##n##_BCR), BFLIP32(HW_DMA##n##_CHCR)); \ |
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187 HW_DMA##n##_CHCR &= BFLIP32(~0x01000000); \ |
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188 DMA_INTERRUPT(n); \ |
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189 } \ |
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190 } |
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191 |
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192 void psxHwWrite32(u32 add, u32 value) { |
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193 switch (add) { |
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194 case 0x1f801070: |
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195 psxHu32(0x1070) &= BFLIP32(BFLIP32(psxHu32(0x1074)) & value); |
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196 return; |
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197 case 0x1f8010c8: |
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198 HW_DMA4_CHCR = BFLIP32(value); // DMA4 chcr (SPU DMA) |
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199 DmaExec(4); |
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200 return; |
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201 case 0x1f8010f4: |
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202 { |
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203 u32 tmp = (~value) & BFLIP32(HW_DMA_ICR); |
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204 HW_DMA_ICR = BFLIP32(((tmp ^ value) & 0xffffff) ^ tmp); |
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205 return; |
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206 } |
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207 |
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208 case 0x1f801100: |
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209 psxRcntWcount(0, value & 0xffff); return; |
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210 case 0x1f801104: |
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211 psxRcntWmode(0, value); return; |
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212 case 0x1f801108: |
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213 psxRcntWtarget(0, value & 0xffff); return; |
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214 // HW_DMA_ICR&= (~value)&0xff000000; |
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215 |
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216 case 0x1f801110: |
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217 psxRcntWcount(1, value & 0xffff); return; |
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218 case 0x1f801114: |
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219 psxRcntWmode(1, value); return; |
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220 case 0x1f801118: |
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221 psxRcntWtarget(1, value & 0xffff); return; |
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222 |
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223 case 0x1f801120: |
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224 psxRcntWcount(2, value & 0xffff); return; |
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225 case 0x1f801124: |
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226 psxRcntWmode(2, value); return; |
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227 case 0x1f801128: |
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228 psxRcntWtarget(2, value & 0xffff); return; |
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229 |
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230 default: |
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231 psxHu32(add) = BFLIP32(value); |
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232 return; |
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233 } |
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234 psxHu32(add) = BFLIP32(value); |
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235 } |
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236 |