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comparison src/xsf/desmume/arm_instructions.c @ 2961:70b0973e7b70

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Merge xsf plugin.
author William Pitcock <nenolod@atheme.org>
date Thu, 16 Oct 2008 14:45:41 -0500
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2960:fe2ba1a712cd 2961:70b0973e7b70
1 /* Copyright (C) 2006 yopyop
2 Copyright (C) 2006 shash
3 yopyop156@ifrance.com
4 yopyop156.ifrance.com
5
6 Copyright (C) 2006-2007 shash
7
8 This file is part of DeSmuME
9
10 DeSmuME is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2 of the License, or
13 (at your option) any later version.
14
15 DeSmuME is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with DeSmuME; if not, write to the Free Software
22 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 */
24
25 #include "cp15.h"
26 #include "debug.h"
27 #include "MMU.h"
28
29
30 // Use this macros for reading/writing, so the GDB stub isn't broken
31 #ifdef GDB_STUB
32 #define READ32(a,b) cpu->mem_if->read32(a,b)
33 #define WRITE32(a,b,c) cpu->mem_if->write32(a,b,c)
34 #define READ16(a,b) cpu->mem_if->read16(a,b)
35 #define WRITE16(a,b,c) cpu->mem_if->write16(a,b,c)
36 #define READ8(a,b) cpu->mem_if->read8(a,b)
37 #define WRITE8(a,b,c) cpu->mem_if->write8(a,b,c)
38 #else
39 #define READ32(a,b) MMU_read32(cpu->proc_ID, b)
40 #define WRITE32(a,b,c) MMU_write32(cpu->proc_ID,b,c)
41 #define READ16(a,b) MMU_read16(cpu->proc_ID, b)
42 #define WRITE16(a,b,c) MMU_write16(cpu->proc_ID,b,c)
43 #define READ8(a,b) MMU_read8(cpu->proc_ID, b)
44 #define WRITE8(a,b,c) MMU_write8(cpu->proc_ID,b,c)
45 #endif
46
47
48
49 #define LSL_IMM shift_op = cpu->R[REG_POS(i,0)]<<((i>>7)&0x1F);
50
51 #define S_LSL_IMM u32 shift_op = ((i>>7)&0x1F);\
52 u32 c = cpu->CPSR.bits.C;\
53 if(shift_op==0)\
54 shift_op=cpu->R[REG_POS(i,0)];\
55 else\
56 {\
57 c = BIT_N(cpu->R[REG_POS(i,0)], 32-shift_op);\
58 shift_op = cpu->R[REG_POS(i,0)]<<((i>>7)&0x1F);\
59 }
60
61 #define LSL_REG u32 shift_op = (cpu->R[REG_POS(i,8)])&0xFF;\
62 if(shift_op>=32)\
63 shift_op=0;\
64 else\
65 shift_op=cpu->R[REG_POS(i,0)]<<shift_op;
66
67 #define S_LSL_REG u32 shift_op = (cpu->R[REG_POS(i,8)])&0xFF;\
68 u32 c = cpu->CPSR.bits.C;\
69 if(shift_op==0)\
70 shift_op=cpu->R[REG_POS(i,0)];\
71 else\
72 if(shift_op<32)\
73 {\
74 c = BIT_N(cpu->R[REG_POS(i,0)], 32-shift_op);\
75 shift_op = cpu->R[REG_POS(i,0)]<<shift_op;\
76 }\
77 else\
78 if(shift_op==32)\
79 {\
80 shift_op = 0;\
81 c = BIT0(cpu->R[REG_POS(i,0)]);\
82 }\
83 else\
84 {\
85 shift_op = 0;\
86 c = 0;\
87 }
88
89 #define LSR_IMM shift_op = ((i>>7)&0x1F);\
90 if(shift_op!=0)\
91 shift_op = cpu->R[REG_POS(i,0)]>>shift_op;
92
93 #define S_LSR_IMM u32 shift_op = ((i>>7)&0x1F);\
94 u32 c = cpu->CPSR.bits.C;\
95 if(shift_op==0)\
96 {\
97 c = BIT31(cpu->R[REG_POS(i,0)]);\
98 }\
99 else\
100 {\
101 c = BIT_N(cpu->R[REG_POS(i,0)], shift_op-1);\
102 shift_op = cpu->R[REG_POS(i,0)]>>shift_op;\
103 }
104
105 #define LSR_REG u32 shift_op = (cpu->R[REG_POS(i,8)])&0xFF;\
106 if(shift_op>=32)\
107 shift_op = 0;\
108 else\
109 shift_op = cpu->R[REG_POS(i,0)]>>shift_op;
110
111 #define S_LSR_REG u32 shift_op = (cpu->R[REG_POS(i,8)])&0xFF;\
112 u32 c = cpu->CPSR.bits.C;\
113 if(shift_op==0)\
114 {\
115 shift_op = cpu->R[REG_POS(i,0)];\
116 }\
117 else\
118 if(shift_op<32)\
119 {\
120 c = BIT_N(cpu->R[REG_POS(i,0)], shift_op-1);\
121 shift_op = cpu->R[REG_POS(i,0)]>>shift_op;\
122 }\
123 else\
124 if(shift_op==32)\
125 {\
126 c = BIT31(cpu->R[REG_POS(i,0)]);\
127 shift_op = 0;\
128 }\
129 else\
130 {\
131 c = 0;\
132 shift_op = 0;\
133 }
134
135 #define ASR_IMM shift_op = ((i>>7)&0x1F);\
136 if(shift_op==0)\
137 shift_op=BIT31(cpu->R[REG_POS(i,0)])*0xFFFFFFFF;\
138 else\
139 shift_op = (u32)(((s32)(cpu->R[REG_POS(i,0)]))>>shift_op);
140
141 #define S_ASR_IMM u32 shift_op = ((i>>7)&0x1F);\
142 u32 c = cpu->CPSR.bits.C;\
143 if(shift_op==0)\
144 {\
145 shift_op=BIT31(cpu->R[REG_POS(i,0)])*0xFFFFFFFF;\
146 c = BIT31(cpu->R[REG_POS(i,0)]);\
147 }\
148 else\
149 {\
150 c = BIT_N(cpu->R[REG_POS(i,0)], shift_op-1);\
151 shift_op = (u32)(((s32)(cpu->R[REG_POS(i,0)]))>>shift_op);\
152 }
153
154 #define ASR_REG u32 shift_op = (cpu->R[REG_POS(i,8)])&0xFF;\
155 if(shift_op==0)\
156 shift_op=cpu->R[REG_POS(i,0)];\
157 else\
158 if(shift_op<32)\
159 shift_op = (u32)(((s32)(cpu->R[REG_POS(i,0)]))>>shift_op);\
160 else\
161 shift_op=BIT31(cpu->R[REG_POS(i,0)])*0xFFFFFFFF;
162
163 #define S_ASR_REG u32 shift_op = (cpu->R[REG_POS(i,8)])&0xFF;\
164 u32 c = cpu->CPSR.bits.C;\
165 if(shift_op==0)\
166 shift_op=cpu->R[REG_POS(i,0)];\
167 else\
168 if(shift_op<32)\
169 {\
170 c = BIT_N(cpu->R[REG_POS(i,0)], shift_op-1);\
171 shift_op = (u32)(((s32)(cpu->R[REG_POS(i,0)]))>>shift_op);\
172 }\
173 else\
174 {\
175 c = BIT31(cpu->R[REG_POS(i,0)]);\
176 shift_op=BIT31(cpu->R[REG_POS(i,0)])*0xFFFFFFFF;\
177 }
178
179 #define ROR_IMM shift_op = ((i>>7)&0x1F);\
180 if(shift_op==0)\
181 {\
182 u32 tmp = cpu->CPSR.bits.C;\
183 shift_op = (tmp<<31)|(cpu->R[REG_POS(i,0)]>>1);\
184 }\
185 else\
186 shift_op = ROR(cpu->R[REG_POS(i,0)],shift_op);
187
188 #define S_ROR_IMM u32 shift_op = ((i>>7)&0x1F);\
189 u32 c = cpu->CPSR.bits.C;\
190 if(shift_op==0)\
191 {\
192 u32 tmp = cpu->CPSR.bits.C;\
193 shift_op = (tmp<<31)|(cpu->R[REG_POS(i,0)]>>1);\
194 c = BIT0(cpu->R[REG_POS(i,0)]);\
195 }\
196 else\
197 {\
198 c = BIT_N(cpu->R[REG_POS(i,0)], shift_op-1);\
199 shift_op = ROR(cpu->R[REG_POS(i,0)],shift_op);\
200 }
201
202 #define ROR_REG u32 shift_op = (cpu->R[REG_POS(i,8)])&0xFF;\
203 if((shift_op==0)||((shift_op&0xF)==0))\
204 shift_op=cpu->R[REG_POS(i,0)];\
205 else\
206 shift_op = ROR(cpu->R[REG_POS(i,0)],(shift_op&0xF));
207
208 #define S_ROR_REG u32 shift_op = (cpu->R[REG_POS(i,8)])&0xFF;\
209 u32 c = cpu->CPSR.bits.C;\
210 if(shift_op==0)\
211 shift_op=cpu->R[REG_POS(i,0)];\
212 else\
213 {\
214 shift_op&=0xF;\
215 if(shift_op==0)\
216 {\
217 shift_op=cpu->R[REG_POS(i,0)];\
218 c = BIT31(cpu->R[REG_POS(i,0)]);\
219 }\
220 else\
221 {\
222 c = BIT_N(cpu->R[REG_POS(i,0)], shift_op-1);\
223 shift_op = ROR(cpu->R[REG_POS(i,0)],(shift_op&0xF));\
224 }\
225 }
226
227 #define IMM_VALUE u32 shift_op = ROR((i&0xFF), (i>>7)&0x1E);
228
229 #define S_IMM_VALUE u32 shift_op = ROR((i&0xFF), (i>>7)&0x1E);\
230 u32 c = cpu->CPSR.bits.C;\
231 if((i>>8)&0xF)\
232 c = BIT31(shift_op);
233
234 #define IMM_OFF (((i>>4)&0xF0)+(i&0xF))
235
236 #define IMM_OFF_12 ((i)&0xFFF)
237
238 extern BOOL execute;
239
240 static u32 FASTCALL OP_UND(armcpu_t *cpu)
241 {
242 u32 i = cpu->instruction;
243 LOG("Undefined instruction: %08X\n", i);
244 execute = FALSE;
245 return 1;
246 }
247
248 //-----------------------AND------------------------------------
249
250 #define OP_AND(a, b) cpu->R[REG_POS(i,12)] = cpu->R[REG_POS(i,16)] & shift_op;\
251 if(REG_POS(i,12)==15)\
252 {\
253 cpu->next_instruction = cpu->R[15];\
254 return b;\
255 }\
256 return a;
257
258 #define OP_ANDS(a, b)\
259 if(REG_POS(i,12)==15)\
260 {\
261 Status_Reg SPSR;\
262 cpu->R[15] = cpu->R[REG_POS(i,16)] & shift_op;\
263 SPSR = cpu->SPSR;\
264 armcpu_switchMode(cpu, SPSR.bits.mode);\
265 cpu->CPSR=SPSR;\
266 cpu->R[15] &= (0XFFFFFFFC|(((u32)SPSR.bits.T)<<1));\
267 cpu->next_instruction = cpu->R[15];\
268 return b;\
269 }\
270 cpu->R[REG_POS(i,12)] = cpu->R[REG_POS(i,16)] & shift_op;\
271 cpu->CPSR.bits.C = c;\
272 cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,12)]);\
273 cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0);\
274 return a;
275
276 static u32 FASTCALL OP_AND_LSL_IMM(register armcpu_t *cpu)
277 {
278 u32 i = cpu->instruction;
279 u32 shift_op;
280 LSL_IMM;
281 OP_AND(1, 3);
282 }
283
284 static u32 FASTCALL OP_AND_LSL_REG(armcpu_t *cpu)
285 {
286 u32 i = cpu->instruction;
287 LSL_REG;
288 OP_AND(2, 4);
289 }
290
291 static u32 FASTCALL OP_AND_LSR_IMM(armcpu_t *cpu)
292 {
293 u32 i = cpu->instruction;
294 u32 shift_op;
295 LSR_IMM;
296 OP_AND(1, 3);
297 }
298
299 static u32 FASTCALL OP_AND_LSR_REG(armcpu_t *cpu)
300 {
301 u32 i = cpu->instruction;
302 LSR_REG;
303 OP_AND(2, 4);
304 }
305
306 static u32 FASTCALL OP_AND_ASR_IMM(armcpu_t *cpu)
307 {
308 u32 i = cpu->instruction;
309 u32 shift_op;
310 ASR_IMM;
311 OP_AND(1, 3);
312 }
313
314 static u32 FASTCALL OP_AND_ASR_REG(armcpu_t *cpu)
315 {
316 u32 i = cpu->instruction;
317 ASR_REG;
318 OP_AND(2, 4);
319 }
320
321 static u32 FASTCALL OP_AND_ROR_IMM(armcpu_t *cpu)
322 {
323 u32 i = cpu->instruction;
324 u32 shift_op;
325 ROR_IMM;
326 OP_AND(1, 3);
327 }
328
329 static u32 FASTCALL OP_AND_ROR_REG(armcpu_t *cpu)
330 {
331 u32 i = cpu->instruction;
332 ROR_REG;
333 OP_AND(2, 4);
334 }
335
336 static u32 FASTCALL OP_AND_IMM_VAL(armcpu_t *cpu)
337 {
338 u32 i = cpu->instruction;
339 IMM_VALUE;
340 OP_AND(1, 3);
341 }
342
343 static u32 FASTCALL OP_AND_S_LSL_IMM(armcpu_t *cpu)
344 {
345 u32 i = cpu->instruction;
346 S_LSL_IMM;
347 OP_ANDS(2, 4);
348 }
349
350 static u32 FASTCALL OP_AND_S_LSL_REG(armcpu_t *cpu)
351 {
352 u32 i = cpu->instruction;
353 S_LSL_REG;
354 OP_ANDS(3, 5);
355 }
356
357 static u32 FASTCALL OP_AND_S_LSR_IMM(armcpu_t *cpu)
358 {
359 u32 i = cpu->instruction;
360 S_LSR_IMM;
361 OP_ANDS(2, 4);
362 }
363
364 static u32 FASTCALL OP_AND_S_LSR_REG(armcpu_t *cpu)
365 {
366 u32 i = cpu->instruction;
367 S_LSR_REG;
368 OP_ANDS(3, 5);
369 }
370
371 static u32 FASTCALL OP_AND_S_ASR_IMM(armcpu_t *cpu)
372 {
373 u32 i = cpu->instruction;
374 S_ASR_IMM;
375 OP_ANDS(2, 4);
376 }
377
378 static u32 FASTCALL OP_AND_S_ASR_REG(armcpu_t *cpu)
379 {
380 u32 i = cpu->instruction;
381 S_ASR_REG;
382 OP_ANDS(3, 5);
383 }
384
385 static u32 FASTCALL OP_AND_S_ROR_IMM(armcpu_t *cpu)
386 {
387 u32 i = cpu->instruction;
388 S_ROR_IMM;
389 OP_ANDS(2, 4);
390 }
391
392 static u32 FASTCALL OP_AND_S_ROR_REG(armcpu_t *cpu)
393 {
394 u32 i = cpu->instruction;
395 S_ROR_REG;
396 OP_ANDS(3, 5);
397 }
398
399 static u32 FASTCALL OP_AND_S_IMM_VAL(armcpu_t *cpu)
400 {
401 u32 i = cpu->instruction;
402 S_IMM_VALUE;
403 OP_ANDS(2, 4);
404 }
405
406 //--------------EOR------------------------------
407
408 #define OP_EOR(a, b) cpu->R[REG_POS(i,12)] = cpu->R[REG_POS(i,16)] ^ shift_op;\
409 if(REG_POS(i,12)==15)\
410 {\
411 cpu->next_instruction = cpu->R[15];\
412 return b;\
413 }\
414 return a;
415
416 #define OP_EORS(a, b) cpu->R[REG_POS(i,12)] = cpu->R[REG_POS(i,16)] ^ shift_op;\
417 if(REG_POS(i,12)==15)\
418 {\
419 Status_Reg SPSR = cpu->SPSR;\
420 armcpu_switchMode(cpu, SPSR.bits.mode);\
421 cpu->CPSR=SPSR;\
422 cpu->R[15] &= (0XFFFFFFFC|(((u32)SPSR.bits.T)<<1));\
423 cpu->next_instruction = cpu->R[15];\
424 return b;\
425 }\
426 cpu->CPSR.bits.C = c;\
427 cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,12)]);\
428 cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0);\
429 return a;
430
431 static u32 FASTCALL OP_EOR_LSL_IMM(armcpu_t *cpu)
432 {
433 u32 i = cpu->instruction;
434 u32 shift_op;
435 LSL_IMM;
436 OP_EOR(1, 3);
437 }
438
439 static u32 FASTCALL OP_EOR_LSL_REG(armcpu_t *cpu)
440 {
441 u32 i = cpu->instruction;
442 LSL_REG;
443 OP_EOR(2, 4);
444 }
445
446 static u32 FASTCALL OP_EOR_LSR_IMM(armcpu_t *cpu)
447 {
448 u32 i = cpu->instruction;
449 u32 shift_op;
450 LSR_IMM;
451 OP_EOR(1, 3);
452 }
453
454 static u32 FASTCALL OP_EOR_LSR_REG(armcpu_t *cpu)
455 {
456 u32 i = cpu->instruction;
457 LSR_REG;
458 OP_EOR(2, 4);
459 }
460
461 static u32 FASTCALL OP_EOR_ASR_IMM(armcpu_t *cpu)
462 {
463 u32 i = cpu->instruction;
464 u32 shift_op;
465 ASR_IMM;
466 OP_EOR(1, 3);
467 }
468
469 static u32 FASTCALL OP_EOR_ASR_REG(armcpu_t *cpu)
470 {
471 u32 i = cpu->instruction;
472 ASR_REG;
473 OP_EOR(2, 4);
474 }
475
476 static u32 FASTCALL OP_EOR_ROR_IMM(armcpu_t *cpu)
477 {
478 u32 i = cpu->instruction;
479 u32 shift_op;
480 ROR_IMM;
481 OP_EOR(1, 3);
482 }
483
484 static u32 FASTCALL OP_EOR_ROR_REG(armcpu_t *cpu)
485 {
486 u32 i = cpu->instruction;
487 ROR_REG;
488 OP_EOR(2, 4);
489 }
490
491 static u32 FASTCALL OP_EOR_IMM_VAL(armcpu_t *cpu)
492 {
493 u32 i = cpu->instruction;
494 IMM_VALUE;
495 OP_EOR(1, 3);
496 }
497
498 static u32 FASTCALL OP_EOR_S_LSL_IMM(armcpu_t *cpu)
499 {
500 u32 i = cpu->instruction;
501 S_LSL_IMM;
502 OP_EORS(2, 4);
503 }
504
505 static u32 FASTCALL OP_EOR_S_LSL_REG(armcpu_t *cpu)
506 {
507 u32 i = cpu->instruction;
508 S_LSL_REG;
509 OP_EORS(3, 5);
510 }
511
512 static u32 FASTCALL OP_EOR_S_LSR_IMM(armcpu_t *cpu)
513 {
514 u32 i = cpu->instruction;
515 S_LSR_IMM;
516 OP_EORS(2, 4);
517 }
518
519 static u32 FASTCALL OP_EOR_S_LSR_REG(armcpu_t *cpu)
520 {
521 u32 i = cpu->instruction;
522 S_LSR_REG;
523 OP_EORS(3, 5);
524 }
525
526 static u32 FASTCALL OP_EOR_S_ASR_IMM(armcpu_t *cpu)
527 {
528 u32 i = cpu->instruction;
529 S_ASR_IMM;
530 OP_EORS(2, 4);
531 }
532
533 static u32 FASTCALL OP_EOR_S_ASR_REG(armcpu_t *cpu)
534 {
535 u32 i = cpu->instruction;
536 S_ASR_REG;
537 OP_EORS(3, 5);
538 }
539
540 static u32 FASTCALL OP_EOR_S_ROR_IMM(armcpu_t *cpu)
541 {
542 u32 i = cpu->instruction;
543 S_ROR_IMM;
544 OP_EORS(2, 4);
545 }
546
547 static u32 FASTCALL OP_EOR_S_ROR_REG(armcpu_t *cpu)
548 {
549 u32 i = cpu->instruction;
550 S_ROR_REG;
551 OP_EORS(3, 5);
552 }
553
554 static u32 FASTCALL OP_EOR_S_IMM_VAL(armcpu_t *cpu)
555 {
556 u32 i = cpu->instruction;
557 S_IMM_VALUE;
558 OP_EORS(2, 4);
559 }
560
561 //-------------SUB-------------------------------------
562
563 #define OP_SUB(a, b) cpu->R[REG_POS(i,12)] = cpu->R[REG_POS(i,16)] - shift_op;\
564 if(REG_POS(i,12)==15)\
565 {\
566 cpu->next_instruction = cpu->R[15];\
567 return b;\
568 }\
569 return a;
570
571 #define OPSUBS(a, b) cpu->R[REG_POS(i,12)] = v - shift_op;\
572 if(REG_POS(i,12)==15)\
573 {\
574 Status_Reg SPSR = cpu->SPSR;\
575 armcpu_switchMode(cpu, SPSR.bits.mode);\
576 cpu->CPSR=SPSR;\
577 cpu->R[15] &= (0XFFFFFFFC|(((u32)SPSR.bits.T)<<1));\
578 cpu->next_instruction = cpu->R[15];\
579 return b;\
580 }\
581 cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,12)]);\
582 cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0);\
583 cpu->CPSR.bits.C = !UNSIGNED_UNDERFLOW(v, shift_op, cpu->R[REG_POS(i,12)]);\
584 cpu->CPSR.bits.V = SIGNED_UNDERFLOW(v, shift_op, cpu->R[REG_POS(i,12)]);\
585 return a;
586
587 static u32 FASTCALL OP_SUB_LSL_IMM(armcpu_t *cpu)
588 {
589 u32 i = cpu->instruction;
590 u32 shift_op;
591 LSL_IMM;
592 OP_SUB(1, 3);
593 }
594
595 static u32 FASTCALL OP_SUB_LSL_REG(armcpu_t *cpu)
596 {
597 u32 i = cpu->instruction;
598 LSL_REG;
599 OP_SUB(2, 4);
600 }
601
602 static u32 FASTCALL OP_SUB_LSR_IMM(armcpu_t *cpu)
603 {
604 u32 i = cpu->instruction;
605 u32 shift_op;
606 LSR_IMM;
607 OP_SUB(1, 3);
608 }
609
610 static u32 FASTCALL OP_SUB_LSR_REG(armcpu_t *cpu)
611 {
612 u32 i = cpu->instruction;
613 LSR_REG;
614 OP_SUB(2, 4);
615 }
616
617 static u32 FASTCALL OP_SUB_ASR_IMM(armcpu_t *cpu)
618 {
619 u32 i = cpu->instruction;
620 u32 shift_op;
621 ASR_IMM;
622 OP_SUB(1, 3);
623 }
624
625 static u32 FASTCALL OP_SUB_ASR_REG(armcpu_t *cpu)
626 {
627 u32 i = cpu->instruction;
628 ASR_REG;
629 OP_SUB(2, 4);
630 }
631
632 static u32 FASTCALL OP_SUB_ROR_IMM(armcpu_t *cpu)
633 {
634 u32 i = cpu->instruction;
635 u32 shift_op;
636 ROR_IMM;
637 OP_SUB(1, 3);
638 }
639
640 static u32 FASTCALL OP_SUB_ROR_REG(armcpu_t *cpu)
641 {
642 u32 i = cpu->instruction;
643 ROR_REG;
644 OP_SUB(2, 4);
645 }
646
647 static u32 FASTCALL OP_SUB_IMM_VAL(armcpu_t *cpu)
648 {
649 u32 i = cpu->instruction;
650 IMM_VALUE;
651 OP_SUB(1, 3);
652 }
653
654 static u32 FASTCALL OP_SUB_S_LSL_IMM(armcpu_t *cpu)
655 {
656 u32 i = cpu->instruction;
657 u32 v = cpu->R[REG_POS(i,16)];
658 u32 shift_op;
659 LSL_IMM;
660 OPSUBS(2, 4);
661 }
662
663 static u32 FASTCALL OP_SUB_S_LSL_REG(armcpu_t *cpu)
664 {
665 u32 i = cpu->instruction;
666 u32 v = cpu->R[REG_POS(i,16)];
667 LSL_REG;
668 OPSUBS(3, 5);
669 }
670
671 static u32 FASTCALL OP_SUB_S_LSR_IMM(armcpu_t *cpu)
672 {
673 u32 i = cpu->instruction;
674 u32 v = cpu->R[REG_POS(i,16)];
675 u32 shift_op;
676 LSR_IMM;
677 OPSUBS(2, 4);
678 }
679
680 static u32 FASTCALL OP_SUB_S_LSR_REG(armcpu_t *cpu)
681 {
682 u32 i = cpu->instruction;
683 u32 v = cpu->R[REG_POS(i,16)];
684 LSR_REG;
685 OPSUBS(3, 5);
686 }
687
688 static u32 FASTCALL OP_SUB_S_ASR_IMM(armcpu_t *cpu)
689 {
690 u32 i = cpu->instruction;
691 u32 v = cpu->R[REG_POS(i,16)];
692 u32 shift_op;
693 ASR_IMM;
694 OPSUBS(2, 4);
695 }
696
697 static u32 FASTCALL OP_SUB_S_ASR_REG(armcpu_t *cpu)
698 {
699 u32 i = cpu->instruction;
700 u32 v = cpu->R[REG_POS(i,16)];
701 ASR_REG;
702 OPSUBS(3, 5);
703 }
704
705 static u32 FASTCALL OP_SUB_S_ROR_IMM(armcpu_t *cpu)
706 {
707 u32 i = cpu->instruction;
708 u32 v = cpu->R[REG_POS(i,16)];
709 u32 shift_op;
710 ROR_IMM;
711 OPSUBS(2, 4);
712 }
713
714 static u32 FASTCALL OP_SUB_S_ROR_REG(armcpu_t *cpu)
715 {
716 u32 i = cpu->instruction;
717 u32 v = cpu->R[REG_POS(i,16)];
718 ROR_REG;
719 OPSUBS(3, 5);
720 }
721
722 static u32 FASTCALL OP_SUB_S_IMM_VAL(armcpu_t *cpu)
723 {
724 u32 i = cpu->instruction;
725 u32 v = cpu->R[REG_POS(i,16)];
726 IMM_VALUE;
727 OPSUBS(2, 4);
728 }
729
730 //------------------RSB------------------------
731
732 #define OP_RSB(a, b) cpu->R[REG_POS(i,12)] = shift_op - cpu->R[REG_POS(i,16)];\
733 if(REG_POS(i,12)==15)\
734 {\
735 cpu->next_instruction = cpu->R[15];\
736 return b;\
737 }\
738 return a;
739
740 #define OP_RSBS(a, b) cpu->R[REG_POS(i,12)] = shift_op - v;\
741 if(REG_POS(i,12)==15)\
742 {\
743 Status_Reg SPSR = cpu->SPSR;\
744 armcpu_switchMode(cpu, SPSR.bits.mode);\
745 cpu->CPSR=SPSR;\
746 cpu->R[15] &= (0XFFFFFFFC|(((u32)SPSR.bits.T)<<1));\
747 cpu->next_instruction = cpu->R[15];\
748 return b;\
749 }\
750 cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,12)]);\
751 cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0);\
752 cpu->CPSR.bits.C = !UNSIGNED_UNDERFLOW(shift_op, v, cpu->R[REG_POS(i,12)]);\
753 cpu->CPSR.bits.V = SIGNED_UNDERFLOW(shift_op, v, cpu->R[REG_POS(i,12)]);\
754 return a;
755
756 static u32 FASTCALL OP_RSB_LSL_IMM(armcpu_t *cpu)
757 {
758 u32 i = cpu->instruction;
759 u32 shift_op;
760 LSL_IMM;
761 OP_RSB(1, 3);
762 }
763
764 static u32 FASTCALL OP_RSB_LSL_REG(armcpu_t *cpu)
765 {
766 u32 i = cpu->instruction;
767 LSL_REG;
768 OP_RSB(2, 4);
769 }
770
771 static u32 FASTCALL OP_RSB_LSR_IMM(armcpu_t *cpu)
772 {
773 u32 i = cpu->instruction;
774 u32 shift_op;
775 LSR_IMM;
776 OP_RSB(1, 3);
777 }
778
779 static u32 FASTCALL OP_RSB_LSR_REG(armcpu_t *cpu)
780 {
781 u32 i = cpu->instruction;
782 LSR_REG;
783 OP_RSB(2, 4);
784 }
785
786 static u32 FASTCALL OP_RSB_ASR_IMM(armcpu_t *cpu)
787 {
788 u32 i = cpu->instruction;
789 u32 shift_op;
790 ASR_IMM;
791 OP_RSB(1, 3);
792 }
793
794 static u32 FASTCALL OP_RSB_ASR_REG(armcpu_t *cpu)
795 {
796 u32 i = cpu->instruction;
797 ASR_REG;
798 OP_RSB(2, 4);
799 }
800
801 static u32 FASTCALL OP_RSB_ROR_IMM(armcpu_t *cpu)
802 {
803 u32 i = cpu->instruction;
804 u32 shift_op;
805 ROR_IMM;
806 OP_RSB(1, 3);
807 }
808
809 static u32 FASTCALL OP_RSB_ROR_REG(armcpu_t *cpu)
810 {
811 u32 i = cpu->instruction;
812 ROR_REG;
813 OP_RSB(2, 4);
814 }
815
816 static u32 FASTCALL OP_RSB_IMM_VAL(armcpu_t *cpu)
817 {
818 u32 i = cpu->instruction;
819 IMM_VALUE;
820 OP_RSB(1, 3);
821 }
822
823 static u32 FASTCALL OP_RSB_S_LSL_IMM(armcpu_t *cpu)
824 {
825 u32 i = cpu->instruction;
826 u32 v = cpu->R[REG_POS(i,16)];
827 u32 shift_op;
828 LSL_IMM;
829 OP_RSBS(2, 4);
830 }
831
832 static u32 FASTCALL OP_RSB_S_LSL_REG(armcpu_t *cpu)
833 {
834 u32 i = cpu->instruction;
835 u32 v = cpu->R[REG_POS(i,16)];
836 LSL_REG;
837 OP_RSBS(3, 5);
838 }
839
840 static u32 FASTCALL OP_RSB_S_LSR_IMM(armcpu_t *cpu)
841 {
842 u32 i = cpu->instruction;
843 u32 v = cpu->R[REG_POS(i,16)];
844 u32 shift_op;
845 LSR_IMM;
846 OP_RSBS(2, 4);
847 }
848
849 static u32 FASTCALL OP_RSB_S_LSR_REG(armcpu_t *cpu)
850 {
851 u32 i = cpu->instruction;
852 u32 v = cpu->R[REG_POS(i,16)];
853 LSR_REG;
854 OP_RSBS(3, 5);
855 }
856
857 static u32 FASTCALL OP_RSB_S_ASR_IMM(armcpu_t *cpu)
858 {
859 u32 i = cpu->instruction;
860 u32 v = cpu->R[REG_POS(i,16)];
861 u32 shift_op;
862 ASR_IMM;
863 OP_RSBS(2, 4);
864 }
865
866 static u32 FASTCALL OP_RSB_S_ASR_REG(armcpu_t *cpu)
867 {
868 u32 i = cpu->instruction;
869 u32 v = cpu->R[REG_POS(i,16)];
870 ASR_REG;
871 OP_RSBS(3, 5);
872 }
873
874 static u32 FASTCALL OP_RSB_S_ROR_IMM(armcpu_t *cpu)
875 {
876 u32 i = cpu->instruction;
877 u32 v = cpu->R[REG_POS(i,16)];
878 u32 shift_op;
879 ROR_IMM;
880 OP_RSBS(2, 4);
881 }
882
883 static u32 FASTCALL OP_RSB_S_ROR_REG(armcpu_t *cpu)
884 {
885 u32 i = cpu->instruction;
886 u32 v = cpu->R[REG_POS(i,16)];
887 ROR_REG;
888 OP_RSBS(3, 5);
889 }
890
891 static u32 FASTCALL OP_RSB_S_IMM_VAL(armcpu_t *cpu)
892 {
893 u32 i = cpu->instruction;
894 u32 v = cpu->R[REG_POS(i,16)];
895 IMM_VALUE;
896 OP_RSBS(2, 4);
897 }
898
899 //------------------ADD-----------------------------------
900
901 #define OP_ADD(a, b) cpu->R[REG_POS(i,12)] = cpu->R[REG_POS(i,16)] + shift_op;\
902 if(REG_POS(i,12)==15)\
903 {\
904 cpu->next_instruction = cpu->R[15];\
905 return b;\
906 }\
907 return a;
908
909 static u32 FASTCALL OP_ADD_LSL_IMM(armcpu_t *cpu)
910 {
911 u32 i = cpu->instruction;
912 u32 shift_op;
913 LSL_IMM;
914 OP_ADD(1, 3);
915 }
916
917 static u32 FASTCALL OP_ADD_LSL_REG(armcpu_t *cpu)
918 {
919 u32 i = cpu->instruction;
920 LSL_REG;
921 OP_ADD(2, 4);
922 }
923
924 static u32 FASTCALL OP_ADD_LSR_IMM(armcpu_t *cpu)
925 {
926 u32 i = cpu->instruction;
927 u32 shift_op;
928 LSR_IMM;
929 OP_ADD(1, 3);
930 }
931
932 static u32 FASTCALL OP_ADD_LSR_REG(armcpu_t *cpu)
933 {
934 u32 i = cpu->instruction;
935 LSR_REG;
936 OP_ADD(2, 4);
937 }
938
939 static u32 FASTCALL OP_ADD_ASR_IMM(armcpu_t *cpu)
940 {
941 u32 i = cpu->instruction;
942 u32 shift_op;
943 ASR_IMM;
944 OP_ADD(1, 3);
945 }
946
947 static u32 FASTCALL OP_ADD_ASR_REG(armcpu_t *cpu)
948 {
949 u32 i = cpu->instruction;
950 ASR_REG;
951 OP_ADD(2, 4);
952 }
953
954 static u32 FASTCALL OP_ADD_ROR_IMM(armcpu_t *cpu)
955 {
956 u32 i = cpu->instruction;
957 u32 shift_op;
958 ROR_IMM;
959 OP_ADD(1, 3);
960 }
961
962 static u32 FASTCALL OP_ADD_ROR_REG(armcpu_t *cpu)
963 {
964 u32 i = cpu->instruction;
965 ROR_REG;
966 OP_ADD(2, 4);
967 }
968
969 static u32 FASTCALL OP_ADD_IMM_VAL(armcpu_t *cpu)
970 {
971 u32 i = cpu->instruction;
972 IMM_VALUE;
973 OP_ADD(1, 3);
974 }
975
976 #define OP_ADDS(a, b) cpu->R[REG_POS(i,12)] = v + shift_op;\
977 if(REG_POS(i,12)==15)\
978 {\
979 Status_Reg SPSR = cpu->SPSR;\
980 armcpu_switchMode(cpu, SPSR.bits.mode);\
981 cpu->CPSR=SPSR;\
982 cpu->R[15] &= (0XFFFFFFFC|(((u32)SPSR.bits.T)<<1));\
983 cpu->next_instruction = cpu->R[15];\
984 return b;\
985 }\
986 cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,12)]);\
987 cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0);\
988 cpu->CPSR.bits.C = UNSIGNED_OVERFLOW(v, shift_op, cpu->R[REG_POS(i,12)]);\
989 cpu->CPSR.bits.V = SIGNED_OVERFLOW(v, shift_op, cpu->R[REG_POS(i,12)]);\
990 return a;
991
992 static u32 FASTCALL OP_ADD_S_LSL_IMM(armcpu_t *cpu)
993 {
994 u32 i = cpu->instruction;
995 u32 v = cpu->R[REG_POS(i,16)];
996 u32 shift_op;
997 LSL_IMM;
998 OP_ADDS(2, 4);
999 }
1000
1001 static u32 FASTCALL OP_ADD_S_LSL_REG(armcpu_t *cpu)
1002 {
1003 u32 i = cpu->instruction;
1004 u32 v = cpu->R[REG_POS(i,16)];
1005 LSL_REG;
1006 OP_ADDS(3, 5);
1007 }
1008
1009 static u32 FASTCALL OP_ADD_S_LSR_IMM(armcpu_t *cpu)
1010 {
1011 u32 i = cpu->instruction;
1012 u32 v = cpu->R[REG_POS(i,16)];
1013 u32 shift_op;
1014 LSR_IMM;
1015 OP_ADDS(2, 4);
1016 }
1017
1018 static u32 FASTCALL OP_ADD_S_LSR_REG(armcpu_t *cpu)
1019 {
1020 u32 i = cpu->instruction;
1021 u32 v = cpu->R[REG_POS(i,16)];
1022 LSR_REG;
1023 OP_ADDS(3, 5);
1024 }
1025
1026 static u32 FASTCALL OP_ADD_S_ASR_IMM(armcpu_t *cpu)
1027 {
1028 u32 i = cpu->instruction;
1029 u32 v = cpu->R[REG_POS(i,16)];
1030 u32 shift_op;
1031 ASR_IMM;
1032 OP_ADDS(2, 4);
1033 }
1034
1035 static u32 FASTCALL OP_ADD_S_ASR_REG(armcpu_t *cpu)
1036 {
1037 u32 i = cpu->instruction;
1038 u32 v = cpu->R[REG_POS(i,16)];
1039 ASR_REG;
1040 OP_ADDS(3, 5);
1041 }
1042
1043 static u32 FASTCALL OP_ADD_S_ROR_IMM(armcpu_t *cpu)
1044 {
1045 u32 i = cpu->instruction;
1046 u32 v = cpu->R[REG_POS(i,16)];
1047 u32 shift_op;
1048 ROR_IMM;
1049 OP_ADDS(2, 4);
1050 }
1051
1052 static u32 FASTCALL OP_ADD_S_ROR_REG(armcpu_t *cpu)
1053 {
1054 u32 i = cpu->instruction;
1055 u32 v = cpu->R[REG_POS(i,16)];
1056 ROR_REG;
1057 OP_ADDS(3, 5);
1058 }
1059
1060 static u32 FASTCALL OP_ADD_S_IMM_VAL(armcpu_t *cpu)
1061 {
1062 u32 i = cpu->instruction;
1063 u32 v = cpu->R[REG_POS(i,16)];
1064 IMM_VALUE;
1065 OP_ADDS(2, 4);
1066 }
1067
1068 //------------------ADC-----------------------------------
1069
1070 #define OP_ADC(a, b) cpu->R[REG_POS(i,12)] = cpu->R[REG_POS(i,16)] + shift_op + cpu->CPSR.bits.C;\
1071 if(REG_POS(i,12)==15)\
1072 {\
1073 cpu->next_instruction = cpu->R[15];\
1074 return b;\
1075 }\
1076 return a;
1077
1078 static u32 FASTCALL OP_ADC_LSL_IMM(armcpu_t *cpu)
1079 {
1080 u32 i = cpu->instruction;
1081 u32 shift_op;
1082 LSL_IMM;
1083 OP_ADC(1, 3);
1084 }
1085
1086 static u32 FASTCALL OP_ADC_LSL_REG(armcpu_t *cpu)
1087 {
1088 u32 i = cpu->instruction;
1089 LSL_REG;
1090 OP_ADC(2, 4);
1091 }
1092
1093 static u32 FASTCALL OP_ADC_LSR_IMM(armcpu_t *cpu)
1094 {
1095 u32 i = cpu->instruction;
1096 u32 shift_op;
1097 LSR_IMM;
1098 OP_ADC(1, 3);
1099 }
1100
1101 static u32 FASTCALL OP_ADC_LSR_REG(armcpu_t *cpu)
1102 {
1103 u32 i = cpu->instruction;
1104 LSR_REG;
1105 OP_ADC(2, 4);
1106 }
1107
1108 static u32 FASTCALL OP_ADC_ASR_IMM(armcpu_t *cpu)
1109 {
1110 u32 i = cpu->instruction;
1111 u32 shift_op;
1112 ASR_IMM;
1113 OP_ADC(1, 3);
1114 }
1115
1116 static u32 FASTCALL OP_ADC_ASR_REG(armcpu_t *cpu)
1117 {
1118 u32 i = cpu->instruction;
1119 ASR_REG;
1120 OP_ADC(2, 4);
1121 }
1122
1123 static u32 FASTCALL OP_ADC_ROR_IMM(armcpu_t *cpu)
1124 {
1125 u32 i = cpu->instruction;
1126 u32 shift_op;
1127 ROR_IMM;
1128 OP_ADC(1, 3);
1129 }
1130
1131 static u32 FASTCALL OP_ADC_ROR_REG(armcpu_t *cpu)
1132 {
1133 u32 i = cpu->instruction;
1134 ROR_REG;
1135 OP_ADC(2, 4);
1136 }
1137
1138 static u32 FASTCALL OP_ADC_IMM_VAL(armcpu_t *cpu)
1139 {
1140 u32 i = cpu->instruction;
1141 IMM_VALUE;
1142 OP_ADC(1, 3);
1143 }
1144
1145 #define OP_ADCS(a, b) \
1146 { \
1147 u32 tmp = shift_op + cpu->CPSR.bits.C;\
1148 cpu->R[REG_POS(i,12)] = v + tmp;\
1149 if(REG_POS(i,12)==15)\
1150 {\
1151 Status_Reg SPSR = cpu->SPSR;\
1152 armcpu_switchMode(cpu, SPSR.bits.mode);\
1153 cpu->CPSR=SPSR;\
1154 cpu->R[15] &= (0XFFFFFFFC|(((u32)SPSR.bits.T)<<1));\
1155 cpu->next_instruction = cpu->R[15];\
1156 return b;\
1157 }\
1158 cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,12)]);\
1159 cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0);\
1160 cpu->CPSR.bits.C = UNSIGNED_OVERFLOW(shift_op, cpu->CPSR.bits.C, tmp) | UNSIGNED_OVERFLOW(v, tmp, cpu->R[REG_POS(i,12)]);\
1161 cpu->CPSR.bits.V = SIGNED_OVERFLOW(shift_op, cpu->CPSR.bits.C, tmp) | SIGNED_OVERFLOW(v, tmp, cpu->R[REG_POS(i,12)]);\
1162 return a; \
1163 }
1164
1165 static u32 FASTCALL OP_ADC_S_LSL_IMM(armcpu_t *cpu)
1166 {
1167 u32 i = cpu->instruction;
1168 u32 v = cpu->R[REG_POS(i,16)];
1169 u32 shift_op;
1170 LSL_IMM;
1171 OP_ADCS(2, 4);
1172 }
1173
1174 static u32 FASTCALL OP_ADC_S_LSL_REG(armcpu_t *cpu)
1175 {
1176 u32 i = cpu->instruction;
1177 u32 v = cpu->R[REG_POS(i,16)];
1178 LSL_REG;
1179 OP_ADCS(3, 5);
1180 }
1181
1182 static u32 FASTCALL OP_ADC_S_LSR_IMM(armcpu_t *cpu)
1183 {
1184 u32 i = cpu->instruction;
1185 u32 v = cpu->R[REG_POS(i,16)];
1186 u32 shift_op;
1187 LSR_IMM;
1188 OP_ADCS(2, 4);
1189 }
1190
1191 static u32 FASTCALL OP_ADC_S_LSR_REG(armcpu_t *cpu)
1192 {
1193 u32 i = cpu->instruction;
1194 u32 v = cpu->R[REG_POS(i,16)];
1195 LSR_REG;
1196 OP_ADCS(3, 5);
1197 }
1198
1199 static u32 FASTCALL OP_ADC_S_ASR_IMM(armcpu_t *cpu)
1200 {
1201 u32 i = cpu->instruction;
1202 u32 v = cpu->R[REG_POS(i,16)];
1203 u32 shift_op;
1204 ASR_IMM;
1205 OP_ADCS(2, 4);
1206 }
1207
1208 static u32 FASTCALL OP_ADC_S_ASR_REG(armcpu_t *cpu)
1209 {
1210 u32 i = cpu->instruction;
1211 u32 v = cpu->R[REG_POS(i,16)];
1212 ASR_REG;
1213 OP_ADCS(3, 5);
1214 }
1215
1216 static u32 FASTCALL OP_ADC_S_ROR_IMM(armcpu_t *cpu)
1217 {
1218 u32 i = cpu->instruction;
1219 u32 v = cpu->R[REG_POS(i,16)];
1220 u32 shift_op;
1221 ROR_IMM;
1222 OP_ADCS(2, 4);
1223 }
1224
1225 static u32 FASTCALL OP_ADC_S_ROR_REG(armcpu_t *cpu)
1226 {
1227 u32 i = cpu->instruction;
1228 u32 v = cpu->R[REG_POS(i,16)];
1229 ROR_REG;
1230 OP_ADCS(3, 5);
1231 }
1232
1233 static u32 FASTCALL OP_ADC_S_IMM_VAL(armcpu_t *cpu)
1234 {
1235 u32 i = cpu->instruction;
1236 u32 v = cpu->R[REG_POS(i,16)];
1237 IMM_VALUE;
1238 OP_ADCS(2, 4);
1239 }
1240
1241 //-------------SBC-------------------------------------
1242
1243 #define OP_SBC(a, b) cpu->R[REG_POS(i,12)] = cpu->R[REG_POS(i,16)] - shift_op - (!cpu->CPSR.bits.C);\
1244 if(REG_POS(i,12)==15)\
1245 {\
1246 cpu->next_instruction = cpu->R[15];\
1247 return b;\
1248 }\
1249 return a;
1250
1251 static u32 FASTCALL OP_SBC_LSL_IMM(armcpu_t *cpu)
1252 {
1253 u32 i = cpu->instruction;
1254 u32 shift_op;
1255 LSL_IMM;
1256 OP_SBC(1, 3);
1257 }
1258
1259 static u32 FASTCALL OP_SBC_LSL_REG(armcpu_t *cpu)
1260 {
1261 u32 i = cpu->instruction;
1262 LSL_REG;
1263 OP_SBC(2, 4);
1264 }
1265
1266 static u32 FASTCALL OP_SBC_LSR_IMM(armcpu_t *cpu)
1267 {
1268 u32 i = cpu->instruction;
1269 u32 shift_op;
1270 LSR_IMM;
1271 OP_SBC(1, 3);
1272 }
1273
1274 static u32 FASTCALL OP_SBC_LSR_REG(armcpu_t *cpu)
1275 {
1276 u32 i = cpu->instruction;
1277 LSR_REG;
1278 OP_SBC(2, 4);
1279 }
1280
1281 static u32 FASTCALL OP_SBC_ASR_IMM(armcpu_t *cpu)
1282 {
1283 u32 i = cpu->instruction;
1284 u32 shift_op;
1285 ASR_IMM;
1286 OP_SBC(1, 3);
1287 }
1288
1289 static u32 FASTCALL OP_SBC_ASR_REG(armcpu_t *cpu)
1290 {
1291 u32 i = cpu->instruction;
1292 ASR_REG;
1293 OP_SBC(2, 4);
1294 }
1295
1296 static u32 FASTCALL OP_SBC_ROR_IMM(armcpu_t *cpu)
1297 {
1298 u32 i = cpu->instruction;
1299 u32 shift_op;
1300 ROR_IMM;
1301 OP_SBC(1, 3);
1302 }
1303
1304 static u32 FASTCALL OP_SBC_ROR_REG(armcpu_t *cpu)
1305 {
1306 u32 i = cpu->instruction;
1307 ROR_REG;
1308 OP_SBC(2, 4);
1309 }
1310
1311 static u32 FASTCALL OP_SBC_IMM_VAL(armcpu_t *cpu)
1312 {
1313 u32 i = cpu->instruction;
1314 IMM_VALUE;
1315 OP_SBC(1, 3);
1316 }
1317
1318 #define OP_SBCS(a, b) \
1319 { \
1320 u32 tmp = v - (!cpu->CPSR.bits.C);\
1321 cpu->R[REG_POS(i,12)] = tmp - shift_op;\
1322 if(REG_POS(i,12)==15)\
1323 {\
1324 Status_Reg SPSR = cpu->SPSR;\
1325 armcpu_switchMode(cpu, SPSR.bits.mode);\
1326 cpu->CPSR=SPSR;\
1327 cpu->R[15] &= (0XFFFFFFFC|(((u32)SPSR.bits.T)<<1));\
1328 cpu->next_instruction = cpu->R[15];\
1329 return b;\
1330 }\
1331 cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,12)]);\
1332 cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0);\
1333 cpu->CPSR.bits.C = (!UNSIGNED_UNDERFLOW(v, (!cpu->CPSR.bits.C), tmp)) & (!UNSIGNED_UNDERFLOW(tmp, shift_op, cpu->R[REG_POS(i,12)]));\
1334 cpu->CPSR.bits.V = SIGNED_UNDERFLOW(v, (!cpu->CPSR.bits.C), tmp) | SIGNED_UNDERFLOW(tmp, shift_op, cpu->R[REG_POS(i,12)]);\
1335 return a; \
1336 }
1337
1338 static u32 FASTCALL OP_SBC_S_LSL_IMM(armcpu_t *cpu)
1339 {
1340 u32 i = cpu->instruction;
1341 u32 v = cpu->R[REG_POS(i,16)];
1342 u32 shift_op;
1343 LSL_IMM;
1344 OP_SBCS(2, 4);
1345 }
1346
1347 static u32 FASTCALL OP_SBC_S_LSL_REG(armcpu_t *cpu)
1348 {
1349 u32 i = cpu->instruction;
1350 u32 v = cpu->R[REG_POS(i,16)];
1351 LSL_REG;
1352 OP_SBCS(3, 5);
1353 }
1354
1355 static u32 FASTCALL OP_SBC_S_LSR_IMM(armcpu_t *cpu)
1356 {
1357 u32 i = cpu->instruction;
1358 u32 v = cpu->R[REG_POS(i,16)];
1359 u32 shift_op;
1360 LSR_IMM;
1361 OP_SBCS(2, 4);
1362 }
1363
1364 static u32 FASTCALL OP_SBC_S_LSR_REG(armcpu_t *cpu)
1365 {
1366 u32 i = cpu->instruction;
1367 u32 v = cpu->R[REG_POS(i,16)];
1368 LSR_REG;
1369 OP_SBCS(3, 5);
1370 }
1371
1372 static u32 FASTCALL OP_SBC_S_ASR_IMM(armcpu_t *cpu)
1373 {
1374 u32 i = cpu->instruction;
1375 u32 v = cpu->R[REG_POS(i,16)];
1376 u32 shift_op;
1377 ASR_IMM;
1378 OP_SBCS(2, 4);
1379 }
1380
1381 static u32 FASTCALL OP_SBC_S_ASR_REG(armcpu_t *cpu)
1382 {
1383 u32 i = cpu->instruction;
1384 u32 v = cpu->R[REG_POS(i,16)];
1385 ASR_REG;
1386 OP_SBCS(3, 5);
1387 }
1388
1389 static u32 FASTCALL OP_SBC_S_ROR_IMM(armcpu_t *cpu)
1390 {
1391 u32 i = cpu->instruction;
1392 u32 v = cpu->R[REG_POS(i,16)];
1393 u32 shift_op;
1394 ROR_IMM;
1395 OP_SBCS(2, 4);
1396 }
1397
1398 static u32 FASTCALL OP_SBC_S_ROR_REG(armcpu_t *cpu)
1399 {
1400 u32 i = cpu->instruction;
1401 u32 v = cpu->R[REG_POS(i,16)];
1402 ROR_REG;
1403 OP_SBCS(3, 5);
1404 }
1405
1406 static u32 FASTCALL OP_SBC_S_IMM_VAL(armcpu_t *cpu)
1407 {
1408 u32 i = cpu->instruction;
1409 u32 v = cpu->R[REG_POS(i,16)];
1410 IMM_VALUE;
1411 OP_SBCS(2, 4);
1412 }
1413
1414 //---------------RSC----------------------------------
1415
1416 #define OP_RSC(a, b) cpu->R[REG_POS(i,12)] = shift_op - cpu->R[REG_POS(i,16)] - (!cpu->CPSR.bits.C);\
1417 if(REG_POS(i,12)==15)\
1418 {\
1419 cpu->next_instruction = cpu->R[15];\
1420 return b;\
1421 }\
1422 return a;
1423
1424 static u32 FASTCALL OP_RSC_LSL_IMM(armcpu_t *cpu)
1425 {
1426 u32 i = cpu->instruction;
1427 u32 shift_op;
1428 LSL_IMM;
1429 OP_RSC(1, 3);
1430 }
1431
1432 static u32 FASTCALL OP_RSC_LSL_REG(armcpu_t *cpu)
1433 {
1434 u32 i = cpu->instruction;
1435 LSL_REG;
1436 OP_RSC(2, 4);
1437 }
1438
1439 static u32 FASTCALL OP_RSC_LSR_IMM(armcpu_t *cpu)
1440 {
1441 u32 i = cpu->instruction;
1442 u32 shift_op;
1443 LSR_IMM;
1444 OP_RSC(1, 3);
1445 }
1446
1447 static u32 FASTCALL OP_RSC_LSR_REG(armcpu_t *cpu)
1448 {
1449 u32 i = cpu->instruction;
1450 LSR_REG;
1451 OP_RSC(2, 4);
1452 }
1453
1454 static u32 FASTCALL OP_RSC_ASR_IMM(armcpu_t *cpu)
1455 {
1456 u32 i = cpu->instruction;
1457 u32 shift_op;
1458 ASR_IMM;
1459 OP_RSC(1, 3);
1460 }
1461
1462 static u32 FASTCALL OP_RSC_ASR_REG(armcpu_t *cpu)
1463 {
1464 u32 i = cpu->instruction;
1465 ASR_REG;
1466 OP_RSC(2, 4);
1467 }
1468
1469 static u32 FASTCALL OP_RSC_ROR_IMM(armcpu_t *cpu)
1470 {
1471 u32 i = cpu->instruction;
1472 u32 shift_op;
1473 ROR_IMM;
1474 OP_RSC(1, 3);
1475 }
1476
1477 static u32 FASTCALL OP_RSC_ROR_REG(armcpu_t *cpu)
1478 {
1479 u32 i = cpu->instruction;
1480 ROR_REG;
1481 OP_RSC(2, 4);
1482 }
1483
1484 static u32 FASTCALL OP_RSC_IMM_VAL(armcpu_t *cpu)
1485 {
1486 u32 i = cpu->instruction;
1487 IMM_VALUE;
1488 OP_RSC(1, 3);
1489 }
1490
1491 #define OP_RSCS(a,b) \
1492 { \
1493 u32 tmp = shift_op - (!cpu->CPSR.bits.C);\
1494 cpu->R[REG_POS(i,12)] = tmp - v;\
1495 if(REG_POS(i,12)==15)\
1496 {\
1497 Status_Reg SPSR = cpu->SPSR;\
1498 armcpu_switchMode(cpu, SPSR.bits.mode);\
1499 cpu->CPSR=SPSR;\
1500 cpu->R[15] &= (0XFFFFFFFC|(((u32)SPSR.bits.T)<<1));\
1501 cpu->next_instruction = cpu->R[15];\
1502 return b;\
1503 }\
1504 cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,12)]);\
1505 cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0);\
1506 cpu->CPSR.bits.C = (!UNSIGNED_UNDERFLOW(shift_op, (!cpu->CPSR.bits.C), tmp)) & (!UNSIGNED_UNDERFLOW(tmp, v, cpu->R[REG_POS(i,12)]));\
1507 cpu->CPSR.bits.V = SIGNED_UNDERFLOW(shift_op, (!cpu->CPSR.bits.C), tmp) | SIGNED_UNDERFLOW(tmp, v, cpu->R[REG_POS(i,12)]);\
1508 return a; \
1509 }
1510
1511 static u32 FASTCALL OP_RSC_S_LSL_IMM(armcpu_t *cpu)
1512 {
1513 u32 i = cpu->instruction;
1514 u32 v = cpu->R[REG_POS(i,16)];
1515 u32 shift_op;
1516 LSL_IMM;
1517 OP_RSCS(2,4);
1518 }
1519
1520 static u32 FASTCALL OP_RSC_S_LSL_REG(armcpu_t *cpu)
1521 {
1522 u32 i = cpu->instruction;
1523 u32 v = cpu->R[REG_POS(i,16)];
1524 LSL_REG;
1525 OP_RSCS(3,5);
1526 }
1527
1528 static u32 FASTCALL OP_RSC_S_LSR_IMM(armcpu_t *cpu)
1529 {
1530 u32 i = cpu->instruction;
1531 u32 v = cpu->R[REG_POS(i,16)];
1532 u32 shift_op;
1533 LSR_IMM;
1534 OP_RSCS(2,4);
1535 }
1536
1537 static u32 FASTCALL OP_RSC_S_LSR_REG(armcpu_t *cpu)
1538 {
1539 u32 i = cpu->instruction;
1540 u32 v = cpu->R[REG_POS(i,16)];
1541 LSR_REG;
1542 OP_RSCS(3,5);
1543 }
1544
1545 static u32 FASTCALL OP_RSC_S_ASR_IMM(armcpu_t *cpu)
1546 {
1547 u32 i = cpu->instruction;
1548 u32 v = cpu->R[REG_POS(i,16)];
1549 u32 shift_op;
1550 ASR_IMM;
1551 OP_RSCS(2,4);
1552 }
1553
1554 static u32 FASTCALL OP_RSC_S_ASR_REG(armcpu_t *cpu)
1555 {
1556 u32 i = cpu->instruction;
1557 u32 v = cpu->R[REG_POS(i,16)];
1558 ASR_REG;
1559 OP_RSCS(3,5);
1560 }
1561
1562 static u32 FASTCALL OP_RSC_S_ROR_IMM(armcpu_t *cpu)
1563 {
1564 u32 i = cpu->instruction;
1565 u32 v = cpu->R[REG_POS(i,16)];
1566 u32 shift_op;
1567 ROR_IMM;
1568 OP_RSCS(2,4);
1569 }
1570
1571 static u32 FASTCALL OP_RSC_S_ROR_REG(armcpu_t *cpu)
1572 {
1573 u32 i = cpu->instruction;
1574 u32 v = cpu->R[REG_POS(i,16)];
1575 ROR_REG;
1576 OP_RSCS(3,5);
1577 }
1578
1579 static u32 FASTCALL OP_RSC_S_IMM_VAL(armcpu_t *cpu)
1580 {
1581 u32 i = cpu->instruction;
1582 u32 v = cpu->R[REG_POS(i,16)];
1583 IMM_VALUE;
1584 OP_RSCS(2,4);
1585 }
1586
1587 //-------------------TST----------------------------
1588
1589 #define OP_TST(a) \
1590 { \
1591 unsigned tmp = cpu->R[REG_POS(i,16)] & shift_op;\
1592 cpu->CPSR.bits.C = c;\
1593 cpu->CPSR.bits.N = BIT31(tmp);\
1594 cpu->CPSR.bits.Z = (tmp==0);\
1595 return a; \
1596 }
1597
1598 static u32 FASTCALL OP_TST_LSL_IMM(armcpu_t *cpu)
1599 {
1600 u32 i = cpu->instruction;
1601 S_LSL_IMM;
1602 OP_TST(1);
1603 }
1604
1605 static u32 FASTCALL OP_TST_LSL_REG(armcpu_t *cpu)
1606 {
1607 u32 i = cpu->instruction;
1608 S_LSL_REG;
1609 OP_TST(2);
1610 }
1611
1612 static u32 FASTCALL OP_TST_LSR_IMM(armcpu_t *cpu)
1613 {
1614 u32 i = cpu->instruction;
1615 S_LSR_IMM;
1616 OP_TST(1);
1617 }
1618
1619 static u32 FASTCALL OP_TST_LSR_REG(armcpu_t *cpu)
1620 {
1621 u32 i = cpu->instruction;
1622 S_LSR_REG;
1623 OP_TST(2);
1624 }
1625
1626 static u32 FASTCALL OP_TST_ASR_IMM(armcpu_t *cpu)
1627 {
1628 u32 i = cpu->instruction;
1629 S_ASR_IMM;
1630 OP_TST(1);
1631 }
1632
1633 static u32 FASTCALL OP_TST_ASR_REG(armcpu_t *cpu)
1634 {
1635 u32 i = cpu->instruction;
1636 S_ASR_REG;
1637 OP_TST(2);
1638 }
1639
1640 static u32 FASTCALL OP_TST_ROR_IMM(armcpu_t *cpu)
1641 {
1642 u32 i = cpu->instruction;
1643 S_ROR_IMM;
1644 OP_TST(1);
1645 }
1646
1647 static u32 FASTCALL OP_TST_ROR_REG(armcpu_t *cpu)
1648 {
1649 u32 i = cpu->instruction;
1650 S_ROR_REG;
1651 OP_TST(2);
1652 }
1653
1654 static u32 FASTCALL OP_TST_IMM_VAL(armcpu_t *cpu)
1655 {
1656 u32 i = cpu->instruction;
1657 S_IMM_VALUE;
1658 OP_TST(1);
1659 }
1660
1661 //-------------------TEQ----------------------------
1662
1663 #define OP_TEQ(a) \
1664 { \
1665 unsigned tmp = cpu->R[REG_POS(i,16)] ^ shift_op;\
1666 cpu->CPSR.bits.C = c;\
1667 cpu->CPSR.bits.N = BIT31(tmp);\
1668 cpu->CPSR.bits.Z = (tmp==0);\
1669 return a; \
1670 }
1671
1672 static u32 FASTCALL OP_TEQ_LSL_IMM(armcpu_t *cpu)
1673 {
1674 u32 i = cpu->instruction;
1675 S_LSL_IMM;
1676 OP_TEQ(1);
1677 }
1678
1679 static u32 FASTCALL OP_TEQ_LSL_REG(armcpu_t *cpu)
1680 {
1681 u32 i = cpu->instruction;
1682 S_LSL_REG;
1683 OP_TEQ(2);
1684 }
1685
1686 static u32 FASTCALL OP_TEQ_LSR_IMM(armcpu_t *cpu)
1687 {
1688 u32 i = cpu->instruction;
1689 S_LSR_IMM;
1690 OP_TEQ(1);
1691 }
1692
1693 static u32 FASTCALL OP_TEQ_LSR_REG(armcpu_t *cpu)
1694 {
1695 u32 i = cpu->instruction;
1696 S_LSR_REG;
1697 OP_TEQ(2);
1698 }
1699
1700 static u32 FASTCALL OP_TEQ_ASR_IMM(armcpu_t *cpu)
1701 {
1702 u32 i = cpu->instruction;
1703 S_ASR_IMM;
1704 OP_TEQ(1);
1705 }
1706
1707 static u32 FASTCALL OP_TEQ_ASR_REG(armcpu_t *cpu)
1708 {
1709 u32 i = cpu->instruction;
1710 S_ASR_REG;
1711 OP_TEQ(2);
1712 }
1713
1714 static u32 FASTCALL OP_TEQ_ROR_IMM(armcpu_t *cpu)
1715 {
1716 u32 i = cpu->instruction;
1717 S_ROR_IMM;
1718 OP_TEQ(1);
1719 }
1720
1721 static u32 FASTCALL OP_TEQ_ROR_REG(armcpu_t *cpu)
1722 {
1723 u32 i = cpu->instruction;
1724 S_ROR_REG;
1725 OP_TEQ(2);
1726 }
1727
1728 static u32 FASTCALL OP_TEQ_IMM_VAL(armcpu_t *cpu)
1729 {
1730 u32 i = cpu->instruction;
1731 S_IMM_VALUE;
1732 OP_TEQ(1);
1733 }
1734
1735 //-------------CMP-------------------------------------
1736
1737 #define OP_CMP(a) \
1738 { \
1739 u32 tmp = cpu->R[REG_POS(i,16)] - shift_op;\
1740 cpu->CPSR.bits.N = BIT31(tmp);\
1741 cpu->CPSR.bits.Z = (tmp==0);\
1742 cpu->CPSR.bits.C = !UNSIGNED_UNDERFLOW(cpu->R[REG_POS(i,16)], shift_op, tmp);\
1743 cpu->CPSR.bits.V = SIGNED_UNDERFLOW(cpu->R[REG_POS(i,16)], shift_op, tmp);\
1744 return a; \
1745 }
1746
1747 static u32 FASTCALL OP_CMP_LSL_IMM(armcpu_t *cpu)
1748 {
1749 u32 i = cpu->instruction;
1750 u32 shift_op;
1751 LSL_IMM;
1752 OP_CMP(1);
1753 }
1754
1755 static u32 FASTCALL OP_CMP_LSL_REG(armcpu_t *cpu)
1756 {
1757 u32 i = cpu->instruction;
1758 LSL_REG;
1759 OP_CMP(2);
1760 }
1761
1762 static u32 FASTCALL OP_CMP_LSR_IMM(armcpu_t *cpu)
1763 {
1764 u32 i = cpu->instruction;
1765 u32 shift_op;
1766 LSR_IMM;
1767 OP_CMP(1);
1768 }
1769
1770 static u32 FASTCALL OP_CMP_LSR_REG(armcpu_t *cpu)
1771 {
1772 u32 i = cpu->instruction;
1773 LSR_REG;
1774 OP_CMP(2);
1775 }
1776
1777 static u32 FASTCALL OP_CMP_ASR_IMM(armcpu_t *cpu)
1778 {
1779 u32 i = cpu->instruction;
1780 u32 shift_op;
1781 ASR_IMM;
1782 OP_CMP(1);
1783 }
1784
1785 static u32 FASTCALL OP_CMP_ASR_REG(armcpu_t *cpu)
1786 {
1787 u32 i = cpu->instruction;
1788 ASR_REG;
1789 OP_CMP(2);
1790 }
1791
1792 static u32 FASTCALL OP_CMP_ROR_IMM(armcpu_t *cpu)
1793 {
1794 u32 i = cpu->instruction;
1795 u32 shift_op;
1796 ROR_IMM;
1797 OP_CMP(1);
1798 }
1799
1800 static u32 FASTCALL OP_CMP_ROR_REG(armcpu_t *cpu)
1801 {
1802 u32 i = cpu->instruction;
1803 ROR_REG;
1804 OP_CMP(2);
1805 }
1806
1807 static u32 FASTCALL OP_CMP_IMM_VAL(armcpu_t *cpu)
1808 {
1809 u32 i = cpu->instruction;
1810 IMM_VALUE;
1811 OP_CMP(1);
1812 }
1813
1814 //---------------CMN---------------------------
1815
1816 #define OP_CMN(a) \
1817 { \
1818 u32 tmp = cpu->R[REG_POS(i,16)] + shift_op;\
1819 cpu->CPSR.bits.N = BIT31(tmp);\
1820 cpu->CPSR.bits.Z = (tmp==0);\
1821 cpu->CPSR.bits.C = UNSIGNED_OVERFLOW(cpu->R[REG_POS(i,16)], shift_op, tmp);\
1822 cpu->CPSR.bits.V = SIGNED_OVERFLOW(cpu->R[REG_POS(i,16)], shift_op, tmp);\
1823 return a; \
1824 }
1825
1826 static u32 FASTCALL OP_CMN_LSL_IMM(armcpu_t *cpu)
1827 {
1828 u32 i = cpu->instruction;
1829 u32 shift_op;
1830 LSL_IMM;
1831 OP_CMN(1);
1832 }
1833
1834 static u32 FASTCALL OP_CMN_LSL_REG(armcpu_t *cpu)
1835 {
1836 u32 i = cpu->instruction;
1837 LSL_REG;
1838 OP_CMN(2);
1839 }
1840
1841 static u32 FASTCALL OP_CMN_LSR_IMM(armcpu_t *cpu)
1842 {
1843 u32 i = cpu->instruction;
1844 u32 shift_op;
1845 LSR_IMM;
1846 OP_CMN(1);
1847 }
1848
1849 static u32 FASTCALL OP_CMN_LSR_REG(armcpu_t *cpu)
1850 {
1851 u32 i = cpu->instruction;
1852 LSR_REG;
1853 OP_CMN(2);
1854 }
1855
1856 static u32 FASTCALL OP_CMN_ASR_IMM(armcpu_t *cpu)
1857 {
1858 u32 i = cpu->instruction;
1859 u32 shift_op;
1860 ASR_IMM;
1861 OP_CMN(1);
1862 }
1863
1864 static u32 FASTCALL OP_CMN_ASR_REG(armcpu_t *cpu)
1865 {
1866 u32 i = cpu->instruction;
1867 ASR_REG;
1868 OP_CMN(2);
1869 }
1870
1871 static u32 FASTCALL OP_CMN_ROR_IMM(armcpu_t *cpu)
1872 {
1873 u32 i = cpu->instruction;
1874 u32 shift_op;
1875 ROR_IMM;
1876 OP_CMN(1);
1877 }
1878
1879 static u32 FASTCALL OP_CMN_ROR_REG(armcpu_t *cpu)
1880 {
1881 u32 i = cpu->instruction;
1882 ROR_REG;
1883 OP_CMN(2);
1884 }
1885
1886 static u32 FASTCALL OP_CMN_IMM_VAL(armcpu_t *cpu)
1887 {
1888 u32 i = cpu->instruction;
1889 IMM_VALUE;
1890 OP_CMN(1);
1891 }
1892
1893 //------------------ORR-------------------
1894
1895 #define OP_ORR(a, b) cpu->R[REG_POS(i,12)] = cpu->R[REG_POS(i,16)] | shift_op;\
1896 if(REG_POS(i,12)==15)\
1897 {\
1898 cpu->next_instruction = cpu->R[15];\
1899 return b;\
1900 }\
1901 return a;
1902
1903 static u32 FASTCALL OP_ORR_LSL_IMM(armcpu_t *cpu)
1904 {
1905 u32 i = cpu->instruction;
1906 u32 shift_op;
1907 LSL_IMM;
1908 OP_ORR(1, 3);
1909 }
1910
1911 static u32 FASTCALL OP_ORR_LSL_REG(armcpu_t *cpu)
1912 {
1913 u32 i = cpu->instruction;
1914 LSL_REG;
1915 OP_ORR(2, 4);
1916 }
1917
1918 static u32 FASTCALL OP_ORR_LSR_IMM(armcpu_t *cpu)
1919 {
1920 u32 i = cpu->instruction;
1921 u32 shift_op;
1922 LSR_IMM;
1923 OP_ORR(1, 3);
1924 }
1925
1926 static u32 FASTCALL OP_ORR_LSR_REG(armcpu_t *cpu)
1927 {
1928 u32 i = cpu->instruction;
1929 LSR_REG;
1930 OP_ORR(2, 4);
1931 }
1932
1933 static u32 FASTCALL OP_ORR_ASR_IMM(armcpu_t *cpu)
1934 {
1935 u32 i = cpu->instruction;
1936 u32 shift_op;
1937 ASR_IMM;
1938 OP_ORR(1, 3);
1939 }
1940
1941 static u32 FASTCALL OP_ORR_ASR_REG(armcpu_t *cpu)
1942 {
1943 u32 i = cpu->instruction;
1944 ASR_REG;
1945 OP_ORR(2, 4);
1946 }
1947
1948 static u32 FASTCALL OP_ORR_ROR_IMM(armcpu_t *cpu)
1949 {
1950 u32 i = cpu->instruction;
1951 u32 shift_op;
1952 ROR_IMM;
1953 OP_ORR(1, 3);
1954 }
1955
1956 static u32 FASTCALL OP_ORR_ROR_REG(armcpu_t *cpu)
1957 {
1958 u32 i = cpu->instruction;
1959 ROR_REG;
1960 OP_ORR(2, 4);
1961 }
1962
1963 static u32 FASTCALL OP_ORR_IMM_VAL(armcpu_t *cpu)
1964 {
1965 u32 i = cpu->instruction;
1966 IMM_VALUE;
1967 OP_ORR(1, 3);
1968 }
1969
1970 static u32 FASTCALL OP_ORR_S_LSL_IMM(armcpu_t *cpu)
1971 {
1972 u32 i = cpu->instruction;
1973 S_LSL_IMM;
1974 cpu->R[REG_POS(i,12)] = cpu->R[REG_POS(i,16)] | shift_op;
1975 if(REG_POS(i,12)==15)
1976 {
1977 Status_Reg SPSR = cpu->SPSR;
1978 armcpu_switchMode(cpu, SPSR.bits.mode);
1979 cpu->CPSR=SPSR;
1980 cpu->R[15] &= (0XFFFFFFFC|(((u32)SPSR.bits.T)<<1));
1981 cpu->next_instruction = cpu->R[15];
1982 return 4;
1983 }
1984 cpu->CPSR.bits.C = c;
1985 cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,12)]);
1986 cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0);
1987 return 2;
1988 }
1989
1990 static u32 FASTCALL OP_ORR_S_LSL_REG(armcpu_t *cpu)
1991 {
1992 u32 i = cpu->instruction;
1993 S_LSL_REG;
1994 cpu->R[REG_POS(i,12)] = cpu->R[REG_POS(i,16)] | shift_op;
1995 if(REG_POS(i,12)==15)
1996 {
1997 Status_Reg SPSR = cpu->SPSR;
1998 armcpu_switchMode(cpu, SPSR.bits.mode);
1999 cpu->CPSR=SPSR;
2000 cpu->R[15] &= (0XFFFFFFFC|(((u32)SPSR.bits.T)<<1));
2001 cpu->next_instruction = cpu->R[15];
2002 return 5;
2003 }
2004 cpu->CPSR.bits.C = c;
2005 cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,12)]);
2006 cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0);
2007 return 3;
2008 }
2009
2010 static u32 FASTCALL OP_ORR_S_LSR_IMM(armcpu_t *cpu)
2011 {
2012 u32 i = cpu->instruction;
2013 S_LSR_IMM;
2014 cpu->R[REG_POS(i,12)] = cpu->R[REG_POS(i,16)] | shift_op;
2015 if(REG_POS(i,12)==15)
2016 {
2017 Status_Reg SPSR = cpu->SPSR;
2018 armcpu_switchMode(cpu, SPSR.bits.mode);
2019 cpu->CPSR=SPSR;
2020 cpu->R[15] &= (0XFFFFFFFC|(((u32)SPSR.bits.T)<<1));
2021 cpu->next_instruction = cpu->R[15];
2022 return 4;
2023 }
2024 cpu->CPSR.bits.C = c;
2025 cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,12)]);
2026 cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0);
2027 return 2;
2028 }
2029
2030 static u32 FASTCALL OP_ORR_S_LSR_REG(armcpu_t *cpu)
2031 {
2032 u32 i = cpu->instruction;
2033 S_LSR_REG;
2034 cpu->R[REG_POS(i,12)] = cpu->R[REG_POS(i,16)] | shift_op;
2035 if(REG_POS(i,12)==15)
2036 {
2037 Status_Reg SPSR = cpu->SPSR;
2038 armcpu_switchMode(cpu, SPSR.bits.mode);
2039 cpu->CPSR=SPSR;
2040 cpu->R[15] &= (0XFFFFFFFC|(((u32)SPSR.bits.T)<<1));
2041 cpu->next_instruction = cpu->R[15];
2042 return 5;
2043 }
2044 cpu->CPSR.bits.C = c;
2045 cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,12)]);
2046 cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0);
2047 return 3;
2048 }
2049
2050 static u32 FASTCALL OP_ORR_S_ASR_IMM(armcpu_t *cpu)
2051 {
2052 u32 i = cpu->instruction;
2053 S_ASR_IMM;
2054 cpu->R[REG_POS(i,12)] = cpu->R[REG_POS(i,16)] | shift_op;
2055 if(REG_POS(i,12)==15)
2056 {
2057 Status_Reg SPSR = cpu->SPSR;
2058 armcpu_switchMode(cpu, SPSR.bits.mode);
2059 cpu->CPSR=SPSR;
2060 cpu->R[15] &= (0XFFFFFFFC|(((u32)SPSR.bits.T)<<1));
2061 cpu->next_instruction = cpu->R[15];
2062 return 4;
2063 }
2064 cpu->CPSR.bits.C = c;
2065 cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,12)]);
2066 cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0);
2067 return 2;
2068 }
2069
2070 static u32 FASTCALL OP_ORR_S_ASR_REG(armcpu_t *cpu)
2071 {
2072 u32 i = cpu->instruction;
2073 S_ASR_REG;
2074 cpu->R[REG_POS(i,12)] = cpu->R[REG_POS(i,16)] | shift_op;
2075 if(REG_POS(i,12)==15)
2076 {
2077 Status_Reg SPSR = cpu->SPSR;
2078 armcpu_switchMode(cpu, SPSR.bits.mode);
2079 cpu->CPSR=SPSR;
2080 cpu->R[15] &= (0XFFFFFFFC|(((u32)SPSR.bits.T)<<1));
2081 cpu->next_instruction = cpu->R[15];
2082 return 5;
2083 }
2084 cpu->CPSR.bits.C = c;
2085 cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,12)]);
2086 cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0);
2087 return 3;
2088 }
2089
2090 static u32 FASTCALL OP_ORR_S_ROR_IMM(armcpu_t *cpu)
2091 {
2092 u32 i = cpu->instruction;
2093 S_ROR_IMM;
2094 cpu->R[REG_POS(i,12)] = cpu->R[REG_POS(i,16)] | shift_op;
2095 if(REG_POS(i,12)==15)
2096 {
2097 Status_Reg SPSR = cpu->SPSR;
2098 armcpu_switchMode(cpu, SPSR.bits.mode);
2099 cpu->CPSR=SPSR;
2100 cpu->R[15] &= (0XFFFFFFFC|(((u32)SPSR.bits.T)<<1));
2101 cpu->next_instruction = cpu->R[15];
2102 return 4;
2103 }
2104 cpu->CPSR.bits.C = c;
2105 cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,12)]);
2106 cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0);
2107 return 2;
2108 }
2109
2110 static u32 FASTCALL OP_ORR_S_ROR_REG(armcpu_t *cpu)
2111 {
2112 u32 i = cpu->instruction;
2113 S_ROR_REG;
2114 cpu->R[REG_POS(i,12)] = cpu->R[REG_POS(i,16)] | shift_op;
2115 if(REG_POS(i,12)==15)
2116 {
2117 Status_Reg SPSR = cpu->SPSR;
2118 armcpu_switchMode(cpu, SPSR.bits.mode);
2119 cpu->CPSR=SPSR;
2120 cpu->R[15] &= (0XFFFFFFFC|(((u32)SPSR.bits.T)<<1));
2121 cpu->next_instruction = cpu->R[15];
2122 return 5;
2123 }
2124 cpu->CPSR.bits.C = c;
2125 cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,12)]);
2126 cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0);
2127 return 3;
2128 }
2129
2130 static u32 FASTCALL OP_ORR_S_IMM_VAL(armcpu_t *cpu)
2131 {
2132 u32 i = cpu->instruction;
2133 S_IMM_VALUE;
2134 cpu->R[REG_POS(i,12)] = cpu->R[REG_POS(i,16)] | shift_op;
2135 if(REG_POS(i,12)==15)
2136 {
2137 Status_Reg SPSR = cpu->SPSR;
2138 armcpu_switchMode(cpu, SPSR.bits.mode);
2139 cpu->CPSR=SPSR;
2140 cpu->R[15] &= (0XFFFFFFFC|(((u32)SPSR.bits.T)<<1));
2141 cpu->next_instruction = cpu->R[15];
2142 return 4;
2143 }
2144 cpu->CPSR.bits.C = c;
2145 cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,12)]);
2146 cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0);
2147 return 2;
2148 }
2149
2150 //------------------MOV-------------------
2151
2152 #define OP_MOV(a, b) cpu->R[REG_POS(i,12)] = shift_op;\
2153 if(REG_POS(i,12)==15)\
2154 {\
2155 cpu->next_instruction = shift_op;\
2156 return b;\
2157 }\
2158 return a;
2159
2160 #define OP_MOV_S(a, b) cpu->R[REG_POS(i,12)] = shift_op;\
2161 if(BIT20(i) && REG_POS(i,12)==15)\
2162 {\
2163 Status_Reg SPSR = cpu->SPSR;\
2164 armcpu_switchMode(cpu, SPSR.bits.mode);\
2165 cpu->CPSR=SPSR;\
2166 cpu->R[15] &= (0XFFFFFFFC|(((u32)SPSR.bits.T)<<1));\
2167 cpu->next_instruction = cpu->R[15];\
2168 return b;\
2169 }\
2170 cpu->CPSR.bits.C = c;\
2171 cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,12)]);\
2172 cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0);\
2173 return a;\
2174
2175 static u32 FASTCALL OP_MOV_LSL_IMM(armcpu_t *cpu)
2176 {
2177 u32 i = cpu->instruction;
2178 u32 shift_op;
2179 LSL_IMM;
2180 OP_MOV(1,3);
2181 }
2182
2183 static u32 FASTCALL OP_MOV_LSL_REG(armcpu_t *cpu)
2184 {
2185 u32 i = cpu->instruction;
2186 LSL_REG;
2187 if (REG_POS(i,0) == 15) shift_op += 4;
2188 OP_MOV(2,4);
2189 }
2190
2191 static u32 FASTCALL OP_MOV_LSR_IMM(armcpu_t *cpu)
2192 {
2193 u32 i = cpu->instruction;
2194 u32 shift_op;
2195 LSR_IMM;
2196 OP_MOV(1,3);
2197 }
2198
2199 static u32 FASTCALL OP_MOV_LSR_REG(armcpu_t *cpu)
2200 {
2201 u32 i = cpu->instruction;
2202 LSR_REG;
2203 if (REG_POS(i,0) == 15) shift_op += 4;
2204 OP_MOV(2,4);
2205 }
2206
2207 static u32 FASTCALL OP_MOV_ASR_IMM(armcpu_t *cpu)
2208 {
2209 u32 i = cpu->instruction;
2210 u32 shift_op;
2211 ASR_IMM;
2212 OP_MOV(1,3);
2213 }
2214
2215 static u32 FASTCALL OP_MOV_ASR_REG(armcpu_t *cpu)
2216 {
2217 u32 i = cpu->instruction;
2218 ASR_REG;
2219 OP_MOV(2,4);
2220 }
2221
2222 static u32 FASTCALL OP_MOV_ROR_IMM(armcpu_t *cpu)
2223 {
2224 u32 i = cpu->instruction;
2225 u32 shift_op;
2226 ROR_IMM;
2227 OP_MOV(2,4);
2228 }
2229
2230 static u32 FASTCALL OP_MOV_ROR_REG(armcpu_t *cpu)
2231 {
2232 u32 i = cpu->instruction;
2233 ROR_REG;
2234 OP_MOV(2,4);
2235 }
2236
2237 static u32 FASTCALL OP_MOV_IMM_VAL(armcpu_t *cpu)
2238 {
2239 u32 i = cpu->instruction;
2240 IMM_VALUE;
2241 OP_MOV(1,3);
2242 }
2243
2244 static u32 FASTCALL OP_MOV_S_LSL_IMM(armcpu_t *cpu)
2245 {
2246 u32 i = cpu->instruction;
2247 S_LSL_IMM;
2248 OP_MOV_S(2,4);
2249 }
2250
2251 static u32 FASTCALL OP_MOV_S_LSL_REG(armcpu_t *cpu)
2252 {
2253 u32 i = cpu->instruction;
2254 S_LSL_REG;
2255 if (REG_POS(i,0) == 15) shift_op += 4;
2256 OP_MOV_S(3,5);
2257 }
2258
2259 static u32 FASTCALL OP_MOV_S_LSR_IMM(armcpu_t *cpu)
2260 {
2261 u32 i = cpu->instruction;
2262 S_LSR_IMM;
2263 OP_MOV_S(2,4);
2264 }
2265
2266 static u32 FASTCALL OP_MOV_S_LSR_REG(armcpu_t *cpu)
2267 {
2268 u32 i = cpu->instruction;
2269 S_LSR_REG;
2270 if (REG_POS(i,0) == 15) shift_op += 4;
2271 OP_MOV_S(3,5);
2272 }
2273
2274 static u32 FASTCALL OP_MOV_S_ASR_IMM(armcpu_t *cpu)
2275 {
2276 u32 i = cpu->instruction;
2277 S_ASR_IMM;
2278 OP_MOV_S(2,4);
2279 }
2280
2281 static u32 FASTCALL OP_MOV_S_ASR_REG(armcpu_t *cpu)
2282 {
2283 u32 i = cpu->instruction;
2284 S_ASR_REG;
2285 OP_MOV_S(3,5);
2286 }
2287
2288 static u32 FASTCALL OP_MOV_S_ROR_IMM(armcpu_t *cpu)
2289 {
2290 u32 i = cpu->instruction;
2291 S_ROR_IMM;
2292 OP_MOV_S(2,4);
2293 }
2294
2295 static u32 FASTCALL OP_MOV_S_ROR_REG(armcpu_t *cpu)
2296 {
2297 u32 i = cpu->instruction;
2298 S_ROR_REG;
2299 OP_MOV_S(3,5);
2300 }
2301
2302 static u32 FASTCALL OP_MOV_S_IMM_VAL(armcpu_t *cpu)
2303 {
2304 u32 i = cpu->instruction;
2305 S_IMM_VALUE;
2306 OP_MOV_S(2,4);
2307 }
2308
2309 //------------------BIC-------------------
2310 #define OPP_BIC(a, b) cpu->R[REG_POS(i,12)] = cpu->R[REG_POS(i,16)] & (~shift_op);\
2311 if(REG_POS(i,12)==15)\
2312 {\
2313 cpu->next_instruction = cpu->R[15];\
2314 return b;\
2315 }\
2316 return a;
2317
2318 #define OPP_BIC_S(a, b) cpu->R[REG_POS(i,12)] = cpu->R[REG_POS(i,16)] & (~shift_op);\
2319 if(REG_POS(i,12)==15)\
2320 {\
2321 Status_Reg SPSR = cpu->SPSR;\
2322 armcpu_switchMode(cpu, SPSR.bits.mode);\
2323 cpu->CPSR=SPSR;\
2324 cpu->R[15] &= (0XFFFFFFFC|(((u32)SPSR.bits.T)<<1));\
2325 cpu->next_instruction = cpu->R[15];\
2326 return b;\
2327 }\
2328 cpu->CPSR.bits.C = c;\
2329 cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,12)]);\
2330 cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0);\
2331 return a;
2332
2333 static u32 FASTCALL OP_BIC_LSL_IMM(armcpu_t *cpu)
2334 {
2335 u32 i = cpu->instruction;
2336 u32 shift_op;
2337 LSL_IMM;
2338 OPP_BIC(1,3);
2339 }
2340
2341 static u32 FASTCALL OP_BIC_LSL_REG(armcpu_t *cpu)
2342 {
2343 u32 i = cpu->instruction;
2344 LSL_REG;
2345 OPP_BIC(2,4);
2346 }
2347
2348 static u32 FASTCALL OP_BIC_LSR_IMM(armcpu_t *cpu)
2349 {
2350 u32 i = cpu->instruction;
2351 u32 shift_op;
2352 LSR_IMM;
2353 OPP_BIC(1,3);
2354 }
2355
2356 static u32 FASTCALL OP_BIC_LSR_REG(armcpu_t *cpu)
2357 {
2358 u32 i = cpu->instruction;
2359 LSR_REG;
2360 OPP_BIC(2,4);
2361 }
2362
2363 static u32 FASTCALL OP_BIC_ASR_IMM(armcpu_t *cpu)
2364 {
2365 u32 i = cpu->instruction;
2366 u32 shift_op;
2367 ASR_IMM;
2368 OPP_BIC(1,3);
2369 }
2370
2371 static u32 FASTCALL OP_BIC_ASR_REG(armcpu_t *cpu)
2372 {
2373 u32 i = cpu->instruction;
2374 ASR_REG;
2375 OPP_BIC(2,4);
2376 }
2377
2378 static u32 FASTCALL OP_BIC_ROR_IMM(armcpu_t *cpu)
2379 {
2380 u32 i = cpu->instruction;
2381 u32 shift_op;
2382 ROR_IMM;
2383 OPP_BIC(1,3);
2384 }
2385
2386 static u32 FASTCALL OP_BIC_ROR_REG(armcpu_t *cpu)
2387 {
2388 u32 i = cpu->instruction;
2389 ROR_REG;
2390 OPP_BIC(2,4);
2391 }
2392
2393 static u32 FASTCALL OP_BIC_IMM_VAL(armcpu_t *cpu)
2394 {
2395 u32 i = cpu->instruction;
2396 IMM_VALUE;
2397 OPP_BIC(1,3);
2398 }
2399
2400 static u32 FASTCALL OP_BIC_S_LSL_IMM(armcpu_t *cpu)
2401 {
2402 u32 i = cpu->instruction;
2403 S_LSL_IMM;
2404 OPP_BIC_S(2,4);
2405 }
2406
2407 static u32 FASTCALL OP_BIC_S_LSL_REG(armcpu_t *cpu)
2408 {
2409 u32 i = cpu->instruction;
2410 S_LSL_REG;
2411 OPP_BIC_S(3,5);
2412 }
2413
2414 static u32 FASTCALL OP_BIC_S_LSR_IMM(armcpu_t *cpu)
2415 {
2416 u32 i = cpu->instruction;
2417 S_LSR_IMM;
2418 OPP_BIC_S(2,4);
2419 }
2420
2421 static u32 FASTCALL OP_BIC_S_LSR_REG(armcpu_t *cpu)
2422 {
2423 u32 i = cpu->instruction;
2424 S_LSR_REG;
2425 OPP_BIC_S(3,5);
2426 }
2427
2428 static u32 FASTCALL OP_BIC_S_ASR_IMM(armcpu_t *cpu)
2429 {
2430 u32 i = cpu->instruction;
2431 S_ASR_IMM;
2432 OPP_BIC_S(2,4);
2433 }
2434
2435 static u32 FASTCALL OP_BIC_S_ASR_REG(armcpu_t *cpu)
2436 {
2437 u32 i = cpu->instruction;
2438 S_ASR_REG;
2439 OPP_BIC_S(3,5);
2440 }
2441
2442 static u32 FASTCALL OP_BIC_S_ROR_IMM(armcpu_t *cpu)
2443 {
2444 u32 i = cpu->instruction;
2445 S_ROR_IMM;
2446 OPP_BIC_S(2,4);
2447 }
2448
2449 static u32 FASTCALL OP_BIC_S_ROR_REG(armcpu_t *cpu)
2450 {
2451 u32 i = cpu->instruction;
2452 S_ROR_REG;
2453 OPP_BIC_S(3,5);
2454 }
2455
2456 static u32 FASTCALL OP_BIC_S_IMM_VAL(armcpu_t *cpu)
2457 {
2458 u32 i = cpu->instruction;
2459 S_IMM_VALUE;
2460 OPP_BIC_S(2,4);
2461 }
2462
2463 //------------------MVN-------------------
2464 #define OPP_MVN(a, b) cpu->R[REG_POS(i,12)] = ~shift_op;\
2465 if(REG_POS(i,12)==15)\
2466 {\
2467 cpu->next_instruction = cpu->R[15];\
2468 return b;\
2469 }\
2470 return a;
2471
2472 #define OPP_MVN_S(a, b) cpu->R[REG_POS(i,12)] = ~shift_op;\
2473 if(REG_POS(i,12)==15)\
2474 {\
2475 Status_Reg SPSR = cpu->SPSR;\
2476 armcpu_switchMode(cpu, SPSR.bits.mode);\
2477 cpu->CPSR=SPSR;\
2478 cpu->R[15] &= (0XFFFFFFFC|(((u32)SPSR.bits.T)<<1));\
2479 cpu->next_instruction = cpu->R[15];\
2480 return b;\
2481 }\
2482 cpu->CPSR.bits.C = c;\
2483 cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,12)]);\
2484 cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0);\
2485 return a;
2486
2487 static u32 FASTCALL OP_MVN_LSL_IMM(armcpu_t *cpu)
2488 {
2489 u32 i = cpu->instruction;
2490 u32 shift_op;
2491 LSL_IMM;
2492 OPP_MVN(1,3);
2493 }
2494
2495 static u32 FASTCALL OP_MVN_LSL_REG(armcpu_t *cpu)
2496 {
2497 u32 i = cpu->instruction;
2498 LSL_REG;
2499 OPP_MVN(2,4);
2500 }
2501
2502 static u32 FASTCALL OP_MVN_LSR_IMM(armcpu_t *cpu)
2503 {
2504 u32 i = cpu->instruction;
2505 u32 shift_op;
2506 LSR_IMM;
2507 OPP_MVN(1,3);
2508 }
2509
2510 static u32 FASTCALL OP_MVN_LSR_REG(armcpu_t *cpu)
2511 {
2512 u32 i = cpu->instruction;
2513 LSR_REG;
2514 OPP_MVN(2,4);
2515 }
2516
2517 static u32 FASTCALL OP_MVN_ASR_IMM(armcpu_t *cpu)
2518 {
2519 u32 i = cpu->instruction;
2520 u32 shift_op;
2521 ASR_IMM;
2522 OPP_MVN(1,3);
2523 }
2524
2525 static u32 FASTCALL OP_MVN_ASR_REG(armcpu_t *cpu)
2526 {
2527 u32 i = cpu->instruction;
2528 ASR_REG;
2529 OPP_MVN(2,4);
2530 }
2531
2532 static u32 FASTCALL OP_MVN_ROR_IMM(armcpu_t *cpu)
2533 {
2534 u32 i = cpu->instruction;
2535 u32 shift_op;
2536 ROR_IMM;
2537 OPP_MVN(1,3);
2538 }
2539
2540 static u32 FASTCALL OP_MVN_ROR_REG(armcpu_t *cpu)
2541 {
2542 u32 i = cpu->instruction;
2543 ROR_REG;
2544 OPP_MVN(2,4);
2545 }
2546
2547 static u32 FASTCALL OP_MVN_IMM_VAL(armcpu_t *cpu)
2548 {
2549 u32 i = cpu->instruction;
2550 IMM_VALUE;
2551 OPP_MVN(1,3);
2552 }
2553
2554 static u32 FASTCALL OP_MVN_S_LSL_IMM(armcpu_t *cpu)
2555 {
2556 u32 i = cpu->instruction;
2557 S_LSL_IMM;
2558 OPP_MVN_S(2,4);
2559 }
2560
2561 static u32 FASTCALL OP_MVN_S_LSL_REG(armcpu_t *cpu)
2562 {
2563 u32 i = cpu->instruction;
2564 S_LSL_REG;
2565 OPP_MVN_S(3,5);
2566 }
2567
2568 static u32 FASTCALL OP_MVN_S_LSR_IMM(armcpu_t *cpu)
2569 {
2570 u32 i = cpu->instruction;
2571 S_LSR_IMM;
2572 OPP_MVN_S(2,4);
2573 }
2574
2575 static u32 FASTCALL OP_MVN_S_LSR_REG(armcpu_t *cpu)
2576 {
2577 u32 i = cpu->instruction;
2578 S_LSR_REG;
2579 OPP_MVN_S(3,5);
2580 }
2581
2582 static u32 FASTCALL OP_MVN_S_ASR_IMM(armcpu_t *cpu)
2583 {
2584 u32 i = cpu->instruction;
2585 S_ASR_IMM;
2586 OPP_MVN_S(2,4);
2587 }
2588
2589 static u32 FASTCALL OP_MVN_S_ASR_REG(armcpu_t *cpu)
2590 {
2591 u32 i = cpu->instruction;
2592 S_ASR_REG;
2593 OPP_MVN_S(3,5);
2594 }
2595
2596 static u32 FASTCALL OP_MVN_S_ROR_IMM(armcpu_t *cpu)
2597 {
2598 u32 i = cpu->instruction;
2599 S_ROR_IMM;
2600 OPP_MVN_S(2,4);
2601 }
2602
2603 static u32 FASTCALL OP_MVN_S_ROR_REG(armcpu_t *cpu)
2604 {
2605 u32 i = cpu->instruction;
2606 S_ROR_REG;
2607 OPP_MVN_S(3,5);
2608 }
2609
2610 static u32 FASTCALL OP_MVN_S_IMM_VAL(armcpu_t *cpu)
2611 {
2612 u32 i = cpu->instruction;
2613 S_IMM_VALUE;
2614 OPP_MVN_S(2,4);
2615 }
2616
2617 //-------------MUL------------------------
2618 #define OPP_M(a,b) v >>= 8;\
2619 if((v==0)||(v==0xFFFFFF))\
2620 return b;\
2621 v >>= 8;\
2622 if((v==0)||(v==0xFFFF))\
2623 return b+1;\
2624 v >>= 8;\
2625 if((v==0)||(v==0xFF))\
2626 return b+2;\
2627 return a;\
2628
2629 static u32 FASTCALL OP_MUL(armcpu_t *cpu)
2630 {
2631 u32 i = cpu->instruction;
2632 u32 v = cpu->R[REG_POS(i,0)];
2633 cpu->R[REG_POS(i,16)] = cpu->R[REG_POS(i,8)] * v;
2634 OPP_M(5,2);
2635 }
2636
2637 static u32 FASTCALL OP_MLA(armcpu_t *cpu)
2638 {
2639 u32 i = cpu->instruction;
2640 u32 v = cpu->R[REG_POS(i,0)];
2641 u32 a = cpu->R[REG_POS(i,8)];
2642 u32 b = cpu->R[REG_POS(i,12)];
2643 cpu->R[REG_POS(i,16)] = a * v + b;
2644
2645 OPP_M(6,3);
2646 }
2647
2648 static u32 FASTCALL OP_MUL_S(armcpu_t *cpu)
2649 {
2650 u32 i = cpu->instruction;
2651 u32 v = cpu->R[REG_POS(i,0)];
2652 cpu->R[REG_POS(i,16)] = cpu->R[REG_POS(i,8)] * v;
2653
2654 cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,16)]);
2655 cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,16)]==0);
2656
2657 OPP_M(6,3);
2658 }
2659
2660 static u32 FASTCALL OP_MLA_S(armcpu_t *cpu)
2661 {
2662 u32 i = cpu->instruction;
2663 u32 v = cpu->R[REG_POS(i,0)];
2664 cpu->R[REG_POS(i,16)] = cpu->R[REG_POS(i,8)] * v + cpu->R[REG_POS(i,12)];
2665 cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,16)]);
2666 cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,16)]==0);
2667 OPP_M(7,4);
2668 }
2669
2670 //----------UMUL--------------------------
2671
2672 static u32 FASTCALL OP_UMULL(armcpu_t *cpu)
2673 {
2674 u32 i = cpu->instruction;
2675 u32 v = cpu->R[REG_POS(i,0)];
2676 u64 res = (u64)v * (u64)cpu->R[REG_POS(i,8)];
2677
2678 cpu->R[REG_POS(i,12)] = (u32)res;
2679 cpu->R[REG_POS(i,16)] = (u32)(res>>32);
2680
2681 OPP_M(6,3);
2682 }
2683
2684 static u32 FASTCALL OP_UMLAL(armcpu_t *cpu)
2685 {
2686 u32 i = cpu->instruction;
2687 u32 v = cpu->R[REG_POS(i,0)];
2688 u64 res = (u64)v * (u64)cpu->R[REG_POS(i,8)] + (u64)cpu->R[REG_POS(i,12)];
2689
2690 cpu->R[REG_POS(i,12)] = (u32)res;
2691 cpu->R[REG_POS(i,16)] += (u32)(res>>32);
2692
2693 OPP_M(7,4);
2694 }
2695
2696 static u32 FASTCALL OP_UMULL_S(armcpu_t *cpu)
2697 {
2698 u32 i = cpu->instruction;
2699 u32 v = cpu->R[REG_POS(i,0)];
2700 u64 res = (u64)v * (u64)cpu->R[REG_POS(i,8)];
2701
2702 cpu->R[REG_POS(i,12)] = (u32)res;
2703 cpu->R[REG_POS(i,16)] = (u32)(res>>32);
2704
2705 cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,16)]);
2706 cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,16)]==0) & (cpu->R[REG_POS(i,12)]==0);
2707
2708 OPP_M(7,4);
2709 }
2710
2711 static u32 FASTCALL OP_UMLAL_S(armcpu_t *cpu)
2712 {
2713 u32 i = cpu->instruction;
2714 u32 v = cpu->R[REG_POS(i,0)];
2715 u64 res = (u64)v * (u64)cpu->R[REG_POS(i,8)] + (u64)cpu->R[REG_POS(i,12)];
2716
2717 cpu->R[REG_POS(i,12)] = (u32)res;
2718 cpu->R[REG_POS(i,16)] += (u32)(res>>32);
2719
2720 cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,16)]);
2721 cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,16)]==0) & (cpu->R[REG_POS(i,12)]==0);
2722
2723 OPP_M(8,5);
2724 }
2725
2726 //----------SMUL--------------------------
2727
2728 static u32 FASTCALL OP_SMULL(armcpu_t *cpu)
2729 {
2730 u32 i = cpu->instruction;
2731 s64 v = (s32)cpu->R[REG_POS(i,0)];
2732 s64 b = (s32)cpu->R[REG_POS(i,8)];
2733 s64 res = v * b;
2734
2735 cpu->R[REG_POS(i,12)] = (u32)(res&0xFFFFFFFF);
2736 cpu->R[REG_POS(i,16)] = (u32)(res>>32);
2737
2738 v &= 0xFFFFFFFF;
2739
2740 OPP_M(6,3);
2741 }
2742
2743 static u32 FASTCALL OP_SMLAL(armcpu_t *cpu)
2744 {
2745 u32 i = cpu->instruction;
2746
2747 s64 v = (s32)cpu->R[REG_POS(i,0)];
2748 s64 b = (s32)cpu->R[REG_POS(i,8)];
2749 s64 res = v * b + (u64)cpu->R[REG_POS(i,12)];
2750
2751 //LOG("%08X * %08X + %08X%08X\r\n", cpu->R[REG_POS(i,0)], cpu->R[REG_POS(i,8)], cpu->R[REG_POS(i,16)], cpu->R[REG_POS(i,12)]);
2752
2753 cpu->R[REG_POS(i,12)] = (u32)res;
2754 cpu->R[REG_POS(i,16)] += (u32)(res>>32);
2755
2756 //LOG("= %08X%08X %08X%08X\r\n", cpu->R[REG_POS(i,16)], cpu->R[REG_POS(i,12)], res);
2757
2758 v &= 0xFFFFFFFF;
2759
2760 OPP_M(7,4);
2761 }
2762
2763 static u32 FASTCALL OP_SMULL_S(armcpu_t *cpu)
2764 {
2765 u32 i = cpu->instruction;
2766 s64 v = (s32)cpu->R[REG_POS(i,0)];
2767 s64 b = (s32)cpu->R[REG_POS(i,8)];
2768 s64 res = v * b;
2769
2770 cpu->R[REG_POS(i,12)] = (u32)res;
2771 cpu->R[REG_POS(i,16)] = (u32)(res>>32);
2772
2773 cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,16)]);
2774 cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,16)]==0) & (cpu->R[REG_POS(i,12)]==0);
2775
2776 v &= 0xFFFFFFFF;
2777
2778 OPP_M(7,4);
2779 }
2780
2781 static u32 FASTCALL OP_SMLAL_S(armcpu_t *cpu)
2782 {
2783 u32 i = cpu->instruction;
2784 s64 v = (s32)cpu->R[REG_POS(i,0)];
2785 s64 b = (s32)cpu->R[REG_POS(i,8)];
2786 s64 res = v * b + (u64)cpu->R[REG_POS(i,12)];
2787
2788 cpu->R[REG_POS(i,12)] = (u32)res;
2789 cpu->R[REG_POS(i,16)] += (u32)(res>>32);
2790
2791 cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,16)]);
2792 cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,16)]==0) & (cpu->R[REG_POS(i,12)]==0);
2793
2794 v &= 0xFFFFFFFF;
2795
2796 OPP_M(8,5);
2797 }
2798
2799 //---------------SWP------------------------------
2800
2801 static u32 FASTCALL OP_SWP(armcpu_t *cpu)
2802 {
2803 u32 i = cpu->instruction;
2804 u32 adr = cpu->R[REG_POS(i,16)];
2805 u32 tmp = ROR(READ32(cpu->mem_if->data, adr), ((cpu->R[REG_POS(i,16)]&3)<<3));
2806
2807 WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,0)]);
2808 cpu->R[REG_POS(i,12)] = tmp;
2809
2810 return 4 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]*2;
2811 }
2812
2813 static u32 FASTCALL OP_SWPB(armcpu_t *cpu)
2814 {
2815 u32 i = cpu->instruction;
2816 u32 adr = cpu->R[REG_POS(i,16)];
2817 u8 tmp = READ8(cpu->mem_if->data, adr);
2818 WRITE8(cpu->mem_if->data, adr, (u8)(cpu->R[REG_POS(i,0)]&0xFF));
2819 cpu->R[REG_POS(i,12)] = tmp;
2820
2821 return 4 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]*2;
2822 }
2823
2824 //------------LDRH-----------------------------
2825
2826 static u32 FASTCALL OP_LDRH_P_IMM_OFF(armcpu_t *cpu)
2827 {
2828 u32 i = cpu->instruction;
2829 u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF;
2830 cpu->R[REG_POS(i,12)] = (u32)READ16(cpu->mem_if->data, adr);
2831
2832 return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
2833 }
2834
2835 static u32 FASTCALL OP_LDRH_M_IMM_OFF(armcpu_t *cpu)
2836 {
2837 u32 i = cpu->instruction;
2838 u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF;
2839 cpu->R[REG_POS(i,12)] = (u32)READ16(cpu->mem_if->data, adr);
2840
2841 return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
2842 }
2843
2844 static u32 FASTCALL OP_LDRH_P_REG_OFF(armcpu_t *cpu)
2845 {
2846 u32 i = cpu->instruction;
2847 u32 adr = cpu->R[REG_POS(i,16)] + cpu->R[REG_POS(i,0)];
2848 cpu->R[REG_POS(i,12)] = (u32)READ16(cpu->mem_if->data, adr);
2849
2850 return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
2851 }
2852
2853 static u32 FASTCALL OP_LDRH_M_REG_OFF(armcpu_t *cpu)
2854 {
2855 u32 i = cpu->instruction;
2856 u32 adr = cpu->R[REG_POS(i,16)] - cpu->R[REG_POS(i,0)];
2857 cpu->R[REG_POS(i,12)] = (u32)READ16(cpu->mem_if->data, adr);
2858
2859 return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
2860 }
2861
2862 static u32 FASTCALL OP_LDRH_PRE_INDE_P_IMM_OFF(armcpu_t *cpu)
2863 {
2864 u32 i = cpu->instruction;
2865 u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF;
2866 cpu->R[REG_POS(i,16)] = adr;
2867 cpu->R[REG_POS(i,12)] = (u32)READ16(cpu->mem_if->data, adr);
2868
2869 return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
2870 }
2871
2872 static u32 FASTCALL OP_LDRH_PRE_INDE_M_IMM_OFF(armcpu_t *cpu)
2873 {
2874 u32 i = cpu->instruction;
2875 u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF;
2876 cpu->R[REG_POS(i,16)] = adr;
2877 cpu->R[REG_POS(i,12)] = (u32)READ16(cpu->mem_if->data, adr);
2878
2879
2880 return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
2881 }
2882
2883 static u32 FASTCALL OP_LDRH_PRE_INDE_P_REG_OFF(armcpu_t *cpu)
2884 {
2885 u32 i = cpu->instruction;
2886 u32 adr = cpu->R[REG_POS(i,16)] + cpu->R[REG_POS(i,0)];
2887 cpu->R[REG_POS(i,16)] = adr;
2888 cpu->R[REG_POS(i,12)] =(u32)READ16(cpu->mem_if->data, adr);
2889
2890 return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
2891 }
2892
2893 static u32 FASTCALL OP_LDRH_PRE_INDE_M_REG_OFF(armcpu_t *cpu)
2894 {
2895 u32 i = cpu->instruction;
2896 u32 adr = cpu->R[REG_POS(i,16)] - cpu->R[REG_POS(i,0)];
2897 cpu->R[REG_POS(i,16)] = adr;
2898 cpu->R[REG_POS(i,12)] = (u32)READ16(cpu->mem_if->data, adr);
2899
2900 return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
2901 }
2902
2903 static u32 FASTCALL OP_LDRH_POS_INDE_P_IMM_OFF(armcpu_t *cpu)
2904 {
2905 u32 i = cpu->instruction;
2906 u32 adr = cpu->R[REG_POS(i,16)];
2907 cpu->R[REG_POS(i,12)] = (u32)READ16(cpu->mem_if->data, adr);
2908 cpu->R[REG_POS(i,16)] += IMM_OFF;
2909
2910 return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
2911 }
2912
2913 static u32 FASTCALL OP_LDRH_POS_INDE_M_IMM_OFF(armcpu_t *cpu)
2914 {
2915 u32 i = cpu->instruction;
2916 u32 adr = cpu->R[REG_POS(i,16)];
2917 cpu->R[REG_POS(i,12)] = (u32)READ16(cpu->mem_if->data, adr);
2918 cpu->R[REG_POS(i,16)] -= IMM_OFF;
2919
2920 return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
2921 }
2922
2923 static u32 FASTCALL OP_LDRH_POS_INDE_P_REG_OFF(armcpu_t *cpu)
2924 {
2925 u32 i = cpu->instruction;
2926 u32 adr = cpu->R[REG_POS(i,16)];
2927 cpu->R[REG_POS(i,12)] = (u32)READ16(cpu->mem_if->data, adr);
2928 cpu->R[REG_POS(i,16)] += cpu->R[REG_POS(i,0)];
2929
2930 return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
2931 }
2932
2933 static u32 FASTCALL OP_LDRH_POS_INDE_M_REG_OFF(armcpu_t *cpu)
2934 {
2935 u32 i = cpu->instruction;
2936 u32 adr = cpu->R[REG_POS(i,16)];
2937 cpu->R[REG_POS(i,12)] = (u32)READ16(cpu->mem_if->data, adr);
2938 cpu->R[REG_POS(i,16)] -= cpu->R[REG_POS(i,0)];
2939
2940 return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
2941 }
2942
2943 //------------STRH-----------------------------
2944
2945 static u32 FASTCALL OP_STRH_P_IMM_OFF(armcpu_t *cpu)
2946 {
2947 u32 i = cpu->instruction;
2948 u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF;
2949 WRITE16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]);
2950
2951 return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
2952 }
2953
2954 static u32 FASTCALL OP_STRH_M_IMM_OFF(armcpu_t *cpu)
2955 {
2956 u32 i = cpu->instruction;
2957 u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF;
2958 WRITE16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]);
2959
2960 return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
2961 }
2962
2963 static u32 FASTCALL OP_STRH_P_REG_OFF(armcpu_t *cpu)
2964 {
2965 u32 i = cpu->instruction;
2966 u32 adr = cpu->R[REG_POS(i,16)] + cpu->R[REG_POS(i,0)];
2967 WRITE16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]);
2968
2969 return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
2970 }
2971
2972 static u32 FASTCALL OP_STRH_M_REG_OFF(armcpu_t *cpu)
2973 {
2974 u32 i = cpu->instruction;
2975 u32 adr = cpu->R[REG_POS(i,16)] - cpu->R[REG_POS(i,0)];
2976 WRITE16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]);
2977
2978 return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
2979 }
2980
2981 static u32 FASTCALL OP_STRH_PRE_INDE_P_IMM_OFF(armcpu_t *cpu)
2982 {
2983 u32 i = cpu->instruction;
2984 u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF;
2985 cpu->R[REG_POS(i,16)] = adr;
2986 WRITE16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]);
2987
2988 return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
2989 }
2990
2991 static u32 FASTCALL OP_STRH_PRE_INDE_M_IMM_OFF(armcpu_t *cpu)
2992 {
2993 u32 i = cpu->instruction;
2994 u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF;
2995 WRITE16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]);
2996 cpu->R[REG_POS(i,16)] = adr;
2997
2998 return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
2999 }
3000
3001 static u32 FASTCALL OP_STRH_PRE_INDE_P_REG_OFF(armcpu_t *cpu)
3002 {
3003 u32 i = cpu->instruction;
3004 u32 adr = cpu->R[REG_POS(i,16)] + cpu->R[REG_POS(i,0)];
3005 WRITE16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]);
3006 cpu->R[REG_POS(i,16)] = adr;
3007
3008 return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
3009 }
3010
3011 static u32 FASTCALL OP_STRH_PRE_INDE_M_REG_OFF(armcpu_t *cpu)
3012 {
3013 u32 i = cpu->instruction;
3014 u32 adr = cpu->R[REG_POS(i,16)] - cpu->R[REG_POS(i,0)];
3015 WRITE16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]);
3016 cpu->R[REG_POS(i,16)] = adr;
3017
3018 return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
3019 }
3020
3021 static u32 FASTCALL OP_STRH_POS_INDE_P_IMM_OFF(armcpu_t *cpu)
3022 {
3023 u32 i = cpu->instruction;
3024 u32 adr = cpu->R[REG_POS(i,16)];
3025 WRITE16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]);
3026 cpu->R[REG_POS(i,16)] += IMM_OFF;
3027
3028 return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
3029 }
3030
3031 static u32 FASTCALL OP_STRH_POS_INDE_M_IMM_OFF(armcpu_t *cpu)
3032 {
3033 u32 i = cpu->instruction;
3034 u32 adr = cpu->R[REG_POS(i,16)];
3035 WRITE16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]);
3036 cpu->R[REG_POS(i,16)] -= IMM_OFF;
3037
3038 return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
3039 }
3040
3041 static u32 FASTCALL OP_STRH_POS_INDE_P_REG_OFF(armcpu_t *cpu)
3042 {
3043 u32 i = cpu->instruction;
3044 u32 adr = cpu->R[REG_POS(i,16)];
3045 WRITE16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]);
3046 cpu->R[REG_POS(i,16)] += cpu->R[REG_POS(i,0)];
3047
3048 return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
3049 }
3050
3051 static u32 FASTCALL OP_STRH_POS_INDE_M_REG_OFF(armcpu_t *cpu)
3052 {
3053 u32 i = cpu->instruction;
3054 u32 adr = cpu->R[REG_POS(i,16)];
3055 WRITE16(cpu->mem_if->data, adr, (u16)cpu->R[REG_POS(i,12)]);
3056 cpu->R[REG_POS(i,16)] -= cpu->R[REG_POS(i,0)];
3057
3058 return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
3059 }
3060
3061 //----------------LDRSH--------------------------
3062
3063 static u32 FASTCALL OP_LDRSH_P_IMM_OFF(armcpu_t *cpu)
3064 {
3065 u32 i = cpu->instruction;
3066 u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF;
3067 cpu->R[REG_POS(i,12)] = (s32)((s16)READ16(cpu->mem_if->data, adr));
3068
3069 return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
3070 }
3071
3072 static u32 FASTCALL OP_LDRSH_M_IMM_OFF(armcpu_t *cpu)
3073 {
3074 u32 i = cpu->instruction;
3075 u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF;
3076 cpu->R[REG_POS(i,12)] = (s32)((s16)READ16(cpu->mem_if->data, adr));
3077
3078 return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
3079 }
3080
3081 static u32 FASTCALL OP_LDRSH_P_REG_OFF(armcpu_t *cpu)
3082 {
3083 u32 i = cpu->instruction;
3084 u32 adr = cpu->R[REG_POS(i,16)] + cpu->R[REG_POS(i,0)];
3085 cpu->R[REG_POS(i,12)] = (s32)((s16)READ16(cpu->mem_if->data, adr));
3086
3087 return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
3088 }
3089
3090 static u32 FASTCALL OP_LDRSH_M_REG_OFF(armcpu_t *cpu)
3091 {
3092 u32 i = cpu->instruction;
3093 u32 adr = cpu->R[REG_POS(i,16)] - cpu->R[REG_POS(i,0)];
3094 cpu->R[REG_POS(i,12)] = (s32)((s16)READ16(cpu->mem_if->data, adr));
3095
3096 return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
3097 }
3098
3099 static u32 FASTCALL OP_LDRSH_PRE_INDE_P_IMM_OFF(armcpu_t *cpu)
3100 {
3101 u32 i = cpu->instruction;
3102 u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF;
3103 cpu->R[REG_POS(i,12)] = (s32)((s16)READ16(cpu->mem_if->data, adr));
3104 cpu->R[REG_POS(i,16)] = adr;
3105
3106 return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
3107 }
3108
3109 static u32 FASTCALL OP_LDRSH_PRE_INDE_M_IMM_OFF(armcpu_t *cpu)
3110 {
3111 u32 i = cpu->instruction;
3112 u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF;
3113 cpu->R[REG_POS(i,12)] = (s32)((s16)READ16(cpu->mem_if->data, adr));
3114 cpu->R[REG_POS(i,16)] = adr;
3115
3116 return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
3117 }
3118
3119 static u32 FASTCALL OP_LDRSH_PRE_INDE_P_REG_OFF(armcpu_t *cpu)
3120 {
3121 u32 i = cpu->instruction;
3122 u32 adr = cpu->R[REG_POS(i,16)] + cpu->R[REG_POS(i,0)];
3123 cpu->R[REG_POS(i,12)] = (s32)((s16)READ16(cpu->mem_if->data, adr));
3124 cpu->R[REG_POS(i,16)] = adr;
3125
3126 return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
3127 }
3128
3129 static u32 FASTCALL OP_LDRSH_PRE_INDE_M_REG_OFF(armcpu_t *cpu)
3130 {
3131 u32 i = cpu->instruction;
3132 u32 adr = cpu->R[REG_POS(i,16)] - cpu->R[REG_POS(i,0)];
3133 cpu->R[REG_POS(i,12)] = (s32)((s16)READ16(cpu->mem_if->data, adr));
3134 cpu->R[REG_POS(i,16)] = adr;
3135
3136 return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
3137 }
3138
3139 static u32 FASTCALL OP_LDRSH_POS_INDE_P_IMM_OFF(armcpu_t *cpu)
3140 {
3141 u32 i = cpu->instruction;
3142 u32 adr = cpu->R[REG_POS(i,16)];
3143 cpu->R[REG_POS(i,12)] = (s32)((s16)READ16(cpu->mem_if->data, adr));
3144 cpu->R[REG_POS(i,16)] += IMM_OFF;
3145
3146 return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
3147 }
3148
3149 static u32 FASTCALL OP_LDRSH_POS_INDE_M_IMM_OFF(armcpu_t *cpu)
3150 {
3151 u32 i = cpu->instruction;
3152 u32 adr = cpu->R[REG_POS(i,16)];
3153 cpu->R[REG_POS(i,12)] = (s32)((s16)READ16(cpu->mem_if->data, adr));
3154 cpu->R[REG_POS(i,16)] -= IMM_OFF;
3155
3156 return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
3157 }
3158
3159 static u32 FASTCALL OP_LDRSH_POS_INDE_P_REG_OFF(armcpu_t *cpu)
3160 {
3161 u32 i = cpu->instruction;
3162 u32 adr = cpu->R[REG_POS(i,16)];
3163 cpu->R[REG_POS(i,12)] = (s32)((s16)READ16(cpu->mem_if->data, adr));
3164 cpu->R[REG_POS(i,16)] += cpu->R[REG_POS(i,0)];
3165
3166 return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
3167 }
3168
3169 static u32 FASTCALL OP_LDRSH_POS_INDE_M_REG_OFF(armcpu_t *cpu)
3170 {
3171 u32 i = cpu->instruction;
3172 u32 adr = cpu->R[REG_POS(i,16)];
3173 cpu->R[REG_POS(i,12)] = (s32)((s16)READ16(cpu->mem_if->data, adr));
3174 cpu->R[REG_POS(i,16)] -= cpu->R[REG_POS(i,0)];
3175
3176 return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
3177 }
3178
3179 //----------------------LDRSB----------------------
3180
3181 static u32 FASTCALL OP_LDRSB_P_IMM_OFF(armcpu_t *cpu)
3182 {
3183 u32 i = cpu->instruction;
3184 u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF;
3185 cpu->R[REG_POS(i,12)] = (s32)((s8)READ8(cpu->mem_if->data, adr));
3186
3187 return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
3188 }
3189
3190 static u32 FASTCALL OP_LDRSB_M_IMM_OFF(armcpu_t *cpu)
3191 {
3192 u32 i = cpu->instruction;
3193 u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF;
3194 cpu->R[REG_POS(i,12)] = (s32)((s8)READ8(cpu->mem_if->data, adr));
3195
3196 return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
3197 }
3198
3199 static u32 FASTCALL OP_LDRSB_P_REG_OFF(armcpu_t *cpu)
3200 {
3201 u32 i = cpu->instruction;
3202 u32 adr = cpu->R[REG_POS(i,16)] + cpu->R[REG_POS(i,0)];
3203 cpu->R[REG_POS(i,12)] = (s32)((s8)READ8(cpu->mem_if->data, adr));
3204
3205 return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
3206 }
3207
3208 static u32 FASTCALL OP_LDRSB_M_REG_OFF(armcpu_t *cpu)
3209 {
3210 u32 i = cpu->instruction;
3211 u32 adr = cpu->R[REG_POS(i,16)] - cpu->R[REG_POS(i,0)];
3212 cpu->R[REG_POS(i,12)] = (s32)((s8)READ8(cpu->mem_if->data, adr));
3213
3214 return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
3215 }
3216
3217 static u32 FASTCALL OP_LDRSB_PRE_INDE_P_IMM_OFF(armcpu_t *cpu)
3218 {
3219 u32 i = cpu->instruction;
3220 u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF;
3221 cpu->R[REG_POS(i,12)] = (s32)((s8)READ8(cpu->mem_if->data, adr));
3222 cpu->R[REG_POS(i,16)] = adr;
3223
3224 return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
3225 }
3226
3227 static u32 FASTCALL OP_LDRSB_PRE_INDE_M_IMM_OFF(armcpu_t *cpu)
3228 {
3229 u32 i = cpu->instruction;
3230 u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF;
3231 cpu->R[REG_POS(i,12)] = (s32)((s8)READ8(cpu->mem_if->data, adr));
3232 cpu->R[REG_POS(i,16)] = adr;
3233
3234 return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
3235 }
3236
3237 static u32 FASTCALL OP_LDRSB_PRE_INDE_P_REG_OFF(armcpu_t *cpu)
3238 {
3239 u32 i = cpu->instruction;
3240 u32 adr = cpu->R[REG_POS(i,16)] + cpu->R[REG_POS(i,0)];
3241 cpu->R[REG_POS(i,12)] = (s32)((s8)READ8(cpu->mem_if->data, adr));
3242 cpu->R[REG_POS(i,16)] = adr;
3243
3244 return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
3245 }
3246
3247 static u32 FASTCALL OP_LDRSB_PRE_INDE_M_REG_OFF(armcpu_t *cpu)
3248 {
3249 u32 i = cpu->instruction;
3250 u32 adr = cpu->R[REG_POS(i,16)] - cpu->R[REG_POS(i,0)];
3251 cpu->R[REG_POS(i,12)] = (s32)((s8)READ8(cpu->mem_if->data, adr));
3252 cpu->R[REG_POS(i,16)] = adr;
3253
3254 return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
3255 }
3256
3257 static u32 FASTCALL OP_LDRSB_POS_INDE_P_IMM_OFF(armcpu_t *cpu)
3258 {
3259 u32 i = cpu->instruction;
3260 u32 adr = cpu->R[REG_POS(i,16)];
3261 cpu->R[REG_POS(i,12)] = (s32)((s8)READ8(cpu->mem_if->data, adr));
3262 cpu->R[REG_POS(i,16)] += IMM_OFF;
3263
3264 return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
3265 }
3266
3267 static u32 FASTCALL OP_LDRSB_POS_INDE_M_IMM_OFF(armcpu_t *cpu)
3268 {
3269 u32 i = cpu->instruction;
3270 u32 adr = cpu->R[REG_POS(i,16)];
3271 cpu->R[REG_POS(i,12)] = (s32)((s8)READ8(cpu->mem_if->data, adr));
3272 cpu->R[REG_POS(i,16)] -= IMM_OFF;
3273
3274 return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
3275 }
3276
3277 static u32 FASTCALL OP_LDRSB_POS_INDE_P_REG_OFF(armcpu_t *cpu)
3278 {
3279 u32 i = cpu->instruction;
3280 u32 adr = cpu->R[REG_POS(i,16)];
3281 cpu->R[REG_POS(i,12)] = (s32)((s8)READ8(cpu->mem_if->data, adr));
3282 cpu->R[REG_POS(i,16)] += cpu->R[REG_POS(i,0)];
3283
3284 return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
3285 }
3286
3287 static u32 FASTCALL OP_LDRSB_POS_INDE_M_REG_OFF(armcpu_t *cpu)
3288 {
3289 u32 i = cpu->instruction;
3290 u32 adr = cpu->R[REG_POS(i,16)];
3291 cpu->R[REG_POS(i,12)] = (s32)((s8)READ8(cpu->mem_if->data, adr));
3292 cpu->R[REG_POS(i,16)] -= cpu->R[REG_POS(i,0)];
3293
3294 return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
3295 }
3296
3297 //--------------MRS--------------------------------
3298
3299 static u32 FASTCALL OP_MRS_CPSR(armcpu_t *cpu)
3300 {
3301 cpu->R[REG_POS(cpu->instruction,12)] = cpu->CPSR.val;
3302
3303 return 1;
3304 }
3305
3306 static u32 FASTCALL OP_MRS_SPSR(armcpu_t *cpu)
3307 {
3308 cpu->R[REG_POS(cpu->instruction,12)] = cpu->SPSR.val;
3309
3310 return 1;
3311 }
3312
3313 //--------------MSR--------------------------------
3314
3315 static u32 FASTCALL OP_MSR_CPSR(armcpu_t *cpu)
3316 {
3317 u32 i = cpu->instruction;
3318 u32 operand = cpu->R[REG_POS(i,0)];
3319
3320 if(cpu->CPSR.bits.mode!=USR)
3321 {
3322 if(BIT16(i))
3323 {
3324 armcpu_switchMode(cpu, operand & 0x1F);
3325 cpu->CPSR.val = (cpu->CPSR.val & 0xFFFFFF00) | (operand & 0xFF);
3326 }
3327 if(BIT17(i))
3328 cpu->CPSR.val = (cpu->CPSR.val & 0xFFFF00FF) | (operand & 0xFF00);
3329 if(BIT18(i))
3330 cpu->CPSR.val = (cpu->CPSR.val & 0xFF00FFFF) | (operand & 0xFF0000);
3331 }
3332 if(BIT19(i))
3333 cpu->CPSR.val = (cpu->CPSR.val & 0x00FFFFFF) | (operand & 0xFF000000);
3334
3335 return 1;
3336 }
3337
3338 static u32 FASTCALL OP_MSR_SPSR(armcpu_t *cpu)
3339 {
3340 u32 i = cpu->instruction;
3341 u32 operand = cpu->R[REG_POS(i,0)];
3342
3343 if(cpu->CPSR.bits.mode!=USR)
3344 {
3345 if(BIT16(i))
3346 {
3347 cpu->SPSR.val = (cpu->SPSR.val & 0xFFFFFF00) | (operand & 0XFF);
3348 }
3349 if(BIT17(i))
3350 cpu->SPSR.val = (cpu->SPSR.val & 0xFFFF00FF) | (operand & 0XFF00);
3351 if(BIT18(i))
3352 cpu->SPSR.val = (cpu->SPSR.val & 0xFF00FFFF) | (operand & 0XFF0000);
3353 }
3354 if(BIT19(i))
3355 cpu->SPSR.val = (cpu->SPSR.val & 0x00FFFFFF) | (operand & 0XFF000000);
3356
3357 return 1;
3358 }
3359
3360 static u32 FASTCALL OP_MSR_CPSR_IMM_VAL(armcpu_t *cpu)
3361 {
3362 u32 i = cpu->instruction;
3363 IMM_VALUE;
3364
3365 if(cpu->CPSR.bits.mode!=USR)
3366 {
3367 if(BIT16(i))
3368 {
3369 armcpu_switchMode(cpu, shift_op & 0x1F);
3370 cpu->CPSR.val = (cpu->CPSR.val & 0xFFFFFF00) | (shift_op & 0XFF);
3371 }
3372 if(BIT17(i))
3373 cpu->CPSR.val = (cpu->CPSR.val & 0xFFFF00FF) | (shift_op & 0XFF00);
3374 if(BIT18(i))
3375 cpu->CPSR.val = (cpu->CPSR.val & 0xFF00FFFF) | (shift_op & 0XFF0000);
3376 }
3377 if(BIT19(i))
3378 {
3379 //cpu->CPSR.val = (cpu->CPSR.val & 0xFF000000) | (shift_op & 0XFF000000);
3380 cpu->CPSR.val = (cpu->CPSR.val & 0x00FFFFFF) | (shift_op & 0xFF000000);
3381 }
3382
3383 return 1;
3384 }
3385
3386 static u32 FASTCALL OP_MSR_SPSR_IMM_VAL(armcpu_t *cpu)
3387 {
3388 u32 i = cpu->instruction;
3389 IMM_VALUE;
3390
3391 if(cpu->CPSR.bits.mode!=USR)
3392 {
3393 if(BIT16(i))
3394 {
3395 cpu->SPSR.val = (cpu->SPSR.val & 0xFFFFFF00) | (shift_op & 0XFF);
3396 }
3397 if(BIT17(i))
3398 cpu->SPSR.val = (cpu->SPSR.val & 0xFFFF00FF) | (shift_op & 0XFF00);
3399 if(BIT18(i))
3400 cpu->SPSR.val = (cpu->SPSR.val & 0xFF00FFFF) | (shift_op & 0XFF0000);
3401 }
3402 if(BIT19(i))
3403 cpu->SPSR.val = (cpu->SPSR.val & 0xFF000000) | (shift_op & 0XFF000000);
3404
3405 return 1;
3406 }
3407
3408 //-----------------BRANCH--------------------------
3409
3410 static u32 FASTCALL OP_BX(armcpu_t *cpu)
3411 {
3412 u32 tmp = cpu->R[REG_POS(cpu->instruction, 0)];
3413
3414 cpu->CPSR.bits.T = BIT0(tmp);
3415 cpu->R[15] = tmp & 0xFFFFFFFE;
3416 cpu->next_instruction = cpu->R[15];
3417 return 3;
3418 }
3419
3420 static u32 FASTCALL OP_BLX_REG(armcpu_t *cpu)
3421 {
3422 u32 tmp = cpu->R[REG_POS(cpu->instruction, 0)];
3423
3424 cpu->R[14] = cpu->next_instruction;
3425 cpu->CPSR.bits.T = BIT0(tmp);
3426 cpu->R[15] = tmp & 0xFFFFFFFE;
3427 cpu->next_instruction = cpu->R[15];
3428 return 3;
3429 }
3430
3431 #define SIGNEXTEND_24(i) (((s32)((i)<<8))>>8)
3432
3433 static u32 FASTCALL OP_B(armcpu_t *cpu)
3434 {
3435 u32 off = SIGNEXTEND_24(cpu->instruction);
3436 if(CONDITION(cpu->instruction)==0xF)
3437 {
3438 cpu->R[14] = cpu->next_instruction;
3439 cpu->CPSR.bits.T = 1;
3440 }
3441 cpu->R[15] += (off<<2);
3442 cpu->next_instruction = cpu->R[15];
3443
3444 return 3;
3445 }
3446
3447 static u32 FASTCALL OP_BL(armcpu_t *cpu)
3448 {
3449 u32 off = SIGNEXTEND_24(cpu->instruction);
3450 if(CONDITION(cpu->instruction)==0xF)
3451 {
3452 cpu->CPSR.bits.T = 1;
3453 cpu->R[15] += 2;
3454 }
3455 cpu->R[14] = cpu->next_instruction;
3456 cpu->R[15] += (off<<2);
3457 cpu->next_instruction = cpu->R[15];
3458
3459 return 3;
3460 }
3461
3462 //----------------CLZ-------------------------------
3463
3464 u8 CLZ_TAB[16]=
3465 {
3466 0, // 0000
3467 1, // 0001
3468 2, 2, // 001X
3469 3, 3, 3, 3, // 01XX
3470 4, 4, 4, 4, 4, 4, 4, 4 // 1XXX
3471 };
3472
3473 static u32 FASTCALL OP_CLZ(armcpu_t *cpu)
3474 {
3475 u32 i = cpu->instruction;
3476 u32 Rm = cpu->R[REG_POS(i,0)];
3477 u32 pos;
3478
3479 if(Rm==0)
3480 {
3481 cpu->R[REG_POS(i,12)]=32;
3482 return 2;
3483 }
3484
3485 Rm |= (Rm >>1);
3486 Rm |= (Rm >>2);
3487 Rm |= (Rm >>4);
3488 Rm |= (Rm >>8);
3489 Rm |= (Rm >>16);
3490
3491 pos =
3492 CLZ_TAB[Rm&0xF] +
3493 CLZ_TAB[(Rm>>4)&0xF] +
3494 CLZ_TAB[(Rm>>8)&0xF] +
3495 CLZ_TAB[(Rm>>12)&0xF] +
3496 CLZ_TAB[(Rm>>16)&0xF] +
3497 CLZ_TAB[(Rm>>20)&0xF] +
3498 CLZ_TAB[(Rm>>24)&0xF] +
3499 CLZ_TAB[(Rm>>28)&0xF];
3500
3501 cpu->R[REG_POS(i,12)]=32 - pos;
3502
3503 return 2;
3504 }
3505
3506 //--------------------QADD--QSUB------------------------------
3507
3508 static u32 FASTCALL OP_QADD(armcpu_t *cpu)
3509 {
3510 u32 i = cpu->instruction;
3511 u32 res = cpu->R[REG_POS(i,16)]+cpu->R[REG_POS(i,0)];
3512
3513 LOG("spe add\r\n");
3514 if(SIGNED_OVERFLOW(cpu->R[REG_POS(i,16)],cpu->R[REG_POS(i,0)], res))
3515 {
3516 cpu->CPSR.bits.Q=1;
3517 cpu->R[REG_POS(i,12)]=0x80000000-BIT31(res);
3518 return 2;
3519 }
3520 cpu->R[REG_POS(i,12)]=res;
3521 if(REG_POS(i,12)==15)
3522 {
3523 cpu->R[15] &= 0XFFFFFFFC;
3524 cpu->next_instruction = cpu->R[15];
3525 return 3;
3526 }
3527 return 2;
3528 }
3529
3530 static u32 FASTCALL OP_QSUB(armcpu_t *cpu)
3531 {
3532 u32 i = cpu->instruction;
3533 u32 res = cpu->R[REG_POS(i,0)]-cpu->R[REG_POS(i,16)];
3534
3535 LOG("spe add\r\n");
3536 if(SIGNED_UNDERFLOW(cpu->R[REG_POS(i,0)], cpu->R[REG_POS(i,16)], res))
3537 {
3538 cpu->CPSR.bits.Q=1;
3539 cpu->R[REG_POS(i,12)]=0x80000000-BIT31(res);
3540 return 2;
3541 }
3542 cpu->R[REG_POS(i,12)]=res;
3543 if(REG_POS(i,12)==15)
3544 {
3545 cpu->R[15] &= 0XFFFFFFFC;
3546 cpu->next_instruction = cpu->R[15];
3547 return 3;
3548 }
3549 return 2;
3550 }
3551
3552 static u32 FASTCALL OP_QDADD(armcpu_t *cpu)
3553 {
3554 u32 i = cpu->instruction;
3555 u32 mul = cpu->R[REG_POS(i,16)]<<1;
3556 u32 res;
3557
3558
3559 LOG("spe add\r\n");
3560 if(BIT31(cpu->R[REG_POS(i,16)])!=BIT31(mul))
3561 {
3562 cpu->CPSR.bits.Q=1;
3563 mul = 0x80000000-BIT31(mul);
3564 }
3565
3566 res = mul + cpu->R[REG_POS(i,0)];
3567 if(SIGNED_OVERFLOW(cpu->R[REG_POS(i,0)],mul, res))
3568 {
3569 cpu->CPSR.bits.Q=1;
3570 cpu->R[REG_POS(i,12)]=0x80000000-BIT31(res);
3571 return 2;
3572 }
3573 cpu->R[REG_POS(i,12)]=res;
3574 if(REG_POS(i,12)==15)
3575 {
3576 cpu->R[15] &= 0XFFFFFFFC;
3577 cpu->next_instruction = cpu->R[15];
3578 return 3;
3579 }
3580 return 2;
3581 }
3582
3583 static u32 FASTCALL OP_QDSUB(armcpu_t *cpu)
3584 {
3585 u32 i = cpu->instruction;
3586 u32 mul = cpu->R[REG_POS(i,16)]<<1;
3587 u32 res;
3588
3589
3590 LOG("spe add\r\n");
3591 if(BIT31(cpu->R[REG_POS(i,16)])!=BIT31(mul))
3592 {
3593 cpu->CPSR.bits.Q=1;
3594 mul = 0x80000000-BIT31(mul);
3595 }
3596
3597 res = cpu->R[REG_POS(i,0)] - mul;
3598 if(SIGNED_UNDERFLOW(cpu->R[REG_POS(i,0)], mul, res))
3599 {
3600 cpu->CPSR.bits.Q=1;
3601 cpu->R[REG_POS(i,12)]=0x80000000-BIT31(res);
3602 return 2;
3603 }
3604 cpu->R[REG_POS(i,12)]=res;
3605 if(REG_POS(i,12)==15)
3606 {
3607 cpu->R[15] &= 0XFFFFFFFC;
3608 cpu->next_instruction = cpu->R[15];
3609 return 3;
3610 }
3611 return 2;
3612 }
3613
3614 //-----------------SMUL-------------------------------
3615
3616 #define HWORD(i) ((s32)(((s32)(i))>>16))
3617 #define LWORD(i) (s32)(((s32)((i)<<16))>>16)
3618
3619 static u32 FASTCALL OP_SMUL_B_B(armcpu_t *cpu)
3620 {
3621 u32 i = cpu->instruction;
3622
3623 cpu->R[REG_POS(i,16)] = (u32)(LWORD(cpu->R[REG_POS(i,0)])* LWORD(cpu->R[REG_POS(i,8)]));
3624
3625 return 2;
3626 }
3627
3628 static u32 FASTCALL OP_SMUL_B_T(armcpu_t *cpu)
3629 {
3630 u32 i = cpu->instruction;
3631
3632 cpu->R[REG_POS(i,16)] = (u32)(LWORD(cpu->R[REG_POS(i,0)])* HWORD(cpu->R[REG_POS(i,8)]));
3633
3634 return 2;
3635 }
3636
3637 static u32 FASTCALL OP_SMUL_T_B(armcpu_t *cpu)
3638 {
3639 u32 i = cpu->instruction;
3640
3641 cpu->R[REG_POS(i,16)] = (u32)(HWORD(cpu->R[REG_POS(i,0)])* LWORD(cpu->R[REG_POS(i,8)]));
3642
3643 return 2;
3644 }
3645
3646 static u32 FASTCALL OP_SMUL_T_T(armcpu_t *cpu)
3647 {
3648 u32 i = cpu->instruction;
3649
3650 cpu->R[REG_POS(i,16)] = (u32)(HWORD(cpu->R[REG_POS(i,0)])* HWORD(cpu->R[REG_POS(i,8)]));
3651
3652 return 2;
3653 }
3654
3655 //-----------SMLA----------------------------
3656
3657 static u32 FASTCALL OP_SMLA_B_B(armcpu_t *cpu)
3658 {
3659 u32 i = cpu->instruction;
3660 u32 tmp = (u32)(LWORD(cpu->R[REG_POS(i,0)])* LWORD(cpu->R[REG_POS(i,8)]));
3661 u32 a = cpu->R[REG_POS(i,12)];
3662
3663 //LOG("SMLABB %08X * %08X + %08X = %08X\r\n", cpu->R[REG_POS(i,0)], cpu->R[REG_POS(i,8)], a, tmp + a);
3664 cpu->R[REG_POS(i,16)] = tmp + a;
3665
3666 if(SIGNED_OVERFLOW(tmp, a, cpu->R[REG_POS(i,16)]))
3667 cpu->CPSR.bits.Q = 1;
3668
3669 return 2;
3670 }
3671
3672 static u32 FASTCALL OP_SMLA_B_T(armcpu_t *cpu)
3673 {
3674 u32 i = cpu->instruction;
3675 u32 tmp = (u32)(LWORD(cpu->R[REG_POS(i,0)])* HWORD(cpu->R[REG_POS(i,8)]));
3676 u32 a = cpu->R[REG_POS(i,12)];
3677
3678 //LOG("SMLABT %08X * %08X + %08X = %08X\r\n", cpu->R[REG_POS(i,0)], cpu->R[REG_POS(i,8)], a, tmp + a);
3679 cpu->R[REG_POS(i,16)] = tmp + a;
3680
3681 if(SIGNED_OVERFLOW(tmp, a, cpu->R[REG_POS(i,16)]))
3682 cpu->CPSR.bits.Q = 1;
3683
3684 return 2;
3685 }
3686
3687 static u32 FASTCALL OP_SMLA_T_B(armcpu_t *cpu)
3688 {
3689 u32 i = cpu->instruction;
3690 u32 tmp = (u32)(HWORD(cpu->R[REG_POS(i,0)])* LWORD(cpu->R[REG_POS(i,8)]));
3691 u32 a = cpu->R[REG_POS(i,12)];
3692
3693 //LOG("SMLATB %08X * %08X + %08X = %08X\r\n", cpu->R[REG_POS(i,0)], cpu->R[REG_POS(i,8)], a, tmp + a);
3694 cpu->R[REG_POS(i,16)] = tmp + a;
3695
3696 if(SIGNED_OVERFLOW(tmp, a, cpu->R[REG_POS(i,16)]))
3697 cpu->CPSR.bits.Q = 1;
3698
3699 return 2;
3700 }
3701
3702 static u32 FASTCALL OP_SMLA_T_T(armcpu_t *cpu)
3703 {
3704 u32 i = cpu->instruction;
3705 u32 tmp = (u32)(HWORD(cpu->R[REG_POS(i,0)])* HWORD(cpu->R[REG_POS(i,8)]));
3706 u32 a = cpu->R[REG_POS(i,12)];
3707
3708 //LOG("SMLATT %08X * %08X + %08X = %08X\r\n", cpu->R[REG_POS(i,0)], cpu->R[REG_POS(i,8)], a, tmp + a);
3709 cpu->R[REG_POS(i,16)] = tmp + a;
3710
3711 if(SIGNED_OVERFLOW(tmp, a, cpu->R[REG_POS(i,16)]))
3712 cpu->CPSR.bits.Q = 1;
3713
3714 return 2;
3715 }
3716
3717 //--------------SMLAL---------------------------------------
3718
3719 static u32 FASTCALL OP_SMLAL_B_B(armcpu_t *cpu)
3720 {
3721 u32 i = cpu->instruction;
3722 s64 tmp = (s64)(LWORD(cpu->R[REG_POS(i,0)])* LWORD(cpu->R[REG_POS(i,8)]));
3723 u64 res = (u64)tmp + cpu->R[REG_POS(i,12)];
3724
3725 LOG("SMLALBB %08X * %08X + %08X%08X = %08X%08X\r\n", (int)cpu->R[REG_POS(i,0)], (int)cpu->R[REG_POS(i,8)], (int)cpu->R[REG_POS(i,16)], (int)cpu->R[REG_POS(i,12)], (int)(cpu->R[REG_POS(i,16)] + (res + ((tmp<0)*0xFFFFFFFF))), (int)(u32) res);
3726
3727 cpu->R[REG_POS(i,12)] = (u32) res;
3728 cpu->R[REG_POS(i,16)] += (res + ((tmp<0)*0xFFFFFFFF));
3729
3730 return 2;
3731 }
3732
3733 static u32 FASTCALL OP_SMLAL_B_T(armcpu_t *cpu)
3734 {
3735 u32 i = cpu->instruction;
3736 s64 tmp = (s64)(LWORD(cpu->R[REG_POS(i,0)])* HWORD(cpu->R[REG_POS(i,8)]));
3737 u64 res = (u64)tmp + cpu->R[REG_POS(i,12)];
3738
3739 LOG("SMLALBT %08X * %08X + %08X%08X = %08X%08X\r\n", (int)cpu->R[REG_POS(i,0)], (int)cpu->R[REG_POS(i,8)], (int)cpu->R[REG_POS(i,16)], (int)cpu->R[REG_POS(i,12)], (int)(cpu->R[REG_POS(i,16)] + res + ((tmp<0)*0xFFFFFFFF)), (int)(u32) res);
3740
3741 cpu->R[REG_POS(i,12)] = (u32) res;
3742 cpu->R[REG_POS(i,16)] += res + ((tmp<0)*0xFFFFFFFF);
3743
3744 return 2;
3745 }
3746
3747 static u32 FASTCALL OP_SMLAL_T_B(armcpu_t *cpu)
3748 {
3749 u32 i = cpu->instruction;
3750 s64 tmp = (s64)(HWORD(cpu->R[REG_POS(i,0)])* (s64)LWORD(cpu->R[REG_POS(i,8)]));
3751 u64 res = (u64)tmp + cpu->R[REG_POS(i,12)];
3752
3753 LOG("SMLALTB %08X * %08X + %08X%08X = %08X%08X\r\n", (int)cpu->R[REG_POS(i,0)], (int)cpu->R[REG_POS(i,8)], (int)cpu->R[REG_POS(i,16)], (int)cpu->R[REG_POS(i,12)], (int)(cpu->R[REG_POS(i,16)] + res + ((tmp<0)*0xFFFFFFFF)), (int)(u32) res);
3754
3755 cpu->R[REG_POS(i,12)] = (u32) res;
3756 cpu->R[REG_POS(i,16)] += res + ((tmp<0)*0xFFFFFFFF);
3757
3758 return 2;
3759 }
3760
3761 static u32 FASTCALL OP_SMLAL_T_T(armcpu_t *cpu)
3762 {
3763 u32 i = cpu->instruction;
3764 s64 tmp = (s64)(HWORD(cpu->R[REG_POS(i,0)])* HWORD(cpu->R[REG_POS(i,8)]));
3765 u64 res = (u64)tmp + cpu->R[REG_POS(i,12)];
3766
3767 LOG("SMLALTT %08X * %08X + %08X%08X = %08X%08X\r\n", (int)cpu->R[REG_POS(i,0)], (int)cpu->R[REG_POS(i,8)], (int)cpu->R[REG_POS(i,16)], (int)cpu->R[REG_POS(i,12)], (int)(cpu->R[REG_POS(i,16)] + res + ((tmp<0)*0xFFFFFFFF)), (int)(u32) res);
3768
3769 cpu->R[REG_POS(i,12)] = (u32) res;
3770 cpu->R[REG_POS(i,16)] += res + ((tmp<0)*0xFFFFFFFF);
3771
3772 return 2;
3773 }
3774
3775 //--------------SMULW--------------------
3776
3777 static u32 FASTCALL OP_SMULW_B(armcpu_t *cpu)
3778 {
3779 u32 i = cpu->instruction;
3780 s64 tmp = (s64)LWORD(cpu->R[REG_POS(i,8)]) * (s64)((s32)cpu->R[REG_POS(i,0)]);
3781
3782 //LOG("SMULWB %08X * %08X = %08X\r\n", cpu->R[REG_POS(i,0)], cpu->R[REG_POS(i,8)], ((tmp>>16)&0xFFFFFFFF);
3783
3784 cpu->R[REG_POS(i,16)] = ((tmp>>16)&0xFFFFFFFF);
3785
3786 return 2;
3787 }
3788
3789 static u32 FASTCALL OP_SMULW_T(armcpu_t *cpu)
3790 {
3791 u32 i = cpu->instruction;
3792 s64 tmp = (s64)HWORD(cpu->R[REG_POS(i,8)]) * (s64)((s32)cpu->R[REG_POS(i,0)]);
3793
3794 //LOG("SMULWT %08X * %08X = %08X\r\n", cpu->R[REG_POS(i,0)], cpu->R[REG_POS(i,8)], ((tmp>>16)&0xFFFFFFFF));
3795
3796 cpu->R[REG_POS(i,16)] = ((tmp>>16)&0xFFFFFFFF);
3797
3798 return 2;
3799 }
3800
3801 //--------------SMLAW-------------------
3802 static u32 FASTCALL OP_SMLAW_B(armcpu_t *cpu)
3803 {
3804 u32 i = cpu->instruction;
3805 s64 tmp = (s64)LWORD(cpu->R[REG_POS(i,8)]) * (s64)((s32)cpu->R[REG_POS(i,0)]);
3806 u32 a = cpu->R[REG_POS(i,12)];
3807
3808 //LOG("SMLAWB %08X * %08X + %08X = %08X\r\n", cpu->R[REG_POS(i,0)], cpu->R[REG_POS(i,8)], a, (tmp>>16) + a);
3809
3810 tmp = (tmp>>16);
3811
3812 cpu->R[REG_POS(i,16)] = tmp + a;
3813
3814 if(SIGNED_OVERFLOW(tmp, a, cpu->R[REG_POS(i,16)]))
3815 cpu->CPSR.bits.Q = 1;
3816
3817 return 2;
3818 }
3819
3820 static u32 FASTCALL OP_SMLAW_T(armcpu_t *cpu)
3821 {
3822 u32 i = cpu->instruction;
3823 s64 tmp = (s64)HWORD(cpu->R[REG_POS(i,8)]) * (s64)((s32)cpu->R[REG_POS(i,0)]);
3824 u32 a = cpu->R[REG_POS(i,12)];
3825
3826 //LOG("SMLAWT %08X * %08X + %08X = %08X\r\n", cpu->R[REG_POS(i,0)], cpu->R[REG_POS(i,8)], a, ((tmp>>16)&0xFFFFFFFF) + a);
3827
3828 tmp = ((tmp>>16)&0xFFFFFFFF);
3829 cpu->R[REG_POS(i,16)] = tmp + a;
3830
3831 if(SIGNED_OVERFLOW(tmp, a, cpu->R[REG_POS(i,16)]))
3832 cpu->CPSR.bits.Q = 1;
3833
3834 return 2;
3835 }
3836
3837 //------------LDR---------------------------
3838
3839 static u32 FASTCALL OP_LDR_P_IMM_OFF(armcpu_t *cpu)
3840 {
3841 u32 i = cpu->instruction;
3842 u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF_12;
3843 u32 val = READ32(cpu->mem_if->data, adr);
3844
3845 if(adr&3)
3846 val = ROR(val, 8*(adr&3));
3847
3848 if(REG_POS(i,12)==15)
3849 {
3850 cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1));
3851 cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit;
3852 cpu->next_instruction = cpu->R[15];
3853 return 5 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
3854 }
3855
3856 cpu->R[REG_POS(i,12)] = val;
3857 return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
3858 }
3859
3860 static u32 FASTCALL OP_LDR_M_IMM_OFF(armcpu_t *cpu)
3861 {
3862 u32 i = cpu->instruction;
3863 u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF_12;
3864 u32 val = READ32(cpu->mem_if->data, adr);
3865
3866 if(adr&3)
3867 val = ROR(val, 8*(adr&3));
3868
3869 if(REG_POS(i,12)==15)
3870 {
3871 cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1));
3872 cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit;
3873 cpu->next_instruction = cpu->R[15];
3874 return 5 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
3875 }
3876
3877 cpu->R[REG_POS(i,12)] = val;
3878
3879 return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
3880 }
3881
3882 static u32 FASTCALL OP_LDR_P_LSL_IMM_OFF(armcpu_t *cpu)
3883 {
3884 u32 i = cpu->instruction;
3885 u32 adr;
3886 u32 val;
3887 u32 shift_op;
3888 LSL_IMM;
3889 adr = cpu->R[REG_POS(i,16)] + shift_op;
3890 val = READ32(cpu->mem_if->data, adr);
3891
3892 if(adr&3)
3893 val = ROR(val, 8*(adr&3));
3894
3895 if(REG_POS(i,12)==15)
3896 {
3897 cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1));
3898 cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit;
3899 cpu->next_instruction = cpu->R[15];
3900 return 5 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
3901 }
3902
3903 cpu->R[REG_POS(i,12)] = val;
3904
3905 return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
3906 }
3907
3908 static u32 FASTCALL OP_LDR_M_LSL_IMM_OFF(armcpu_t *cpu)
3909 {
3910 u32 i = cpu->instruction;
3911 u32 adr;
3912 u32 val;
3913 u32 shift_op;
3914 LSL_IMM;
3915 adr = cpu->R[REG_POS(i,16)] - shift_op;
3916 val = READ32(cpu->mem_if->data, adr);
3917
3918 if(adr&3)
3919 val = ROR(val, 8*(adr&3));
3920
3921 if(REG_POS(i,12)==15)
3922 {
3923 cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1));
3924 cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit;
3925 cpu->next_instruction = cpu->R[15];
3926 return 5 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
3927 }
3928
3929 cpu->R[REG_POS(i,12)] = val;
3930
3931 return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
3932 }
3933
3934 static u32 FASTCALL OP_LDR_P_LSR_IMM_OFF(armcpu_t *cpu)
3935 {
3936 u32 i = cpu->instruction;
3937 u32 adr;
3938 u32 val;
3939 u32 shift_op;
3940 LSR_IMM;
3941 adr = cpu->R[REG_POS(i,16)] + shift_op;
3942 val = READ32(cpu->mem_if->data, adr);
3943
3944 if(adr&3)
3945 val = ROR(val, 8*(adr&3));
3946
3947 if(REG_POS(i,12)==15)
3948 {
3949 cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1));
3950 cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit;
3951 cpu->next_instruction = cpu->R[15];
3952 return 5 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
3953 }
3954
3955 cpu->R[REG_POS(i,12)] = val;
3956
3957 return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
3958 }
3959
3960 static u32 FASTCALL OP_LDR_M_LSR_IMM_OFF(armcpu_t *cpu)
3961 {
3962 u32 i = cpu->instruction;
3963 u32 adr;
3964 u32 val;
3965 u32 shift_op;
3966 LSR_IMM;
3967 adr = cpu->R[REG_POS(i,16)] - shift_op;
3968 val = READ32(cpu->mem_if->data, adr);
3969
3970 if(adr&3)
3971 val = ROR(val, 8*(adr&3));
3972
3973 if(REG_POS(i,12)==15)
3974 {
3975 cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1));
3976 cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit;
3977 cpu->next_instruction = cpu->R[15];
3978 return 5 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
3979 }
3980
3981 cpu->R[REG_POS(i,12)] = val;
3982
3983 return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
3984 }
3985
3986 static u32 FASTCALL OP_LDR_P_ASR_IMM_OFF(armcpu_t *cpu)
3987 {
3988 u32 i = cpu->instruction;
3989 u32 adr;
3990 u32 val;
3991 u32 shift_op;
3992 ASR_IMM;
3993 adr = cpu->R[REG_POS(i,16)] + shift_op;
3994 val = READ32(cpu->mem_if->data, adr);
3995
3996 if(adr&3)
3997 val = ROR(val, 8*(adr&3));
3998
3999 if(REG_POS(i,12)==15)
4000 {
4001 cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1));
4002 cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit;
4003 cpu->next_instruction = cpu->R[15];
4004 return 5 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
4005 }
4006
4007 cpu->R[REG_POS(i,12)] = val;
4008
4009 return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
4010 }
4011
4012 static u32 FASTCALL OP_LDR_M_ASR_IMM_OFF(armcpu_t *cpu)
4013 {
4014 u32 i = cpu->instruction;
4015 u32 adr;
4016 u32 val;
4017 u32 shift_op;
4018 ASR_IMM;
4019 adr = cpu->R[REG_POS(i,16)] - shift_op;
4020 val = READ32(cpu->mem_if->data, adr);
4021
4022 if(adr&3)
4023 val = ROR(val, 8*(adr&3));
4024
4025 if(REG_POS(i,12)==15)
4026 {
4027 cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1));
4028 cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit;
4029 cpu->next_instruction = cpu->R[15];
4030 return 5 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
4031 }
4032
4033 cpu->R[REG_POS(i,12)] = val;
4034
4035 return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
4036 }
4037
4038 static u32 FASTCALL OP_LDR_P_ROR_IMM_OFF(armcpu_t *cpu)
4039 {
4040 u32 i = cpu->instruction;
4041 u32 adr;
4042 u32 val;
4043 u32 shift_op;
4044 ROR_IMM;
4045 adr = cpu->R[REG_POS(i,16)] + shift_op;
4046 val = READ32(cpu->mem_if->data, adr);
4047
4048 if(adr&3)
4049 val = ROR(val, 8*(adr&3));
4050
4051 if(REG_POS(i,12)==15)
4052 {
4053 cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1));
4054 cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit;
4055 cpu->next_instruction = cpu->R[15];
4056 return 5 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
4057 }
4058
4059 cpu->R[REG_POS(i,12)] = val;
4060
4061 return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
4062 }
4063
4064 static u32 FASTCALL OP_LDR_M_ROR_IMM_OFF(armcpu_t *cpu)
4065 {
4066 u32 i = cpu->instruction;
4067 u32 adr;
4068 u32 val;
4069 u32 shift_op;
4070 ROR_IMM;
4071 adr = cpu->R[REG_POS(i,16)] - shift_op;
4072 val = READ32(cpu->mem_if->data, adr);
4073
4074 if(adr&3)
4075 val = ROR(val, 8*(adr&3));
4076
4077 if(REG_POS(i,12)==15)
4078 {
4079 cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1));
4080 cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit;
4081 cpu->next_instruction = cpu->R[15];
4082 return 5 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
4083 }
4084
4085 cpu->R[REG_POS(i,12)] = val;
4086 cpu->R[REG_POS(i,16)] = adr;
4087
4088 return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
4089 }
4090
4091 static u32 FASTCALL OP_LDR_P_IMM_OFF_PREIND(armcpu_t *cpu)
4092 {
4093 u32 i = cpu->instruction;
4094 u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF_12;
4095 u32 val = READ32(cpu->mem_if->data, adr);
4096
4097 if(adr&3)
4098 val = ROR(val, 8*(adr&3));
4099
4100 if(REG_POS(i,12)==15)
4101 {
4102 cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1));
4103 cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit;
4104 cpu->next_instruction = cpu->R[15];
4105 cpu->R[REG_POS(i,16)] = adr;
4106 return 5 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
4107 }
4108
4109 cpu->R[REG_POS(i,16)] = adr;
4110 cpu->R[REG_POS(i,12)] = val;
4111
4112 return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
4113 }
4114
4115 static u32 FASTCALL OP_LDR_M_IMM_OFF_PREIND(armcpu_t *cpu)
4116 {
4117 u32 i = cpu->instruction;
4118 u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF_12;
4119 u32 val = READ32(cpu->mem_if->data, adr);
4120
4121 if(adr&3)
4122 val = ROR(val, 8*(adr&3));
4123
4124 if(REG_POS(i,12)==15)
4125 {
4126 cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1));
4127 cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit;
4128 cpu->next_instruction = cpu->R[15];
4129 cpu->R[REG_POS(i,16)] = adr;
4130 return 5 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
4131 }
4132
4133 cpu->R[REG_POS(i,16)] = adr;
4134 cpu->R[REG_POS(i,12)] = val;
4135
4136
4137 return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
4138 }
4139
4140 static u32 FASTCALL OP_LDR_P_LSL_IMM_OFF_PREIND(armcpu_t *cpu)
4141 {
4142 u32 i = cpu->instruction;
4143 u32 adr;
4144 u32 val;
4145 u32 shift_op;
4146 LSL_IMM;
4147 adr = cpu->R[REG_POS(i,16)] + shift_op;
4148 val = READ32(cpu->mem_if->data, adr);
4149
4150 if(adr&3)
4151 val = ROR(val, 8*(adr&3));
4152
4153 if(REG_POS(i,12)==15)
4154 {
4155 cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1));
4156 cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit;
4157 cpu->next_instruction = cpu->R[15];
4158 cpu->R[REG_POS(i,16)] = adr;
4159 return 5 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
4160 }
4161
4162 cpu->R[REG_POS(i,16)] = adr;
4163 cpu->R[REG_POS(i,12)] = val;
4164
4165
4166 return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
4167 }
4168
4169 static u32 FASTCALL OP_LDR_M_LSL_IMM_OFF_PREIND(armcpu_t *cpu)
4170 {
4171 u32 i = cpu->instruction;
4172 u32 adr;
4173 u32 val;
4174 u32 shift_op;
4175 LSL_IMM;
4176 adr = cpu->R[REG_POS(i,16)] - shift_op;
4177 val = READ32(cpu->mem_if->data, adr);
4178
4179 if(adr&3)
4180 val = ROR(val, 8*(adr&3));
4181
4182 if(REG_POS(i,12)==15)
4183 {
4184 cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1));
4185 cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit;
4186 cpu->next_instruction = cpu->R[15];
4187 cpu->R[REG_POS(i,16)] = adr;
4188 return 5 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
4189 }
4190
4191 cpu->R[REG_POS(i,16)] = adr;
4192 cpu->R[REG_POS(i,12)] = val;
4193
4194
4195 return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
4196 }
4197
4198 static u32 FASTCALL OP_LDR_P_LSR_IMM_OFF_PREIND(armcpu_t *cpu)
4199 {
4200 u32 i = cpu->instruction;
4201 u32 adr;
4202 u32 val;
4203 u32 shift_op;
4204 LSR_IMM;
4205 adr = cpu->R[REG_POS(i,16)] + shift_op;
4206 val = READ32(cpu->mem_if->data, adr);
4207
4208 if(adr&3)
4209 val = ROR(val, 8*(adr&3));
4210
4211 if(REG_POS(i,12)==15)
4212 {
4213 cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1));
4214 cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit;
4215 cpu->next_instruction = cpu->R[15];
4216 cpu->R[REG_POS(i,16)] = adr;
4217 return 5 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
4218 }
4219
4220 cpu->R[REG_POS(i,16)] = adr;
4221 cpu->R[REG_POS(i,12)] = val;
4222
4223
4224 return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
4225 }
4226
4227 static u32 FASTCALL OP_LDR_M_LSR_IMM_OFF_PREIND(armcpu_t *cpu)
4228 {
4229 u32 i = cpu->instruction;
4230 u32 adr;
4231 u32 val;
4232 u32 shift_op;
4233 LSR_IMM;
4234 adr = cpu->R[REG_POS(i,16)] - shift_op;
4235 val = READ32(cpu->mem_if->data, adr);
4236
4237 if(adr&3)
4238 val = ROR(val, 8*(adr&3));
4239
4240 if(REG_POS(i,12)==15)
4241 {
4242 cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1));
4243 cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit;
4244 cpu->next_instruction = cpu->R[15];
4245 cpu->R[REG_POS(i,16)] = adr;
4246 return 5 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
4247 }
4248
4249 cpu->R[REG_POS(i,16)] = adr;
4250 cpu->R[REG_POS(i,12)] = val;
4251
4252
4253 return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
4254 }
4255
4256 static u32 FASTCALL OP_LDR_P_ASR_IMM_OFF_PREIND(armcpu_t *cpu)
4257 {
4258 u32 i = cpu->instruction;
4259 u32 adr;
4260 u32 val;
4261 u32 shift_op;
4262 ASR_IMM;
4263 adr = cpu->R[REG_POS(i,16)] + shift_op;
4264 val = READ32(cpu->mem_if->data, adr);
4265
4266 if(adr&3)
4267 val = ROR(val, 8*(adr&3));
4268
4269 if(REG_POS(i,12)==15)
4270 {
4271 cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1));
4272 cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit;
4273 cpu->next_instruction = cpu->R[15];
4274 cpu->R[REG_POS(i,16)] = adr;
4275 return 5 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
4276 }
4277
4278 cpu->R[REG_POS(i,16)] = adr;
4279 cpu->R[REG_POS(i,12)] = val;
4280
4281
4282 return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
4283 }
4284
4285 static u32 FASTCALL OP_LDR_M_ASR_IMM_OFF_PREIND(armcpu_t *cpu)
4286 {
4287 u32 i = cpu->instruction;
4288 u32 adr;
4289 u32 val;
4290 u32 shift_op;
4291 ASR_IMM;
4292 adr = cpu->R[REG_POS(i,16)] - shift_op;
4293 val = READ32(cpu->mem_if->data, adr);
4294
4295 if(adr&3)
4296 val = ROR(val, 8*(adr&3));
4297
4298 if(REG_POS(i,12)==15)
4299 {
4300 cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1));
4301 cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit;
4302 cpu->next_instruction = cpu->R[15];
4303 cpu->R[REG_POS(i,16)] = adr;
4304 return 5 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
4305 }
4306
4307 cpu->R[REG_POS(i,16)] = adr;
4308 cpu->R[REG_POS(i,12)] = val;
4309
4310
4311 return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
4312 }
4313
4314 static u32 FASTCALL OP_LDR_P_ROR_IMM_OFF_PREIND(armcpu_t *cpu)
4315 {
4316 u32 i = cpu->instruction;
4317 u32 adr;
4318 u32 val;
4319 u32 shift_op;
4320 ROR_IMM;
4321 adr = cpu->R[REG_POS(i,16)] + shift_op;
4322 val = READ32(cpu->mem_if->data, adr);
4323
4324 if(adr&3)
4325 val = ROR(val, 8*(adr&3));
4326
4327 if(REG_POS(i,12)==15)
4328 {
4329 cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1));
4330 cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit;
4331 cpu->next_instruction = cpu->R[15];
4332 cpu->R[REG_POS(i,16)] = adr;
4333 return 5 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
4334 }
4335
4336 cpu->R[REG_POS(i,16)] = adr;
4337 cpu->R[REG_POS(i,12)] = val;
4338
4339
4340 return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
4341 }
4342
4343 static u32 FASTCALL OP_LDR_M_ROR_IMM_OFF_PREIND(armcpu_t *cpu)
4344 {
4345 u32 i = cpu->instruction;
4346 u32 adr;
4347 u32 val;
4348 u32 shift_op;
4349 ROR_IMM;
4350 adr = cpu->R[REG_POS(i,16)] - shift_op;
4351 val = READ32(cpu->mem_if->data, adr);
4352
4353 if(adr&3)
4354 val = ROR(val, 8*(adr&3));
4355
4356 if(REG_POS(i,12)==15)
4357 {
4358 cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1));
4359 cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit;
4360 cpu->next_instruction = cpu->R[15];
4361 cpu->R[REG_POS(i,16)] = adr;
4362 return 5 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
4363 }
4364
4365 cpu->R[REG_POS(i,16)] = adr;
4366 cpu->R[REG_POS(i,12)] = val;
4367
4368 return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
4369 }
4370
4371 static u32 FASTCALL OP_LDR_P_IMM_OFF_POSTIND(armcpu_t *cpu)
4372 {
4373 u32 i = cpu->instruction;
4374 u32 adr = cpu->R[REG_POS(i,16)];
4375 u32 val = READ32(cpu->mem_if->data, adr);
4376
4377 if(adr&3)
4378 val = ROR(val, 8*(adr&3));
4379
4380 if(REG_POS(i,12)==15)
4381 {
4382 cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1));
4383 cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit;
4384 cpu->next_instruction = cpu->R[15];
4385 cpu->R[REG_POS(i,16)] = adr + IMM_OFF_12;
4386 return 5 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
4387 }
4388
4389 cpu->R[REG_POS(i,16)] = adr + IMM_OFF_12;
4390 cpu->R[REG_POS(i,12)] = val;
4391
4392 return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
4393 }
4394
4395 //------------------------------------------------------------
4396 static u32 FASTCALL OP_LDR_P_IMM_OFF_POSTIND2(armcpu_t *cpu)
4397 {
4398 u32 i = cpu->instruction;
4399
4400 u32 adr = cpu->R[REG_POS(i,16)];
4401 u32 val = READ32(cpu->mem_if->data, adr);
4402 u32 old;
4403 if(adr&3)
4404 val = ROR(val, 8*(adr&3));
4405
4406 if(REG_POS(i,12)==15)
4407 {
4408 cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1));
4409 cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit;
4410 cpu->next_instruction = cpu->R[15];
4411 cpu->R[REG_POS(i,16)] = adr + IMM_OFF_12;
4412 return 5 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
4413 }
4414
4415 old = armcpu_switchMode(cpu, USR);
4416 cpu->R[REG_POS(i,12)] = val;
4417 armcpu_switchMode(cpu, old);
4418
4419 cpu->R[REG_POS(i,16)] = adr + IMM_OFF_12;
4420
4421 return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
4422 }
4423
4424 //------------------------------------------------------------
4425
4426 static u32 FASTCALL OP_LDR_M_IMM_OFF_POSTIND(armcpu_t *cpu)
4427 {
4428 u32 i = cpu->instruction;
4429 u32 adr = cpu->R[REG_POS(i,16)];
4430 u32 val = READ32(cpu->mem_if->data, adr);
4431
4432 if(adr&3)
4433 val = ROR(val, 8*(adr&3));
4434
4435 if(REG_POS(i,12)==15)
4436 {
4437 cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1));
4438 cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit;
4439 cpu->next_instruction = cpu->R[15];
4440 cpu->R[REG_POS(i,16)] = adr - IMM_OFF_12;
4441 return 5 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
4442 }
4443
4444 cpu->R[REG_POS(i,16)] = adr - IMM_OFF_12;
4445 cpu->R[REG_POS(i,12)] = val;
4446
4447 return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
4448 }
4449
4450 static u32 FASTCALL OP_LDR_P_LSL_IMM_OFF_POSTIND(armcpu_t *cpu)
4451 {
4452 u32 i = cpu->instruction;
4453 u32 adr;
4454 u32 val;
4455 u32 shift_op;
4456 LSL_IMM;
4457 adr = cpu->R[REG_POS(i,16)];
4458 val = READ32(cpu->mem_if->data, adr);
4459
4460 if(adr&3)
4461 val = ROR(val, 8*(adr&3));
4462
4463 if(REG_POS(i,12)==15)
4464 {
4465 cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1));
4466 cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit;
4467 cpu->next_instruction = cpu->R[15];
4468 cpu->R[REG_POS(i,16)] = adr + shift_op;
4469 return 5 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
4470 }
4471
4472 cpu->R[REG_POS(i,16)] = adr + shift_op;
4473 cpu->R[REG_POS(i,12)] = val;
4474
4475 return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
4476 }
4477
4478 static u32 FASTCALL OP_LDR_M_LSL_IMM_OFF_POSTIND(armcpu_t *cpu)
4479 {
4480 u32 i = cpu->instruction;
4481 u32 adr;
4482 u32 val;
4483 u32 shift_op;
4484 LSL_IMM;
4485 adr = cpu->R[REG_POS(i,16)];
4486 val = READ32(cpu->mem_if->data, adr);
4487
4488 if(adr&3)
4489 val = ROR(val, 8*(adr&3));
4490
4491 if(REG_POS(i,12)==15)
4492 {
4493 cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1));
4494 cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit;
4495 cpu->next_instruction = cpu->R[15];
4496 cpu->R[REG_POS(i,16)] = adr - shift_op;
4497 return 5 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
4498 }
4499
4500 cpu->R[REG_POS(i,16)] = adr - shift_op;
4501 cpu->R[REG_POS(i,12)] = val;
4502
4503 return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
4504 }
4505
4506 static u32 FASTCALL OP_LDR_P_LSR_IMM_OFF_POSTIND(armcpu_t *cpu)
4507 {
4508 u32 i = cpu->instruction;
4509 u32 adr;
4510 u32 val;
4511 u32 shift_op;
4512 LSR_IMM;
4513 adr = cpu->R[REG_POS(i,16)];
4514 val = READ32(cpu->mem_if->data, adr);
4515
4516 if(adr&3)
4517 val = ROR(val, 8*(adr&3));
4518
4519 if(REG_POS(i,12)==15)
4520 {
4521 cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1));
4522 cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit;
4523 cpu->next_instruction = cpu->R[15];
4524 cpu->R[REG_POS(i,16)] = adr + shift_op;
4525 return 5 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
4526 }
4527
4528 cpu->R[REG_POS(i,16)] = adr + shift_op;
4529 cpu->R[REG_POS(i,12)] = val;
4530
4531 return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
4532 }
4533
4534 static u32 FASTCALL OP_LDR_M_LSR_IMM_OFF_POSTIND(armcpu_t *cpu)
4535 {
4536 u32 i = cpu->instruction;
4537 u32 adr;
4538 u32 val;
4539 u32 shift_op;
4540 LSR_IMM;
4541 adr = cpu->R[REG_POS(i,16)];
4542 val = READ32(cpu->mem_if->data, adr);
4543
4544 if(adr&3)
4545 val = ROR(val, 8*(adr&3));
4546
4547 if(REG_POS(i,12)==15)
4548 {
4549 cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1));
4550 cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit;
4551 cpu->next_instruction = cpu->R[15];
4552 cpu->R[REG_POS(i,16)] = adr - shift_op;
4553 return 5 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
4554 }
4555
4556 cpu->R[REG_POS(i,16)] = adr - shift_op;
4557 cpu->R[REG_POS(i,12)] = val;
4558
4559 return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
4560 }
4561
4562 static u32 FASTCALL OP_LDR_P_ASR_IMM_OFF_POSTIND(armcpu_t *cpu)
4563 {
4564 u32 i = cpu->instruction;
4565 u32 adr;
4566 u32 val;
4567 u32 shift_op;
4568 ASR_IMM;
4569 adr = cpu->R[REG_POS(i,16)];
4570 val = READ32(cpu->mem_if->data, adr);
4571
4572 if(adr&3)
4573 val = ROR(val, 8*(adr&3));
4574
4575 if(REG_POS(i,12)==15)
4576 {
4577 cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1));
4578 cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit;
4579 cpu->next_instruction = cpu->R[15];
4580 cpu->R[REG_POS(i,16)] = adr + shift_op;
4581 return 5 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
4582 }
4583
4584 cpu->R[REG_POS(i,16)] = adr + shift_op;
4585 cpu->R[REG_POS(i,12)] = val;
4586
4587 return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
4588 }
4589
4590 static u32 FASTCALL OP_LDR_M_ASR_IMM_OFF_POSTIND(armcpu_t *cpu)
4591 {
4592 u32 i = cpu->instruction;
4593 u32 adr;
4594 u32 val;
4595 u32 shift_op;
4596 ASR_IMM;
4597 adr = cpu->R[REG_POS(i,16)];
4598 val = READ32(cpu->mem_if->data, adr);
4599
4600 if(adr&3)
4601 val = ROR(val, 8*(adr&3));
4602
4603 if(REG_POS(i,12)==15)
4604 {
4605 cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1));
4606 cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit;
4607 cpu->next_instruction = cpu->R[15];
4608 cpu->R[REG_POS(i,16)] = adr - shift_op;
4609 return 5 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
4610 }
4611
4612 cpu->R[REG_POS(i,16)] = adr - shift_op;
4613 cpu->R[REG_POS(i,12)] = val;
4614
4615 return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
4616 }
4617
4618 static u32 FASTCALL OP_LDR_P_ROR_IMM_OFF_POSTIND(armcpu_t *cpu)
4619 {
4620 u32 i = cpu->instruction;
4621 u32 adr;
4622 u32 val;
4623 u32 shift_op;
4624 ROR_IMM;
4625 adr = cpu->R[REG_POS(i,16)];
4626 val = READ32(cpu->mem_if->data, adr);
4627
4628 if(adr&3)
4629 val = ROR(val, 8*(adr&3));
4630
4631 if(REG_POS(i,12)==15)
4632 {
4633 cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1));
4634 cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit;
4635 cpu->next_instruction = cpu->R[15];
4636 cpu->R[REG_POS(i,16)] = adr + shift_op;
4637 return 5 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
4638 }
4639
4640 cpu->R[REG_POS(i,16)] = adr + shift_op;
4641 cpu->R[REG_POS(i,12)] = val;
4642
4643 return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
4644 }
4645
4646 static u32 FASTCALL OP_LDR_M_ROR_IMM_OFF_POSTIND(armcpu_t *cpu)
4647 {
4648 u32 i = cpu->instruction;
4649 u32 adr;
4650 u32 val;
4651 u32 shift_op;
4652 ROR_IMM;
4653 adr = cpu->R[REG_POS(i,16)];
4654 val = READ32(cpu->mem_if->data, adr);
4655
4656 if(adr&3)
4657 val = ROR(val, 8*(adr&3));
4658
4659 if(REG_POS(i,12)==15)
4660 {
4661 cpu->R[15] = val & (0XFFFFFFFC | (((u32)cpu->LDTBit)<<1));
4662 cpu->CPSR.bits.T = BIT0(val) & cpu->LDTBit;
4663 cpu->next_instruction = cpu->R[15];
4664 cpu->R[REG_POS(i,16)] = adr - shift_op;
4665 return 5 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
4666 }
4667
4668 cpu->R[REG_POS(i,16)] = adr - shift_op;
4669 cpu->R[REG_POS(i,12)] = val;
4670
4671 return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
4672 }
4673
4674 //-----------------LDRB-------------------------------------------
4675
4676 static u32 FASTCALL OP_LDRB_P_IMM_OFF(armcpu_t *cpu)
4677 {
4678 u32 i = cpu->instruction;
4679 u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF_12;
4680 u32 val = READ8(cpu->mem_if->data, adr);
4681 cpu->R[REG_POS(i,12)] = val;
4682
4683 return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
4684 }
4685
4686 static u32 FASTCALL OP_LDRB_M_IMM_OFF(armcpu_t *cpu)
4687 {
4688 u32 i = cpu->instruction;
4689 u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF_12;
4690 u32 val = READ8(cpu->mem_if->data, adr);
4691 cpu->R[REG_POS(i,12)] = val;
4692
4693 return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
4694 }
4695
4696 static u32 FASTCALL OP_LDRB_P_LSL_IMM_OFF(armcpu_t *cpu)
4697 {
4698 u32 i = cpu->instruction;
4699 u32 adr;
4700 u32 val;
4701 u32 shift_op;
4702 LSL_IMM;
4703 adr = cpu->R[REG_POS(i,16)] + shift_op;
4704 val = READ8(cpu->mem_if->data, adr);
4705 cpu->R[REG_POS(i,12)] = val;
4706
4707 return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
4708 }
4709
4710 static u32 FASTCALL OP_LDRB_M_LSL_IMM_OFF(armcpu_t *cpu)
4711 {
4712 u32 i = cpu->instruction;
4713 u32 adr;
4714 u32 val;
4715 u32 shift_op;
4716 LSL_IMM;
4717 adr = cpu->R[REG_POS(i,16)] - shift_op;
4718 val = READ8(cpu->mem_if->data, adr);
4719 cpu->R[REG_POS(i,12)] = val;
4720
4721 return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
4722 }
4723
4724 static u32 FASTCALL OP_LDRB_P_LSR_IMM_OFF(armcpu_t *cpu)
4725 {
4726 u32 i = cpu->instruction;
4727 u32 adr;
4728 u32 val;
4729 u32 shift_op;
4730 LSR_IMM;
4731 adr = cpu->R[REG_POS(i,16)] + shift_op;
4732 val = READ8(cpu->mem_if->data, adr);
4733 cpu->R[REG_POS(i,12)] = val;
4734
4735 return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
4736 }
4737
4738 static u32 FASTCALL OP_LDRB_M_LSR_IMM_OFF(armcpu_t *cpu)
4739 {
4740 u32 i = cpu->instruction;
4741 u32 adr;
4742 u32 val;
4743 u32 shift_op;
4744 LSR_IMM;
4745 adr = cpu->R[REG_POS(i,16)] - shift_op;
4746 val = READ8(cpu->mem_if->data, adr);
4747 cpu->R[REG_POS(i,12)] = val;
4748
4749 return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
4750 }
4751
4752 static u32 FASTCALL OP_LDRB_P_ASR_IMM_OFF(armcpu_t *cpu)
4753 {
4754 u32 i = cpu->instruction;
4755 u32 adr;
4756 u32 val;
4757 u32 shift_op;
4758 ASR_IMM;
4759 adr = cpu->R[REG_POS(i,16)] + shift_op;
4760 val = READ8(cpu->mem_if->data, adr);
4761 cpu->R[REG_POS(i,12)] = val;
4762
4763 return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
4764 }
4765
4766 static u32 FASTCALL OP_LDRB_M_ASR_IMM_OFF(armcpu_t *cpu)
4767 {
4768 u32 i = cpu->instruction;
4769 u32 adr;
4770 u32 val;
4771 u32 shift_op;
4772 ASR_IMM;
4773 adr = cpu->R[REG_POS(i,16)] - shift_op;
4774 val = READ8(cpu->mem_if->data, adr);
4775 cpu->R[REG_POS(i,12)] = val;
4776
4777 return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
4778 }
4779
4780 static u32 FASTCALL OP_LDRB_P_ROR_IMM_OFF(armcpu_t *cpu)
4781 {
4782 u32 i = cpu->instruction;
4783 u32 adr;
4784 u32 val;
4785 u32 shift_op;
4786 ROR_IMM;
4787 adr = cpu->R[REG_POS(i,16)] + shift_op;
4788 val = READ8(cpu->mem_if->data, adr);
4789 cpu->R[REG_POS(i,12)] = val;
4790
4791 return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
4792 }
4793
4794 static u32 FASTCALL OP_LDRB_M_ROR_IMM_OFF(armcpu_t *cpu)
4795 {
4796 u32 i = cpu->instruction;
4797 u32 adr;
4798 u32 val;
4799 u32 shift_op;
4800 ROR_IMM;
4801 adr = cpu->R[REG_POS(i,16)] - shift_op;
4802 val = READ8(cpu->mem_if->data, adr);
4803 cpu->R[REG_POS(i,12)] = val;
4804 cpu->R[REG_POS(i,16)] = adr;
4805
4806 return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
4807 }
4808
4809 static u32 FASTCALL OP_LDRB_P_IMM_OFF_PREIND(armcpu_t *cpu)
4810 {
4811 u32 i = cpu->instruction;
4812 u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF_12;
4813 u32 val = READ8(cpu->mem_if->data, adr);
4814
4815 cpu->R[REG_POS(i,16)] = adr;
4816 cpu->R[REG_POS(i,12)] = val;
4817
4818
4819 return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
4820 }
4821
4822 static u32 FASTCALL OP_LDRB_M_IMM_OFF_PREIND(armcpu_t *cpu)
4823 {
4824 u32 i = cpu->instruction;
4825 u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF_12;
4826 u32 val = READ8(cpu->mem_if->data, adr);
4827
4828 cpu->R[REG_POS(i,16)] = adr;
4829 cpu->R[REG_POS(i,12)] = val;
4830
4831 return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
4832 }
4833
4834 static u32 FASTCALL OP_LDRB_P_LSL_IMM_OFF_PREIND(armcpu_t *cpu)
4835 {
4836 u32 i = cpu->instruction;
4837 u32 adr;
4838 u32 val;
4839 u32 shift_op;
4840 LSL_IMM;
4841 adr = cpu->R[REG_POS(i,16)] + shift_op;
4842 val = READ8(cpu->mem_if->data, adr);
4843
4844 cpu->R[REG_POS(i,16)] = adr;
4845 cpu->R[REG_POS(i,12)] = val;
4846
4847
4848 return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
4849 }
4850
4851 static u32 FASTCALL OP_LDRB_M_LSL_IMM_OFF_PREIND(armcpu_t *cpu)
4852 {
4853 u32 i = cpu->instruction;
4854 u32 adr;
4855 u32 val;
4856 u32 shift_op;
4857 LSL_IMM;
4858 adr = cpu->R[REG_POS(i,16)] - shift_op;
4859 val = READ8(cpu->mem_if->data, adr);
4860
4861 cpu->R[REG_POS(i,16)] = adr;
4862 cpu->R[REG_POS(i,12)] = val;
4863
4864 return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
4865 }
4866
4867 static u32 FASTCALL OP_LDRB_P_LSR_IMM_OFF_PREIND(armcpu_t *cpu)
4868 {
4869 u32 i = cpu->instruction;
4870 u32 adr;
4871 u32 val;
4872 u32 shift_op;
4873 LSR_IMM;
4874 adr = cpu->R[REG_POS(i,16)] + shift_op;
4875 val = READ8(cpu->mem_if->data, adr);
4876 cpu->R[REG_POS(i,16)] = adr;
4877 cpu->R[REG_POS(i,12)] = val;
4878
4879 return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
4880 }
4881
4882 static u32 FASTCALL OP_LDRB_M_LSR_IMM_OFF_PREIND(armcpu_t *cpu)
4883 {
4884 u32 i = cpu->instruction;
4885 u32 adr;
4886 u32 val;
4887 u32 shift_op;
4888 LSR_IMM;
4889 adr = cpu->R[REG_POS(i,16)] - shift_op;
4890 val = READ8(cpu->mem_if->data, adr);
4891 cpu->R[REG_POS(i,16)] = adr;
4892 cpu->R[REG_POS(i,12)] = val;
4893
4894 return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
4895 }
4896
4897 static u32 FASTCALL OP_LDRB_P_ASR_IMM_OFF_PREIND(armcpu_t *cpu)
4898 {
4899 u32 i = cpu->instruction;
4900 u32 adr;
4901 u32 val;
4902 u32 shift_op;
4903 ASR_IMM;
4904 adr = cpu->R[REG_POS(i,16)] + shift_op;
4905 val = READ8(cpu->mem_if->data, adr);
4906 cpu->R[REG_POS(i,16)] = adr;
4907 cpu->R[REG_POS(i,12)] = val;
4908
4909 return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
4910 }
4911
4912 static u32 FASTCALL OP_LDRB_M_ASR_IMM_OFF_PREIND(armcpu_t *cpu)
4913 {
4914 u32 i = cpu->instruction;
4915 u32 adr;
4916 u32 val;
4917 u32 shift_op;
4918 ASR_IMM;
4919 adr = cpu->R[REG_POS(i,16)] - shift_op;
4920 val = READ8(cpu->mem_if->data, adr);
4921 cpu->R[REG_POS(i,16)] = adr;
4922 cpu->R[REG_POS(i,12)] = val;
4923
4924 return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
4925 }
4926
4927 static u32 FASTCALL OP_LDRB_P_ROR_IMM_OFF_PREIND(armcpu_t *cpu)
4928 {
4929 u32 i = cpu->instruction;
4930 u32 adr;
4931 u32 val;
4932 u32 shift_op;
4933 ROR_IMM;
4934 adr = cpu->R[REG_POS(i,16)] + shift_op;
4935 val = READ8(cpu->mem_if->data, adr);
4936 cpu->R[REG_POS(i,16)] = adr;
4937 cpu->R[REG_POS(i,12)] = val;
4938
4939 return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
4940 }
4941
4942 static u32 FASTCALL OP_LDRB_M_ROR_IMM_OFF_PREIND(armcpu_t *cpu)
4943 {
4944 u32 i = cpu->instruction;
4945 u32 adr;
4946 u32 val;
4947 u32 shift_op;
4948 ROR_IMM;
4949 adr = cpu->R[REG_POS(i,16)] - shift_op;
4950 val = READ8(cpu->mem_if->data, adr);
4951 cpu->R[REG_POS(i,16)] = adr;
4952 cpu->R[REG_POS(i,12)] = val;
4953
4954 return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
4955 }
4956
4957 static u32 FASTCALL OP_LDRB_P_IMM_OFF_POSTIND(armcpu_t *cpu)
4958 {
4959 u32 i = cpu->instruction;
4960 u32 adr = cpu->R[REG_POS(i,16)];
4961 u32 val = READ8(cpu->mem_if->data, adr);
4962 cpu->R[REG_POS(i,16)] = adr + IMM_OFF_12;
4963 cpu->R[REG_POS(i,12)] = val;
4964
4965 return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
4966 }
4967
4968 static u32 FASTCALL OP_LDRB_M_IMM_OFF_POSTIND(armcpu_t *cpu)
4969 {
4970 u32 i = cpu->instruction;
4971 u32 adr = cpu->R[REG_POS(i,16)];
4972 u32 val = READ8(cpu->mem_if->data, adr);
4973 cpu->R[REG_POS(i,16)] = adr - IMM_OFF_12;
4974 cpu->R[REG_POS(i,12)] = val;
4975
4976 return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
4977 }
4978
4979 static u32 FASTCALL OP_LDRB_P_LSL_IMM_OFF_POSTIND(armcpu_t *cpu)
4980 {
4981 u32 i = cpu->instruction;
4982 u32 adr;
4983 u32 val;
4984 u32 shift_op;
4985 LSL_IMM;
4986 adr = cpu->R[REG_POS(i,16)];
4987 val = READ8(cpu->mem_if->data, adr);
4988 cpu->R[REG_POS(i,16)] = adr + shift_op;
4989 cpu->R[REG_POS(i,12)] = val;
4990
4991 return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
4992 }
4993
4994 static u32 FASTCALL OP_LDRB_M_LSL_IMM_OFF_POSTIND(armcpu_t *cpu)
4995 {
4996 u32 i = cpu->instruction;
4997 u32 adr;
4998 u32 val;
4999 u32 shift_op;
5000 LSL_IMM;
5001 adr = cpu->R[REG_POS(i,16)];
5002 val = READ8(cpu->mem_if->data, adr);
5003 cpu->R[REG_POS(i,16)] = adr - shift_op;
5004 cpu->R[REG_POS(i,12)] = val;
5005
5006 return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
5007 }
5008
5009 static u32 FASTCALL OP_LDRB_P_LSR_IMM_OFF_POSTIND(armcpu_t *cpu)
5010 {
5011 u32 i = cpu->instruction;
5012 u32 adr;
5013 u32 val;
5014 u32 shift_op;
5015 LSR_IMM;
5016 adr = cpu->R[REG_POS(i,16)];
5017 val = READ8(cpu->mem_if->data, adr);
5018 cpu->R[REG_POS(i,16)] = adr + shift_op;
5019 cpu->R[REG_POS(i,12)] = val;
5020
5021 return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
5022 }
5023
5024 static u32 FASTCALL OP_LDRB_M_LSR_IMM_OFF_POSTIND(armcpu_t *cpu)
5025 {
5026 u32 i = cpu->instruction;
5027 u32 adr;
5028 u32 val;
5029 u32 shift_op;
5030 LSR_IMM;
5031 adr = cpu->R[REG_POS(i,16)];
5032 val = READ8(cpu->mem_if->data, adr);
5033 cpu->R[REG_POS(i,16)] = adr - shift_op;
5034 cpu->R[REG_POS(i,12)] = val;
5035
5036 return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
5037 }
5038
5039 static u32 FASTCALL OP_LDRB_P_ASR_IMM_OFF_POSTIND(armcpu_t *cpu)
5040 {
5041 u32 i = cpu->instruction;
5042 u32 adr;
5043 u32 val;
5044 u32 shift_op;
5045 ASR_IMM;
5046 adr = cpu->R[REG_POS(i,16)];
5047 val = READ8(cpu->mem_if->data, adr);
5048 cpu->R[REG_POS(i,16)] = adr + shift_op;
5049 cpu->R[REG_POS(i,12)] = val;
5050
5051 return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
5052 }
5053
5054 static u32 FASTCALL OP_LDRB_M_ASR_IMM_OFF_POSTIND(armcpu_t *cpu)
5055 {
5056 u32 i = cpu->instruction;
5057 u32 adr;
5058 u32 val;
5059 u32 shift_op;
5060 ASR_IMM;
5061 adr = cpu->R[REG_POS(i,16)];
5062 val = READ8(cpu->mem_if->data, adr);
5063 cpu->R[REG_POS(i,16)] = adr - shift_op;
5064 cpu->R[REG_POS(i,12)] = val;
5065
5066 return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
5067 }
5068
5069 static u32 FASTCALL OP_LDRB_P_ROR_IMM_OFF_POSTIND(armcpu_t *cpu)
5070 {
5071 u32 i = cpu->instruction;
5072 u32 adr;
5073 u32 val;
5074 u32 shift_op;
5075 ROR_IMM;
5076 adr = cpu->R[REG_POS(i,16)];
5077 val = READ8(cpu->mem_if->data, adr);
5078 cpu->R[REG_POS(i,16)] = adr + shift_op;
5079 cpu->R[REG_POS(i,12)] = val;
5080
5081 return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
5082 }
5083
5084 static u32 FASTCALL OP_LDRB_M_ROR_IMM_OFF_POSTIND(armcpu_t *cpu)
5085 {
5086 u32 i = cpu->instruction;
5087 u32 adr;
5088 u32 val;
5089 u32 shift_op;
5090 ROR_IMM;
5091 adr = cpu->R[REG_POS(i,16)];
5092 val = READ8(cpu->mem_if->data, adr);
5093 cpu->R[REG_POS(i,16)] = adr - shift_op;
5094 cpu->R[REG_POS(i,12)] = val;
5095
5096 return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
5097 }
5098
5099 //----------------------STR--------------------------------
5100
5101 static u32 FASTCALL OP_STR_P_IMM_OFF(armcpu_t *cpu)
5102 {
5103 u32 i = cpu->instruction;
5104 u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF_12;
5105 WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]);
5106
5107 // execute = false;
5108
5109 return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
5110 }
5111
5112 static u32 FASTCALL OP_STR_M_IMM_OFF(armcpu_t *cpu)
5113 {
5114 u32 i = cpu->instruction;
5115 u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF_12;
5116 WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]);
5117
5118 return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
5119 }
5120
5121 static u32 FASTCALL OP_STR_P_LSL_IMM_OFF(armcpu_t *cpu)
5122 {
5123 u32 i = cpu->instruction;
5124 u32 adr;
5125 u32 shift_op;
5126 LSL_IMM;
5127 adr = cpu->R[REG_POS(i,16)] + shift_op;
5128 WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]);
5129
5130 return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
5131 }
5132
5133 static u32 FASTCALL OP_STR_M_LSL_IMM_OFF(armcpu_t *cpu)
5134 {
5135 u32 i = cpu->instruction;
5136 u32 adr;
5137 u32 shift_op;
5138 LSL_IMM;
5139 adr = cpu->R[REG_POS(i,16)] - shift_op;
5140 WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]);
5141
5142 return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
5143 }
5144
5145 static u32 FASTCALL OP_STR_P_LSR_IMM_OFF(armcpu_t *cpu)
5146 {
5147 u32 i = cpu->instruction;
5148 u32 adr;
5149 u32 shift_op;
5150 LSR_IMM;
5151 adr = cpu->R[REG_POS(i,16)] + shift_op;
5152 WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]);
5153
5154 return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
5155 }
5156
5157 static u32 FASTCALL OP_STR_M_LSR_IMM_OFF(armcpu_t *cpu)
5158 {
5159 u32 i = cpu->instruction;
5160 u32 adr;
5161 u32 shift_op;
5162 LSR_IMM;
5163 adr = cpu->R[REG_POS(i,16)] - shift_op;
5164 WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]);
5165
5166 return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
5167 }
5168
5169 static u32 FASTCALL OP_STR_P_ASR_IMM_OFF(armcpu_t *cpu)
5170 {
5171 u32 i = cpu->instruction;
5172 u32 adr;
5173 u32 shift_op;
5174 ASR_IMM;
5175 adr = cpu->R[REG_POS(i,16)] + shift_op;
5176 WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]);
5177
5178 return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
5179 }
5180
5181 static u32 FASTCALL OP_STR_M_ASR_IMM_OFF(armcpu_t *cpu)
5182 {
5183 u32 i = cpu->instruction;
5184 u32 adr;
5185 u32 shift_op;
5186 ASR_IMM;
5187 adr = cpu->R[REG_POS(i,16)] - shift_op;
5188 WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]);
5189
5190 return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
5191 }
5192
5193 static u32 FASTCALL OP_STR_P_ROR_IMM_OFF(armcpu_t *cpu)
5194 {
5195 u32 i = cpu->instruction;
5196 u32 adr;
5197 u32 shift_op;
5198 ROR_IMM;
5199 adr = cpu->R[REG_POS(i,16)] + shift_op;
5200 WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]);
5201
5202 return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
5203 }
5204
5205 static u32 FASTCALL OP_STR_M_ROR_IMM_OFF(armcpu_t *cpu)
5206 {
5207 u32 i = cpu->instruction;
5208 u32 adr;
5209 u32 shift_op;
5210 ROR_IMM;
5211 adr = cpu->R[REG_POS(i,16)] - shift_op;
5212 WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]);
5213 cpu->R[REG_POS(i,16)] = adr;
5214
5215 return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
5216 }
5217
5218 static u32 FASTCALL OP_STR_P_IMM_OFF_PREIND(armcpu_t *cpu)
5219 {
5220 u32 i = cpu->instruction;
5221 u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF_12;
5222 WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]);
5223 cpu->R[REG_POS(i,16)] = adr;
5224
5225 return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
5226 }
5227
5228 static u32 FASTCALL OP_STR_M_IMM_OFF_PREIND(armcpu_t *cpu)
5229 {
5230 u32 i = cpu->instruction;
5231 u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF_12;
5232 WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]);
5233 cpu->R[REG_POS(i,16)] = adr;
5234
5235 return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
5236 }
5237
5238 static u32 FASTCALL OP_STR_P_LSL_IMM_OFF_PREIND(armcpu_t *cpu)
5239 {
5240 u32 i = cpu->instruction;
5241 u32 adr;
5242 u32 shift_op;
5243 LSL_IMM;
5244 adr = cpu->R[REG_POS(i,16)] + shift_op;
5245 WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]);
5246 cpu->R[REG_POS(i,16)] = adr;
5247
5248 return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
5249 }
5250
5251 static u32 FASTCALL OP_STR_M_LSL_IMM_OFF_PREIND(armcpu_t *cpu)
5252 {
5253 u32 i = cpu->instruction;
5254 u32 adr;
5255 u32 shift_op;
5256 LSL_IMM;
5257 adr = cpu->R[REG_POS(i,16)] - shift_op;
5258 WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]);
5259 cpu->R[REG_POS(i,16)] = adr;
5260
5261 return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
5262 }
5263
5264 static u32 FASTCALL OP_STR_P_LSR_IMM_OFF_PREIND(armcpu_t *cpu)
5265 {
5266 u32 i = cpu->instruction;
5267 u32 adr;
5268 u32 shift_op;
5269 LSR_IMM;
5270 adr = cpu->R[REG_POS(i,16)] + shift_op;
5271 WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]);
5272 cpu->R[REG_POS(i,16)] = adr;
5273
5274 return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
5275 }
5276
5277 static u32 FASTCALL OP_STR_M_LSR_IMM_OFF_PREIND(armcpu_t *cpu)
5278 {
5279 u32 i = cpu->instruction;
5280 u32 adr;
5281 u32 shift_op;
5282 LSR_IMM;
5283 adr = cpu->R[REG_POS(i,16)] - shift_op;
5284 WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]);
5285 cpu->R[REG_POS(i,16)] = adr;
5286
5287 return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
5288 }
5289
5290 static u32 FASTCALL OP_STR_P_ASR_IMM_OFF_PREIND(armcpu_t *cpu)
5291 {
5292 u32 i = cpu->instruction;
5293 u32 adr;
5294 u32 shift_op;
5295 ASR_IMM;
5296 adr = cpu->R[REG_POS(i,16)] + shift_op;
5297 WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]);
5298 cpu->R[REG_POS(i,16)] = adr;
5299
5300 return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
5301 }
5302
5303 static u32 FASTCALL OP_STR_M_ASR_IMM_OFF_PREIND(armcpu_t *cpu)
5304 {
5305 u32 i = cpu->instruction;
5306 u32 adr;
5307 u32 shift_op;
5308 ASR_IMM;
5309 adr = cpu->R[REG_POS(i,16)] - shift_op;
5310 WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]);
5311 cpu->R[REG_POS(i,16)] = adr;
5312
5313 return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
5314 }
5315
5316 static u32 FASTCALL OP_STR_P_ROR_IMM_OFF_PREIND(armcpu_t *cpu)
5317 {
5318 u32 i = cpu->instruction;
5319 u32 adr;
5320 u32 shift_op;
5321 ROR_IMM;
5322 adr = cpu->R[REG_POS(i,16)] + shift_op;
5323 WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]);
5324 cpu->R[REG_POS(i,16)] = adr;
5325
5326 return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
5327 }
5328
5329 static u32 FASTCALL OP_STR_M_ROR_IMM_OFF_PREIND(armcpu_t *cpu)
5330 {
5331 u32 i = cpu->instruction;
5332 u32 adr;
5333 u32 shift_op;
5334 ROR_IMM;
5335 adr = cpu->R[REG_POS(i,16)] - shift_op;
5336 WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]);
5337 cpu->R[REG_POS(i,16)] = adr;
5338
5339 return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
5340 }
5341
5342 static u32 FASTCALL OP_STR_P_IMM_OFF_POSTIND(armcpu_t *cpu)
5343 {
5344 u32 i = cpu->instruction;
5345 u32 adr = cpu->R[REG_POS(i,16)];
5346 WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]);
5347 cpu->R[REG_POS(i,16)] = adr + IMM_OFF_12;
5348
5349 return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
5350 }
5351
5352 static u32 FASTCALL OP_STR_M_IMM_OFF_POSTIND(armcpu_t *cpu)
5353 {
5354 u32 i = cpu->instruction;
5355 u32 adr = cpu->R[REG_POS(i,16)];
5356 WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]);
5357 cpu->R[REG_POS(i,16)] = adr - IMM_OFF_12;
5358
5359 return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
5360 }
5361
5362 static u32 FASTCALL OP_STR_P_LSL_IMM_OFF_POSTIND(armcpu_t *cpu)
5363 {
5364 u32 i = cpu->instruction;
5365 u32 adr;
5366 u32 shift_op;
5367 LSL_IMM;
5368 adr = cpu->R[REG_POS(i,16)];
5369 WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]);
5370 cpu->R[REG_POS(i,16)] = adr + shift_op;
5371
5372 return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
5373 }
5374
5375 static u32 FASTCALL OP_STR_M_LSL_IMM_OFF_POSTIND(armcpu_t *cpu)
5376 {
5377 u32 i = cpu->instruction;
5378 u32 adr;
5379 u32 shift_op;
5380 LSL_IMM;
5381 adr = cpu->R[REG_POS(i,16)];
5382 WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]);
5383 cpu->R[REG_POS(i,16)] = adr - shift_op;
5384
5385 return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
5386 }
5387
5388 static u32 FASTCALL OP_STR_P_LSR_IMM_OFF_POSTIND(armcpu_t *cpu)
5389 {
5390 u32 i = cpu->instruction;
5391 u32 adr;
5392 u32 shift_op;
5393 LSR_IMM;
5394 adr = cpu->R[REG_POS(i,16)];
5395 WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]);
5396 cpu->R[REG_POS(i,16)] = adr + shift_op;
5397
5398 return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
5399 }
5400
5401 static u32 FASTCALL OP_STR_M_LSR_IMM_OFF_POSTIND(armcpu_t *cpu)
5402 {
5403 u32 i = cpu->instruction;
5404 u32 adr;
5405 u32 shift_op;
5406 LSR_IMM;
5407 adr = cpu->R[REG_POS(i,16)];
5408 WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]);
5409 cpu->R[REG_POS(i,16)] = adr - shift_op;
5410
5411 return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
5412 }
5413
5414 static u32 FASTCALL OP_STR_P_ASR_IMM_OFF_POSTIND(armcpu_t *cpu)
5415 {
5416 u32 i = cpu->instruction;
5417 u32 adr;
5418 u32 shift_op;
5419 ASR_IMM;
5420 adr = cpu->R[REG_POS(i,16)];
5421 WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]);
5422 cpu->R[REG_POS(i,16)] = adr + shift_op;
5423
5424 return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
5425 }
5426
5427 static u32 FASTCALL OP_STR_M_ASR_IMM_OFF_POSTIND(armcpu_t *cpu)
5428 {
5429 u32 i = cpu->instruction;
5430 u32 adr;
5431 u32 shift_op;
5432 ASR_IMM;
5433 adr = cpu->R[REG_POS(i,16)];
5434 WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]);
5435 cpu->R[REG_POS(i,16)] = adr - shift_op;
5436
5437 return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
5438 }
5439
5440 static u32 FASTCALL OP_STR_P_ROR_IMM_OFF_POSTIND(armcpu_t *cpu)
5441 {
5442 u32 i = cpu->instruction;
5443 u32 adr;
5444 u32 shift_op;
5445 ROR_IMM;
5446 adr = cpu->R[REG_POS(i,16)];
5447 WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]);
5448 cpu->R[REG_POS(i,16)] = adr + shift_op;
5449
5450 return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
5451 }
5452
5453 static u32 FASTCALL OP_STR_M_ROR_IMM_OFF_POSTIND(armcpu_t *cpu)
5454 {
5455 u32 i = cpu->instruction;
5456 u32 adr;
5457 u32 shift_op;
5458 ROR_IMM;
5459 adr = cpu->R[REG_POS(i,16)];
5460 WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]);
5461 cpu->R[REG_POS(i,16)] = adr - shift_op;
5462
5463 return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
5464 }
5465
5466 //-----------------------STRB-------------------------------------
5467
5468 static u32 FASTCALL OP_STRB_P_IMM_OFF(armcpu_t *cpu)
5469 {
5470 u32 i = cpu->instruction;
5471 u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF_12;
5472 WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]);
5473
5474 return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
5475 }
5476
5477 static u32 FASTCALL OP_STRB_M_IMM_OFF(armcpu_t *cpu)
5478 {
5479 u32 i = cpu->instruction;
5480 u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF_12;
5481 WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]);
5482
5483 return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
5484 }
5485
5486 static u32 FASTCALL OP_STRB_P_LSL_IMM_OFF(armcpu_t *cpu)
5487 {
5488 u32 i = cpu->instruction;
5489 u32 adr;
5490 u32 shift_op;
5491 LSL_IMM;
5492 adr = cpu->R[REG_POS(i,16)] + shift_op;
5493 WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]);
5494
5495 return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
5496 }
5497
5498 static u32 FASTCALL OP_STRB_M_LSL_IMM_OFF(armcpu_t *cpu)
5499 {
5500 u32 i = cpu->instruction;
5501 u32 adr;
5502 u32 shift_op;
5503 LSL_IMM;
5504 adr = cpu->R[REG_POS(i,16)] - shift_op;
5505 WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]);
5506
5507 return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
5508 }
5509
5510 static u32 FASTCALL OP_STRB_P_LSR_IMM_OFF(armcpu_t *cpu)
5511 {
5512 u32 i = cpu->instruction;
5513 u32 adr;
5514 u32 shift_op;
5515 LSR_IMM;
5516 adr = cpu->R[REG_POS(i,16)] + shift_op;
5517 WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]);
5518
5519 return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
5520 }
5521
5522 static u32 FASTCALL OP_STRB_M_LSR_IMM_OFF(armcpu_t *cpu)
5523 {
5524 u32 i = cpu->instruction;
5525 u32 adr;
5526 u32 shift_op;
5527 LSR_IMM;
5528 adr = cpu->R[REG_POS(i,16)] - shift_op;
5529 WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]);
5530
5531 return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
5532 }
5533
5534 static u32 FASTCALL OP_STRB_P_ASR_IMM_OFF(armcpu_t *cpu)
5535 {
5536 u32 i = cpu->instruction;
5537 u32 adr;
5538 u32 shift_op;
5539 ASR_IMM;
5540 adr = cpu->R[REG_POS(i,16)] + shift_op;
5541 WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]);
5542
5543 return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
5544 }
5545
5546 static u32 FASTCALL OP_STRB_M_ASR_IMM_OFF(armcpu_t *cpu)
5547 {
5548 u32 i = cpu->instruction;
5549 u32 adr;
5550 u32 shift_op;
5551 ASR_IMM;
5552 adr = cpu->R[REG_POS(i,16)] - shift_op;
5553 WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]);
5554
5555 return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
5556 }
5557
5558 static u32 FASTCALL OP_STRB_P_ROR_IMM_OFF(armcpu_t *cpu)
5559 {
5560 u32 i = cpu->instruction;
5561 u32 adr;
5562 u32 shift_op;
5563 ROR_IMM;
5564 adr = cpu->R[REG_POS(i,16)] + shift_op;
5565 WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]);
5566
5567 return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
5568 }
5569
5570 static u32 FASTCALL OP_STRB_M_ROR_IMM_OFF(armcpu_t *cpu)
5571 {
5572 u32 i = cpu->instruction;
5573 u32 adr;
5574 u32 shift_op;
5575 ROR_IMM;
5576 adr = cpu->R[REG_POS(i,16)] - shift_op;
5577 WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]);
5578
5579 return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
5580 }
5581
5582 static u32 FASTCALL OP_STRB_P_IMM_OFF_PREIND(armcpu_t *cpu)
5583 {
5584 u32 i = cpu->instruction;
5585 u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF_12;
5586 WRITE8(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]);
5587 cpu->R[REG_POS(i,16)] = adr;
5588
5589 return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
5590 }
5591
5592 static u32 FASTCALL OP_STRB_M_IMM_OFF_PREIND(armcpu_t *cpu)
5593 {
5594 u32 i = cpu->instruction;
5595 u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF_12;
5596 WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]);
5597 cpu->R[REG_POS(i,16)] = adr;
5598
5599 return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
5600 }
5601
5602 static u32 FASTCALL OP_STRB_P_LSL_IMM_OFF_PREIND(armcpu_t *cpu)
5603 {
5604 u32 i = cpu->instruction;
5605 u32 adr;
5606 u32 shift_op;
5607 LSL_IMM;
5608 adr = cpu->R[REG_POS(i,16)] + shift_op;
5609 WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]);
5610 cpu->R[REG_POS(i,16)] = adr;
5611
5612 return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
5613 }
5614
5615 static u32 FASTCALL OP_STRB_M_LSL_IMM_OFF_PREIND(armcpu_t *cpu)
5616 {
5617 u32 i = cpu->instruction;
5618 u32 adr;
5619 u32 shift_op;
5620 LSL_IMM;
5621 adr = cpu->R[REG_POS(i,16)] - shift_op;
5622 WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]);
5623 cpu->R[REG_POS(i,16)] = adr;
5624
5625 return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
5626 }
5627
5628 static u32 FASTCALL OP_STRB_P_LSR_IMM_OFF_PREIND(armcpu_t *cpu)
5629 {
5630 u32 i = cpu->instruction;
5631 u32 adr;
5632 u32 shift_op;
5633 LSR_IMM;
5634 adr = cpu->R[REG_POS(i,16)] + shift_op;
5635 WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]);
5636 cpu->R[REG_POS(i,16)] = adr;
5637
5638 return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
5639 }
5640
5641 static u32 FASTCALL OP_STRB_M_LSR_IMM_OFF_PREIND(armcpu_t *cpu)
5642 {
5643 u32 i = cpu->instruction;
5644 u32 adr;
5645 u32 shift_op;
5646 LSR_IMM;
5647 adr = cpu->R[REG_POS(i,16)] - shift_op;
5648 WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]);
5649 cpu->R[REG_POS(i,16)] = adr;
5650
5651 return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
5652 }
5653
5654 static u32 FASTCALL OP_STRB_P_ASR_IMM_OFF_PREIND(armcpu_t *cpu)
5655 {
5656 u32 i = cpu->instruction;
5657 u32 adr;
5658 u32 shift_op;
5659 ASR_IMM;
5660 adr = cpu->R[REG_POS(i,16)] + shift_op;
5661 WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]);
5662 cpu->R[REG_POS(i,16)] = adr;
5663
5664 return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
5665 }
5666
5667 static u32 FASTCALL OP_STRB_M_ASR_IMM_OFF_PREIND(armcpu_t *cpu)
5668 {
5669 u32 i = cpu->instruction;
5670 u32 adr;
5671 u32 shift_op;
5672 ASR_IMM;
5673 adr = cpu->R[REG_POS(i,16)] - shift_op;
5674 WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]);
5675 cpu->R[REG_POS(i,16)] = adr;
5676
5677 return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
5678 }
5679
5680 static u32 FASTCALL OP_STRB_P_ROR_IMM_OFF_PREIND(armcpu_t *cpu)
5681 {
5682 u32 i = cpu->instruction;
5683 u32 adr;
5684 u32 shift_op;
5685 ROR_IMM;
5686 adr = cpu->R[REG_POS(i,16)] + shift_op;
5687 WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]);
5688 cpu->R[REG_POS(i,16)] = adr;
5689
5690 return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
5691 }
5692
5693 static u32 FASTCALL OP_STRB_M_ROR_IMM_OFF_PREIND(armcpu_t *cpu)
5694 {
5695 u32 i = cpu->instruction;
5696 u32 adr;
5697 u32 shift_op;
5698 ROR_IMM;
5699 adr = cpu->R[REG_POS(i,16)] - shift_op;
5700 WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]);
5701 cpu->R[REG_POS(i,16)] = adr;
5702
5703 return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
5704 }
5705
5706 static u32 FASTCALL OP_STRB_P_IMM_OFF_POSTIND(armcpu_t *cpu)
5707 {
5708 u32 i = cpu->instruction;
5709 u32 adr = cpu->R[REG_POS(i,16)];
5710 WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]);
5711 cpu->R[REG_POS(i,16)] = adr + IMM_OFF_12;
5712
5713 return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
5714 }
5715
5716 static u32 FASTCALL OP_STRB_M_IMM_OFF_POSTIND(armcpu_t *cpu)
5717 {
5718 u32 i = cpu->instruction;
5719 u32 adr = cpu->R[REG_POS(i,16)];
5720 WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]);
5721 cpu->R[REG_POS(i,16)] = adr - IMM_OFF_12;
5722
5723 return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
5724 }
5725
5726 static u32 FASTCALL OP_STRB_P_LSL_IMM_OFF_POSTIND(armcpu_t *cpu)
5727 {
5728 u32 i = cpu->instruction;
5729 u32 adr;
5730 u32 shift_op;
5731 LSL_IMM;
5732 adr = cpu->R[REG_POS(i,16)];
5733 WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]);
5734 cpu->R[REG_POS(i,16)] = adr + shift_op;
5735
5736 return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
5737 }
5738
5739 static u32 FASTCALL OP_STRB_M_LSL_IMM_OFF_POSTIND(armcpu_t *cpu)
5740 {
5741 u32 i = cpu->instruction;
5742 u32 adr;
5743 u32 shift_op;
5744 LSL_IMM;
5745 adr = cpu->R[REG_POS(i,16)];
5746 WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]);
5747 cpu->R[REG_POS(i,16)] = adr - shift_op;
5748
5749 return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
5750 }
5751
5752 static u32 FASTCALL OP_STRB_P_LSR_IMM_OFF_POSTIND(armcpu_t *cpu)
5753 {
5754 u32 i = cpu->instruction;
5755 u32 adr;
5756 u32 shift_op;
5757 LSR_IMM;
5758 adr = cpu->R[REG_POS(i,16)];
5759 WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]);
5760 cpu->R[REG_POS(i,16)] = adr + shift_op;
5761
5762 return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
5763 }
5764
5765 static u32 FASTCALL OP_STRB_M_LSR_IMM_OFF_POSTIND(armcpu_t *cpu)
5766 {
5767 u32 i = cpu->instruction;
5768 u32 adr;
5769 u32 shift_op;
5770 LSR_IMM;
5771 adr = cpu->R[REG_POS(i,16)];
5772 WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]);
5773 cpu->R[REG_POS(i,16)] = adr - shift_op;
5774
5775 return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
5776 }
5777
5778 static u32 FASTCALL OP_STRB_P_ASR_IMM_OFF_POSTIND(armcpu_t *cpu)
5779 {
5780 u32 i = cpu->instruction;
5781 u32 adr;
5782 u32 shift_op;
5783 ASR_IMM;
5784 adr = cpu->R[REG_POS(i,16)];
5785 WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]);
5786 cpu->R[REG_POS(i,16)] = adr + shift_op;
5787
5788 return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
5789 }
5790
5791 static u32 FASTCALL OP_STRB_M_ASR_IMM_OFF_POSTIND(armcpu_t *cpu)
5792 {
5793 u32 i = cpu->instruction;
5794 u32 adr;
5795 u32 shift_op;
5796 ASR_IMM;
5797 adr = cpu->R[REG_POS(i,16)];
5798 WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]);
5799 cpu->R[REG_POS(i,16)] = adr - shift_op;
5800
5801 return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
5802 }
5803
5804 static u32 FASTCALL OP_STRB_P_ROR_IMM_OFF_POSTIND(armcpu_t *cpu)
5805 {
5806 u32 i = cpu->instruction;
5807 u32 adr;
5808 u32 shift_op;
5809 ROR_IMM;
5810 adr = cpu->R[REG_POS(i,16)];
5811 WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]);
5812 cpu->R[REG_POS(i,16)] = adr + shift_op;
5813
5814 return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
5815 }
5816
5817 static u32 FASTCALL OP_STRB_M_ROR_IMM_OFF_POSTIND(armcpu_t *cpu)
5818 {
5819 u32 i = cpu->instruction;
5820 u32 adr;
5821 u32 shift_op;
5822 ROR_IMM;
5823 adr = cpu->R[REG_POS(i,16)];
5824 WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]);
5825 cpu->R[REG_POS(i,16)] = adr - shift_op;
5826
5827 return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
5828 }
5829
5830 //-----------------------LDRBT-------------------------------------
5831
5832 static u32 FASTCALL OP_LDRBT_P_IMM_OFF_POSTIND(armcpu_t *cpu)
5833 {
5834 u32 oldmode;
5835 u32 i;
5836 u32 adr;
5837 u32 val;
5838
5839 if(cpu->CPSR.bits.mode==USR)
5840 return 2;
5841 oldmode = armcpu_switchMode(cpu, SYS);
5842
5843 i = cpu->instruction;
5844 adr = cpu->R[REG_POS(i,16)];
5845 val = READ8(cpu->mem_if->data, adr);
5846 cpu->R[REG_POS(i,12)] = val;
5847 cpu->R[REG_POS(i,16)] = adr + IMM_OFF_12;
5848
5849 armcpu_switchMode(cpu, oldmode);
5850
5851 return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
5852 }
5853
5854 static u32 FASTCALL OP_LDRBT_M_IMM_OFF_POSTIND(armcpu_t *cpu)
5855 {
5856 u32 oldmode;
5857 u32 i;
5858 u32 adr;
5859 u32 val;
5860
5861 if(cpu->CPSR.bits.mode==USR)
5862 return 2;
5863 oldmode = armcpu_switchMode(cpu, SYS);
5864
5865 //execute = FALSE;
5866 LOG("Untested opcode: OP_LDRBT_M_IMM_OFF_POSTIND\n");
5867
5868
5869 i = cpu->instruction;
5870 adr = cpu->R[REG_POS(i,16)];
5871 val = READ8(cpu->mem_if->data, adr);
5872 cpu->R[REG_POS(i,12)] = val;
5873 cpu->R[REG_POS(i,16)] = adr - IMM_OFF_12;
5874
5875 armcpu_switchMode(cpu, oldmode);
5876
5877 return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
5878 }
5879
5880 static u32 FASTCALL OP_LDRBT_P_REG_OFF_POSTIND(armcpu_t *cpu)
5881 {
5882 u32 oldmode;
5883 u32 i;
5884 u32 adr;
5885 u32 val;
5886
5887 if(cpu->CPSR.bits.mode==USR)
5888 return 2;
5889
5890 oldmode = armcpu_switchMode(cpu, SYS);
5891 //execute = FALSE;
5892 LOG("Untested opcode: OP_LDRBT_P_REG_OFF_POSTIND");
5893
5894
5895 i = cpu->instruction;
5896 adr = cpu->R[REG_POS(i,16)];
5897 val = READ8(cpu->mem_if->data, adr);
5898 cpu->R[REG_POS(i,12)] = val;
5899 cpu->R[REG_POS(i,16)] = adr + cpu->R[REG_POS(i,0)];
5900
5901 armcpu_switchMode(cpu, oldmode);
5902
5903 return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
5904 }
5905
5906 static u32 FASTCALL OP_LDRBT_P_LSL_IMM_OFF_POSTIND(armcpu_t *cpu)
5907 {
5908 u32 oldmode;
5909 u32 i;
5910 u32 adr;
5911 u32 val;
5912 u32 shift_op;
5913
5914 if(cpu->CPSR.bits.mode==USR)
5915 return 2;
5916 oldmode = armcpu_switchMode(cpu, SYS);
5917 //execute = FALSE;
5918 LOG("Untested opcode: OP_LDRBT_P_LSL_IMM_OFF_POSTIND");
5919
5920
5921 i = cpu->instruction;
5922 LSL_IMM;
5923 adr = cpu->R[REG_POS(i,16)];
5924 val = READ8(cpu->mem_if->data, adr);
5925 cpu->R[REG_POS(i,12)] = val;
5926 cpu->R[REG_POS(i,16)] = adr + shift_op;
5927
5928 armcpu_switchMode(cpu, oldmode);
5929
5930 return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
5931 }
5932
5933 static u32 FASTCALL OP_LDRBT_M_LSL_IMM_OFF_POSTIND(armcpu_t *cpu)
5934 {
5935 u32 oldmode;
5936 u32 i;
5937 u32 adr;
5938 u32 val;
5939 u32 shift_op;
5940
5941 if(cpu->CPSR.bits.mode==USR)
5942 return 2;
5943
5944 oldmode = armcpu_switchMode(cpu, SYS);
5945 //execute = FALSE;
5946 LOG("Untested opcode: OP_LDRBT_M_LSL_IMM_OFF_POSTIND");
5947
5948
5949 i = cpu->instruction;
5950 LSL_IMM;
5951 adr = cpu->R[REG_POS(i,16)];
5952 val = READ8(cpu->mem_if->data, adr);
5953 cpu->R[REG_POS(i,12)] = val;
5954 cpu->R[REG_POS(i,16)] = adr - shift_op;
5955
5956 armcpu_switchMode(cpu, oldmode);
5957
5958 return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
5959 }
5960
5961 static u32 FASTCALL OP_LDRBT_P_LSR_IMM_OFF_POSTIND(armcpu_t *cpu)
5962 {
5963 u32 oldmode;
5964 u32 i;
5965 u32 adr;
5966 u32 val;
5967 u32 shift_op;
5968
5969 if(cpu->CPSR.bits.mode==USR)
5970 return 2;
5971
5972 oldmode = armcpu_switchMode(cpu, SYS);
5973 //execute = FALSE;
5974 LOG("Untested opcode: OP_LDRBT_P_LSR_IMM_OFF_POSTIND");
5975
5976
5977 i = cpu->instruction;
5978 LSR_IMM;
5979 adr = cpu->R[REG_POS(i,16)];
5980 val = READ8(cpu->mem_if->data, adr);
5981 cpu->R[REG_POS(i,12)] = val;
5982 cpu->R[REG_POS(i,16)] = adr + shift_op;
5983
5984 armcpu_switchMode(cpu, oldmode);
5985
5986 return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
5987 }
5988
5989 static u32 FASTCALL OP_LDRBT_M_LSR_IMM_OFF_POSTIND(armcpu_t *cpu)
5990 {
5991 u32 oldmode;
5992 u32 i;
5993 u32 adr;
5994 u32 val;
5995 u32 shift_op;
5996
5997 if(cpu->CPSR.bits.mode==USR)
5998 return 2;
5999
6000 oldmode = armcpu_switchMode(cpu, SYS);
6001 //execute = FALSE;
6002 LOG("Untested opcode: OP_LDRBT_M_LSR_IMM_OFF_POSTIND");
6003
6004
6005 i = cpu->instruction;
6006 LSR_IMM;
6007 adr = cpu->R[REG_POS(i,16)];
6008 val = READ8(cpu->mem_if->data, adr);
6009 cpu->R[REG_POS(i,12)] = val;
6010 cpu->R[REG_POS(i,16)] = adr - shift_op;
6011
6012 armcpu_switchMode(cpu, oldmode);
6013
6014 return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
6015 }
6016
6017 static u32 FASTCALL OP_LDRBT_P_ASR_IMM_OFF_POSTIND(armcpu_t *cpu)
6018 {
6019 u32 oldmode;
6020 u32 i;
6021 u32 adr;
6022 u32 val;
6023 u32 shift_op;
6024
6025 if(cpu->CPSR.bits.mode==USR)
6026 return 2;
6027
6028 oldmode = armcpu_switchMode(cpu, SYS);
6029 //execute = FALSE;
6030 LOG("Untested opcode: OP_LDRBT_P_ASR_IMM_OFF_POSTIND");
6031
6032
6033 i = cpu->instruction;
6034 ASR_IMM;
6035 adr = cpu->R[REG_POS(i,16)];
6036 val = READ8(cpu->mem_if->data, adr);
6037 cpu->R[REG_POS(i,12)] = val;
6038 cpu->R[REG_POS(i,16)] = adr + shift_op;
6039
6040 armcpu_switchMode(cpu, oldmode);
6041
6042 return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
6043 }
6044
6045 static u32 FASTCALL OP_LDRBT_M_ASR_IMM_OFF_POSTIND(armcpu_t *cpu)
6046 {
6047 u32 oldmode;
6048 u32 i;
6049 u32 adr;
6050 u32 val;
6051 u32 shift_op;
6052
6053 if(cpu->CPSR.bits.mode==USR)
6054 return 2;
6055
6056 oldmode = armcpu_switchMode(cpu, SYS);
6057 //execute = FALSE;
6058 LOG("Untested opcode: OP_LDRBT_M_ASR_IMM_OFF_POSTIND");
6059
6060
6061 i = cpu->instruction;
6062 ASR_IMM;
6063 adr = cpu->R[REG_POS(i,16)];
6064 val = READ8(cpu->mem_if->data, adr);
6065 cpu->R[REG_POS(i,12)] = val;
6066 cpu->R[REG_POS(i,16)] = adr - shift_op;
6067
6068 armcpu_switchMode(cpu, oldmode);
6069
6070 return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
6071 }
6072
6073 static u32 FASTCALL OP_LDRBT_P_ROR_IMM_OFF_POSTIND(armcpu_t *cpu)
6074 {
6075 u32 oldmode;
6076 u32 i;
6077 u32 adr;
6078 u32 val;
6079 u32 shift_op;
6080
6081 if(cpu->CPSR.bits.mode==USR)
6082 return 2;
6083
6084 oldmode = armcpu_switchMode(cpu, SYS);
6085 //execute = FALSE;
6086 LOG("Untested opcode: OP_LDRBT_P_ROR_IMM_OFF_POSTIND");
6087
6088
6089 i = cpu->instruction;
6090 ROR_IMM;
6091 adr = cpu->R[REG_POS(i,16)];
6092 val = READ8(cpu->mem_if->data, adr);
6093 cpu->R[REG_POS(i,12)] = val;
6094 cpu->R[REG_POS(i,16)] = adr + shift_op;
6095
6096 armcpu_switchMode(cpu, oldmode);
6097
6098 return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
6099 }
6100
6101 static u32 FASTCALL OP_LDRBT_M_ROR_IMM_OFF_POSTIND(armcpu_t *cpu)
6102 {
6103 u32 oldmode;
6104 u32 i;
6105 u32 adr;
6106 u32 val;
6107 u32 shift_op;
6108
6109 if(cpu->CPSR.bits.mode==USR)
6110 return 2;
6111
6112 oldmode = armcpu_switchMode(cpu, SYS);
6113 //execute = FALSE;
6114 LOG("Untested opcode: OP_LDRBT_M_ROR_IMM_OFF_POSTIND");
6115
6116
6117 i = cpu->instruction;
6118 ROR_IMM;
6119 adr = cpu->R[REG_POS(i,16)];
6120 val = READ8(cpu->mem_if->data, adr);
6121 cpu->R[REG_POS(i,12)] = val;
6122 cpu->R[REG_POS(i,16)] = adr - shift_op;
6123
6124 armcpu_switchMode(cpu, oldmode);
6125
6126 return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
6127 }
6128
6129 //----------------------STRBT----------------------------
6130
6131 static u32 FASTCALL OP_STRBT_P_IMM_OFF_POSTIND(armcpu_t *cpu)
6132 {
6133 u32 oldmode;
6134 u32 i;
6135 u32 adr;
6136
6137 if(cpu->CPSR.bits.mode==USR)
6138 return 2;
6139
6140 oldmode = armcpu_switchMode(cpu, SYS);
6141
6142
6143 i = cpu->instruction;
6144 adr = cpu->R[REG_POS(i,16)];
6145 WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]);
6146 cpu->R[REG_POS(i,16)] = adr + IMM_OFF_12;
6147
6148 armcpu_switchMode(cpu, oldmode);
6149
6150 return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
6151 }
6152
6153 static u32 FASTCALL OP_STRBT_M_IMM_OFF_POSTIND(armcpu_t *cpu)
6154 {
6155 u32 oldmode;
6156 u32 i;
6157 u32 adr;
6158
6159 if(cpu->CPSR.bits.mode==USR)
6160 return 2;
6161
6162 oldmode = armcpu_switchMode(cpu, SYS);
6163
6164
6165 i = cpu->instruction;
6166 adr = cpu->R[REG_POS(i,16)];
6167 WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]);
6168 cpu->R[REG_POS(i,16)] = adr - IMM_OFF_12;
6169
6170 armcpu_switchMode(cpu, oldmode);
6171
6172 return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
6173 }
6174
6175 static u32 FASTCALL OP_STRBT_P_REG_OFF_POSTIND(armcpu_t *cpu)
6176 {
6177 u32 oldmode;
6178 u32 i;
6179 u32 adr;
6180
6181 if(cpu->CPSR.bits.mode==USR)
6182 return 2;
6183
6184 oldmode = armcpu_switchMode(cpu, SYS);
6185
6186
6187 i = cpu->instruction;
6188 adr = cpu->R[REG_POS(i,16)];
6189 WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]);
6190 cpu->R[REG_POS(i,16)] = adr + cpu->R[REG_POS(i,0)];
6191
6192 armcpu_switchMode(cpu, oldmode);
6193
6194 return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
6195 }
6196
6197 static u32 FASTCALL OP_STRBT_M_REG_OFF_POSTIND(armcpu_t *cpu)
6198 {
6199 u32 oldmode;
6200 u32 i;
6201 u32 adr;
6202
6203 if(cpu->CPSR.bits.mode==USR)
6204 return 2;
6205
6206 oldmode = armcpu_switchMode(cpu, SYS);
6207
6208
6209 i = cpu->instruction;
6210 adr = cpu->R[REG_POS(i,16)];
6211 WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]);
6212 cpu->R[REG_POS(i,16)] = adr - cpu->R[REG_POS(i,0)];
6213
6214 armcpu_switchMode(cpu, oldmode);
6215
6216 return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
6217 }
6218
6219 static u32 FASTCALL OP_STRBT_P_LSL_IMM_OFF_POSTIND(armcpu_t *cpu)
6220 {
6221 u32 oldmode;
6222 u32 i;
6223 u32 adr;
6224 u32 shift_op;
6225
6226 if(cpu->CPSR.bits.mode==USR)
6227 return 2;
6228
6229 oldmode = armcpu_switchMode(cpu, SYS);
6230
6231
6232 i = cpu->instruction;
6233 LSL_IMM;
6234 adr = cpu->R[REG_POS(i,16)];
6235 WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]);
6236 cpu->R[REG_POS(i,16)] = adr + shift_op;
6237
6238 armcpu_switchMode(cpu, oldmode);
6239
6240 return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
6241 }
6242
6243 static u32 FASTCALL OP_STRBT_M_LSL_IMM_OFF_POSTIND(armcpu_t *cpu)
6244 {
6245 u32 oldmode;
6246 u32 i;
6247 u32 adr;
6248 u32 shift_op;
6249
6250 if(cpu->CPSR.bits.mode==USR)
6251 return 2;
6252
6253 oldmode = armcpu_switchMode(cpu, SYS);
6254
6255
6256 i = cpu->instruction;
6257 LSL_IMM;
6258 adr = cpu->R[REG_POS(i,16)];
6259 WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]);
6260 cpu->R[REG_POS(i,16)] = adr - shift_op;
6261
6262 armcpu_switchMode(cpu, oldmode);
6263
6264 return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
6265 }
6266
6267 static u32 FASTCALL OP_STRBT_P_LSR_IMM_OFF_POSTIND(armcpu_t *cpu)
6268 {
6269 u32 oldmode;
6270 u32 i;
6271 u32 adr;
6272 u32 shift_op;
6273
6274 if(cpu->CPSR.bits.mode==USR)
6275 return 2;
6276
6277 oldmode = armcpu_switchMode(cpu, SYS);
6278
6279
6280 i = cpu->instruction;
6281 LSR_IMM;
6282 adr = cpu->R[REG_POS(i,16)];
6283 WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]);
6284 cpu->R[REG_POS(i,16)] = adr + shift_op;
6285
6286 armcpu_switchMode(cpu, oldmode);
6287
6288 return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
6289 }
6290
6291 static u32 FASTCALL OP_STRBT_M_LSR_IMM_OFF_POSTIND(armcpu_t *cpu)
6292 {
6293 u32 oldmode;
6294 u32 i;
6295 u32 adr;
6296 u32 shift_op;
6297
6298 if(cpu->CPSR.bits.mode==USR)
6299 return 2;
6300
6301 oldmode = armcpu_switchMode(cpu, SYS);
6302
6303
6304 i = cpu->instruction;
6305 LSR_IMM;
6306 adr = cpu->R[REG_POS(i,16)];
6307 WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]);
6308 cpu->R[REG_POS(i,16)] = adr - shift_op;
6309
6310 armcpu_switchMode(cpu, oldmode);
6311
6312 return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
6313 }
6314
6315 static u32 FASTCALL OP_STRBT_P_ASR_IMM_OFF_POSTIND(armcpu_t *cpu)
6316 {
6317 u32 oldmode;
6318 u32 i;
6319 u32 adr;
6320 u32 shift_op;
6321
6322 if(cpu->CPSR.bits.mode==USR)
6323 return 2;
6324
6325 oldmode = armcpu_switchMode(cpu, SYS);
6326
6327
6328 i = cpu->instruction;
6329 ASR_IMM;
6330 adr = cpu->R[REG_POS(i,16)];
6331 WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]);
6332 cpu->R[REG_POS(i,16)] = adr + shift_op;
6333
6334 armcpu_switchMode(cpu, oldmode);
6335
6336 return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
6337 }
6338
6339 static u32 FASTCALL OP_STRBT_M_ASR_IMM_OFF_POSTIND(armcpu_t *cpu)
6340 {
6341 u32 oldmode;
6342 u32 i;
6343 u32 adr;
6344 u32 shift_op;
6345
6346 if(cpu->CPSR.bits.mode==USR)
6347 return 2;
6348
6349 oldmode = armcpu_switchMode(cpu, SYS);
6350
6351
6352 i = cpu->instruction;
6353 ASR_IMM;
6354 adr = cpu->R[REG_POS(i,16)];
6355 WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]);
6356 cpu->R[REG_POS(i,16)] = adr - shift_op;
6357
6358 armcpu_switchMode(cpu, oldmode);
6359
6360 return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
6361 }
6362
6363 static u32 FASTCALL OP_STRBT_P_ROR_IMM_OFF_POSTIND(armcpu_t *cpu)
6364 {
6365 u32 oldmode;
6366 u32 i;
6367 u32 adr;
6368 u32 shift_op;
6369
6370 if(cpu->CPSR.bits.mode==USR)
6371 return 2;
6372
6373 oldmode = armcpu_switchMode(cpu, SYS);
6374
6375
6376 i = cpu->instruction;
6377 ROR_IMM;
6378 adr = cpu->R[REG_POS(i,16)];
6379 WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]);
6380 cpu->R[REG_POS(i,16)] = adr + shift_op;
6381
6382 armcpu_switchMode(cpu, oldmode);
6383
6384 return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
6385 }
6386
6387 static u32 FASTCALL OP_STRBT_M_ROR_IMM_OFF_POSTIND(armcpu_t *cpu)
6388 {
6389 u32 oldmode;
6390 u32 i;
6391 u32 adr;
6392 u32 shift_op;
6393
6394 if(cpu->CPSR.bits.mode==USR)
6395 return 2;
6396
6397 oldmode = armcpu_switchMode(cpu, SYS);
6398
6399
6400 i = cpu->instruction;
6401 ROR_IMM;
6402 adr = cpu->R[REG_POS(i,16)];
6403 WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]);
6404 cpu->R[REG_POS(i,16)] = adr - shift_op;
6405
6406 armcpu_switchMode(cpu, oldmode);
6407
6408 return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
6409 }
6410
6411 //---------------------LDM-----------------------------
6412
6413 #define OP_L_IA(reg, adr) if(BIT##reg(i))\
6414 {\
6415 registres[reg] = READ32(cpu->mem_if->data, start);\
6416 c += waitState[(start>>24)&0xF];\
6417 adr += 4;\
6418 }
6419
6420 #define OP_L_IB(reg, adr) if(BIT##reg(i))\
6421 {\
6422 adr += 4;\
6423 registres[reg] = READ32(cpu->mem_if->data, start);\
6424 c += waitState[(start>>24)&0xF];\
6425 }
6426
6427 #define OP_L_DA(reg, adr) if(BIT##reg(i))\
6428 {\
6429 registres[reg] = READ32(cpu->mem_if->data, start);\
6430 c += waitState[(start>>24)&0xF];\
6431 adr -= 4;\
6432 }
6433
6434 #define OP_L_DB(reg, adr) if(BIT##reg(i))\
6435 {\
6436 adr -= 4;\
6437 registres[reg] = READ32(cpu->mem_if->data, start);\
6438 c += waitState[(start>>24)&0xF];\
6439 }
6440
6441 static u32 FASTCALL OP_LDMIA(armcpu_t *cpu)
6442 {
6443 u32 i = cpu->instruction;
6444 u32 c = 0;
6445 u32 start = cpu->R[REG_POS(i,16)];
6446
6447 u32 * registres = cpu->R;
6448 u32 * waitState = MMU.MMU_WAIT32[cpu->proc_ID];
6449
6450 OP_L_IA(0, start);
6451 OP_L_IA(1, start);
6452 OP_L_IA(2, start);
6453 OP_L_IA(3, start);
6454 OP_L_IA(4, start);
6455 OP_L_IA(5, start);
6456 OP_L_IA(6, start);
6457 OP_L_IA(7, start);
6458 OP_L_IA(8, start);
6459 OP_L_IA(9, start);
6460 OP_L_IA(10, start);
6461 OP_L_IA(11, start);
6462 OP_L_IA(12, start);
6463 OP_L_IA(13, start);
6464 OP_L_IA(14, start);
6465
6466 if(BIT15(i))
6467 {
6468 u32 tmp = READ32(cpu->mem_if->data, start);
6469 registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1));
6470 cpu->CPSR.bits.T = BIT0(tmp);
6471 //start += 4;
6472 cpu->next_instruction = registres[15];
6473 c += waitState[(start>>24)&0xF];
6474 }
6475
6476 return c + 2;
6477 }
6478
6479 static u32 FASTCALL OP_LDMIB(armcpu_t *cpu)
6480 {
6481 u32 i = cpu->instruction;
6482 u32 c = 0;
6483 u32 start = cpu->R[REG_POS(i,16)];
6484
6485 u32 * registres = cpu->R;
6486 u32 * waitState = MMU.MMU_WAIT32[cpu->proc_ID];
6487
6488 OP_L_IB(0, start);
6489 OP_L_IB(1, start);
6490 OP_L_IB(2, start);
6491 OP_L_IB(3, start);
6492 OP_L_IB(4, start);
6493 OP_L_IB(5, start);
6494 OP_L_IB(6, start);
6495 OP_L_IB(7, start);
6496 OP_L_IB(8, start);
6497 OP_L_IB(9, start);
6498 OP_L_IB(10, start);
6499 OP_L_IB(11, start);
6500 OP_L_IB(12, start);
6501 OP_L_IB(13, start);
6502 OP_L_IB(14, start);
6503
6504 if(BIT15(i))
6505 {
6506 u32 tmp;
6507 start += 4;
6508 c += waitState[(start>>24)&0xF];
6509 tmp = READ32(cpu->mem_if->data, start);
6510 registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1));
6511 cpu->CPSR.bits.T = BIT0(tmp);
6512 cpu->next_instruction = registres[15];
6513 c += 2 + (c==0);
6514 }
6515
6516 return c + 2;
6517 }
6518
6519 static u32 FASTCALL OP_LDMDA(armcpu_t *cpu)
6520 {
6521 u32 i = cpu->instruction;
6522 u32 c = 0;
6523 u32 start = cpu->R[REG_POS(i,16)];
6524
6525 u32 * registres = cpu->R;
6526 u32 * waitState = MMU.MMU_WAIT32[cpu->proc_ID];
6527
6528 if(BIT15(i))
6529 {
6530 u32 tmp = READ32(cpu->mem_if->data, start);
6531 registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1));
6532 cpu->CPSR.bits.T = BIT0(tmp);
6533 c += waitState[(start>>24)&0xF];
6534 start -= 4;
6535 cpu->next_instruction = registres[15];
6536 }
6537
6538 OP_L_DA(14, start);
6539 OP_L_DA(13, start);
6540 OP_L_DA(12, start);
6541 OP_L_DA(11, start);
6542 OP_L_DA(10, start);
6543 OP_L_DA(9, start);
6544 OP_L_DA(8, start);
6545 OP_L_DA(7, start);
6546 OP_L_DA(6, start);
6547 OP_L_DA(5, start);
6548 OP_L_DA(4, start);
6549 OP_L_DA(3, start);
6550 OP_L_DA(2, start);
6551 OP_L_DA(1, start);
6552 OP_L_DA(0, start);
6553
6554 return c + 2;
6555 }
6556
6557 static u32 FASTCALL OP_LDMDB(armcpu_t *cpu)
6558 {
6559 u32 i = cpu->instruction;
6560 u32 c = 0;
6561 u32 start = cpu->R[REG_POS(i,16)];
6562
6563 u32 * registres = cpu->R;
6564 u32 * waitState = MMU.MMU_WAIT32[cpu->proc_ID];
6565
6566 if(BIT15(i))
6567 {
6568 u32 tmp;
6569 start -= 4;
6570 tmp = READ32(cpu->mem_if->data, start);
6571 registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1));
6572 cpu->CPSR.bits.T = BIT0(tmp);
6573 cpu->next_instruction = registres[15];
6574 c += waitState[(start>>24)&0xF];
6575 }
6576
6577 OP_L_DB(14, start);
6578 OP_L_DB(13, start);
6579 OP_L_DB(12, start);
6580 OP_L_DB(11, start);
6581 OP_L_DB(10, start);
6582 OP_L_DB(9, start);
6583 OP_L_DB(8, start);
6584 OP_L_DB(7, start);
6585 OP_L_DB(6, start);
6586 OP_L_DB(5, start);
6587 OP_L_DB(4, start);
6588 OP_L_DB(3, start);
6589 OP_L_DB(2, start);
6590 OP_L_DB(1, start);
6591 OP_L_DB(0, start);
6592
6593 return c + 2;
6594 }
6595
6596 static u32 FASTCALL OP_LDMIA_W(armcpu_t *cpu)
6597 {
6598 u32 i = cpu->instruction, c = 0, count;
6599 u32 start = cpu->R[REG_POS(i,16)];
6600 u32 bitList = (~((2 << REG_POS(i,16))-1)) & 0xFFFF;
6601
6602 u32 * registres = cpu->R;
6603 u32 * waitState = MMU.MMU_WAIT32[cpu->proc_ID];
6604
6605 OP_L_IA(0, start);
6606 OP_L_IA(1, start);
6607 OP_L_IA(2, start);
6608 OP_L_IA(3, start);
6609 OP_L_IA(4, start);
6610 OP_L_IA(5, start);
6611 OP_L_IA(6, start);
6612 OP_L_IA(7, start);
6613 OP_L_IA(8, start);
6614 OP_L_IA(9, start);
6615 OP_L_IA(10, start);
6616 OP_L_IA(11, start);
6617 OP_L_IA(12, start);
6618 OP_L_IA(13, start);
6619 OP_L_IA(14, start);
6620
6621 if(BIT15(i))
6622 {
6623 u32 tmp = READ32(cpu->mem_if->data, start);
6624 registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1));
6625 cpu->CPSR.bits.T = BIT0(tmp);
6626 c += waitState[(start>>24)&0xF];
6627 start += 4;
6628 cpu->next_instruction = registres[15];
6629 }
6630
6631 if(i & (1 << REG_POS(i,16))) {
6632 if(i & bitList)
6633 cpu->R[REG_POS(i,16)] = start;
6634 }
6635 else
6636 cpu->R[REG_POS(i,16)] = start;
6637
6638 return c + 2;
6639 }
6640
6641 static u32 FASTCALL OP_LDMIB_W(armcpu_t *cpu)
6642 {
6643 u32 i = cpu->instruction, c = 0, count;
6644 u32 start = cpu->R[REG_POS(i,16)];
6645 u32 bitList = (~((2 << REG_POS(i,16))-1)) & 0xFFFF;
6646
6647 u32 * registres = cpu->R;
6648 u32 * waitState = MMU.MMU_WAIT32[cpu->proc_ID];
6649
6650 OP_L_IB(0, start);
6651 OP_L_IB(1, start);
6652 OP_L_IB(2, start);
6653 OP_L_IB(3, start);
6654 OP_L_IB(4, start);
6655 OP_L_IB(5, start);
6656 OP_L_IB(6, start);
6657 OP_L_IB(7, start);
6658 OP_L_IB(8, start);
6659 OP_L_IB(9, start);
6660 OP_L_IB(10, start);
6661 OP_L_IB(11, start);
6662 OP_L_IB(12, start);
6663 OP_L_IB(13, start);
6664 OP_L_IB(14, start);
6665
6666 if(BIT15(i))
6667 {
6668 u32 tmp;
6669 start += 4;
6670 c += waitState[(start>>24)&0xF];
6671 tmp = READ32(cpu->mem_if->data, start);
6672 registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1));
6673 cpu->CPSR.bits.T = BIT0(tmp);
6674 cpu->next_instruction = registres[15];
6675 c += 2 + (c==0);
6676 }
6677
6678 if(i & (1 << REG_POS(i,16))) {
6679 if(i & bitList)
6680 cpu->R[REG_POS(i,16)] = start;
6681 }
6682 else
6683 cpu->R[REG_POS(i,16)] = start;
6684
6685 return c + 2;
6686 }
6687
6688 static u32 FASTCALL OP_LDMDA_W(armcpu_t *cpu)
6689 {
6690 u32 i = cpu->instruction, c = 0, count;
6691 u32 start = cpu->R[REG_POS(i,16)];
6692 u32 bitList = (~((2 << REG_POS(i,16))-1)) & 0xFFFF;
6693
6694 u32 * registres = cpu->R;
6695 u32 * waitState = MMU.MMU_WAIT32[cpu->proc_ID];
6696
6697 if(BIT15(i))
6698 {
6699 u32 tmp = READ32(cpu->mem_if->data, start);
6700 registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1));
6701 cpu->CPSR.bits.T = BIT0(tmp);
6702 c += waitState[(start>>24)&0xF];
6703 start -= 4;
6704 cpu->next_instruction = registres[15];
6705 }
6706
6707 OP_L_DA(14, start);
6708 OP_L_DA(13, start);
6709 OP_L_DA(12, start);
6710 OP_L_DA(11, start);
6711 OP_L_DA(10, start);
6712 OP_L_DA(9, start);
6713 OP_L_DA(8, start);
6714 OP_L_DA(7, start);
6715 OP_L_DA(6, start);
6716 OP_L_DA(5, start);
6717 OP_L_DA(4, start);
6718 OP_L_DA(3, start);
6719 OP_L_DA(2, start);
6720 OP_L_DA(1, start);
6721 OP_L_DA(0, start);
6722
6723 if(i & (1 << REG_POS(i,16))) {
6724 if(i & bitList)
6725 cpu->R[REG_POS(i,16)] = start;
6726 }
6727 else
6728 cpu->R[REG_POS(i,16)] = start;
6729
6730 return c + 2;
6731 }
6732
6733 static u32 FASTCALL OP_LDMDB_W(armcpu_t *cpu)
6734 {
6735 u32 i = cpu->instruction, c = 0, count;
6736 u32 start = cpu->R[REG_POS(i,16)];
6737 u32 bitList = (~((2 << REG_POS(i,16))-1)) & 0xFFFF;
6738 u32 * registres = cpu->R;
6739 u32 * waitState = MMU.MMU_WAIT32[cpu->proc_ID];
6740
6741 if(BIT15(i))
6742 {
6743 u32 tmp;
6744 start -= 4;
6745 tmp = READ32(cpu->mem_if->data, start);
6746 registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1));
6747 cpu->CPSR.bits.T = BIT0(tmp);
6748 cpu->next_instruction = registres[15];
6749 c += waitState[(start>>24)&0xF];
6750 }
6751
6752 OP_L_DB(14, start);
6753 OP_L_DB(13, start);
6754 OP_L_DB(12, start);
6755 OP_L_DB(11, start);
6756 OP_L_DB(10, start);
6757 OP_L_DB(9, start);
6758 OP_L_DB(8, start);
6759 OP_L_DB(7, start);
6760 OP_L_DB(6, start);
6761 OP_L_DB(5, start);
6762 OP_L_DB(4, start);
6763 OP_L_DB(3, start);
6764 OP_L_DB(2, start);
6765 OP_L_DB(1, start);
6766 OP_L_DB(0, start);
6767
6768 if(i & (1 << REG_POS(i,16))) {
6769 if(i & bitList)
6770 cpu->R[REG_POS(i,16)] = start;
6771 }
6772 else
6773 cpu->R[REG_POS(i,16)] = start;
6774
6775 return c + 2;
6776 }
6777
6778 static u32 FASTCALL OP_LDMIA2(armcpu_t *cpu)
6779 {
6780 u32 i = cpu->instruction;
6781 u32 oldmode;
6782
6783 u32 c = 0;
6784
6785 u32 start = cpu->R[REG_POS(i,16)];
6786 u32 * registres;
6787 u32 * waitState;
6788
6789 if(BIT15(i)==0)
6790 {
6791 if(cpu->CPSR.bits.mode==USR)
6792 return 1;
6793 oldmode = armcpu_switchMode(cpu, SYS);
6794 }
6795
6796 registres = cpu->R;
6797 waitState = MMU.MMU_WAIT32[cpu->proc_ID];
6798
6799 OP_L_IA(0, start);
6800 OP_L_IA(1, start);
6801 OP_L_IA(2, start);
6802 OP_L_IA(3, start);
6803 OP_L_IA(4, start);
6804 OP_L_IA(5, start);
6805 OP_L_IA(6, start);
6806 OP_L_IA(7, start);
6807 OP_L_IA(8, start);
6808 OP_L_IA(9, start);
6809 OP_L_IA(10, start);
6810 OP_L_IA(11, start);
6811 OP_L_IA(12, start);
6812 OP_L_IA(13, start);
6813 OP_L_IA(14, start);
6814
6815 if(BIT15(i))
6816 {
6817 u32 tmp = READ32(cpu->mem_if->data, start);
6818 Status_Reg SPSR;
6819 cpu->R[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1));
6820 SPSR = cpu->SPSR;
6821 armcpu_switchMode(cpu, SPSR.bits.mode);
6822 cpu->CPSR=SPSR;
6823 //start += 4;
6824 cpu->next_instruction = cpu->R[15];
6825 c += MMU.MMU_WAIT32[cpu->proc_ID][(start>>24)&0xF];
6826 }
6827 else
6828 {
6829 armcpu_switchMode(cpu, oldmode);
6830 }
6831 return c + 2;
6832 }
6833
6834 static u32 FASTCALL OP_LDMIB2(armcpu_t *cpu)
6835 {
6836 u32 i = cpu->instruction;
6837 u32 oldmode;
6838 u32 c = 0;
6839
6840 u32 start = cpu->R[REG_POS(i,16)];
6841 u32 * registres;
6842 u32 * waitState;
6843 //execute = FALSE;
6844 LOG("Untested opcode: OP_LDMIB2");
6845
6846 if(BIT15(i)==0)
6847 {
6848 if(cpu->CPSR.bits.mode==USR)
6849 return 2;
6850 oldmode = armcpu_switchMode(cpu, SYS);
6851 }
6852
6853 registres = cpu->R;
6854 waitState = MMU.MMU_WAIT32[cpu->proc_ID];
6855
6856 OP_L_IB(0, start);
6857 OP_L_IB(1, start);
6858 OP_L_IB(2, start);
6859 OP_L_IB(3, start);
6860 OP_L_IB(4, start);
6861 OP_L_IB(5, start);
6862 OP_L_IB(6, start);
6863 OP_L_IB(7, start);
6864 OP_L_IB(8, start);
6865 OP_L_IB(9, start);
6866 OP_L_IB(10, start);
6867 OP_L_IB(11, start);
6868 OP_L_IB(12, start);
6869 OP_L_IB(13, start);
6870 OP_L_IB(14, start);
6871
6872 if(BIT15(i))
6873 {
6874 u32 tmp;
6875 Status_Reg SPSR;
6876 start += 4;
6877 tmp = READ32(cpu->mem_if->data, start);
6878 registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1));
6879 SPSR = cpu->SPSR;
6880 armcpu_switchMode(cpu, SPSR.bits.mode);
6881 cpu->CPSR=SPSR;
6882 cpu->next_instruction = registres[15];
6883 c += waitState[(start>>24)&0xF];
6884 }
6885 else
6886 {
6887 armcpu_switchMode(cpu, oldmode);
6888 }
6889 return c + 2;
6890 }
6891
6892 static u32 FASTCALL OP_LDMDA2(armcpu_t *cpu)
6893 {
6894 u32 i = cpu->instruction;
6895
6896 u32 oldmode;
6897 u32 c = 0;
6898 u32 * registres;
6899 u32 * waitState;
6900
6901 u32 start = cpu->R[REG_POS(i,16)];
6902 //execute = FALSE;
6903 LOG("Untested opcode: OP_LDMDA2");
6904
6905 if(BIT15(i)==0)
6906 {
6907 if(cpu->CPSR.bits.mode==USR)
6908 return 2;
6909 oldmode = armcpu_switchMode(cpu, SYS);
6910 }
6911
6912 registres = cpu->R;
6913 waitState = MMU.MMU_WAIT32[cpu->proc_ID];
6914
6915 if(BIT15(i))
6916 {
6917 u32 tmp = READ32(cpu->mem_if->data, start);
6918 registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1));
6919 cpu->CPSR = cpu->SPSR;
6920 c += waitState[(start>>24)&0xF];
6921 start -= 4;
6922 cpu->next_instruction = registres[15];
6923 }
6924
6925 OP_L_DA(14, start);
6926 OP_L_DA(13, start);
6927 OP_L_DA(12, start);
6928 OP_L_DA(11, start);
6929 OP_L_DA(10, start);
6930 OP_L_DA(9, start);
6931 OP_L_DA(8, start);
6932 OP_L_DA(7, start);
6933 OP_L_DA(6, start);
6934 OP_L_DA(5, start);
6935 OP_L_DA(4, start);
6936 OP_L_DA(3, start);
6937 OP_L_DA(2, start);
6938 OP_L_DA(1, start);
6939 OP_L_DA(0, start);
6940
6941 if(BIT15(i)==0)
6942 {
6943 armcpu_switchMode(cpu, oldmode);
6944 }
6945 else
6946 {
6947 Status_Reg SPSR = cpu->SPSR;
6948 armcpu_switchMode(cpu, SPSR.bits.mode);
6949 cpu->CPSR=SPSR;
6950 }
6951
6952 return c + 2;
6953 }
6954
6955 static u32 FASTCALL OP_LDMDB2(armcpu_t *cpu)
6956 {
6957 u32 i = cpu->instruction;
6958
6959 u32 oldmode;
6960 u32 c = 0;
6961 u32 * registres;
6962 u32 * waitState;
6963
6964 u32 start = cpu->R[REG_POS(i,16)];
6965 if(BIT15(i)==0)
6966 {
6967 if(cpu->CPSR.bits.mode==USR)
6968 return 2;
6969 oldmode = armcpu_switchMode(cpu, SYS);
6970 }
6971
6972 registres = cpu->R;
6973 waitState = MMU.MMU_WAIT32[cpu->proc_ID];
6974
6975 if(BIT15(i))
6976 {
6977 u32 tmp;
6978 start -= 4;
6979 tmp = READ32(cpu->mem_if->data, start);
6980 registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1));
6981 cpu->CPSR = cpu->SPSR;
6982 cpu->next_instruction = registres[15];
6983 c += waitState[(start>>24)&0xF];
6984 }
6985
6986 OP_L_DB(14, start);
6987 OP_L_DB(13, start);
6988 OP_L_DB(12, start);
6989 OP_L_DB(11, start);
6990 OP_L_DB(10, start);
6991 OP_L_DB(9, start);
6992 OP_L_DB(8, start);
6993 OP_L_DB(7, start);
6994 OP_L_DB(6, start);
6995 OP_L_DB(5, start);
6996 OP_L_DB(4, start);
6997 OP_L_DB(3, start);
6998 OP_L_DB(2, start);
6999 OP_L_DB(1, start);
7000 OP_L_DB(0, start);
7001
7002 if(BIT15(i)==0)
7003 {
7004 armcpu_switchMode(cpu, oldmode);
7005 }
7006 else
7007 {
7008 Status_Reg SPSR = cpu->SPSR;
7009 armcpu_switchMode(cpu, SPSR.bits.mode);
7010 cpu->CPSR=SPSR;
7011 }
7012
7013 return 2 + c;
7014 }
7015
7016 static u32 FASTCALL OP_LDMIA2_W(armcpu_t *cpu)
7017 {
7018 u32 i = cpu->instruction;
7019 u32 c = 0;
7020
7021 u32 oldmode;
7022 u32 start = cpu->R[REG_POS(i,16)];
7023 u32 * registres;
7024 u32 * waitState;
7025 u32 tmp;
7026 Status_Reg SPSR;
7027 // execute = FALSE;
7028 if(BIT15(i)==0)
7029 {
7030 if(cpu->CPSR.bits.mode==USR)
7031 return 2;
7032 oldmode = armcpu_switchMode(cpu, SYS);
7033 }
7034
7035 registres = cpu->R;
7036 waitState = MMU.MMU_WAIT32[cpu->proc_ID];
7037
7038 OP_L_IA(0, start);
7039 OP_L_IA(1, start);
7040 OP_L_IA(2, start);
7041 OP_L_IA(3, start);
7042 OP_L_IA(4, start);
7043 OP_L_IA(5, start);
7044 OP_L_IA(6, start);
7045 OP_L_IA(7, start);
7046 OP_L_IA(8, start);
7047 OP_L_IA(9, start);
7048 OP_L_IA(10, start);
7049 OP_L_IA(11, start);
7050 OP_L_IA(12, start);
7051 OP_L_IA(13, start);
7052 OP_L_IA(14, start);
7053
7054 if(BIT15(i)==0)
7055 {
7056 registres[REG_POS(i,16)] = start;
7057 armcpu_switchMode(cpu, oldmode);
7058 return c + 2;
7059 }
7060
7061 registres[REG_POS(i,16)] = start + 4;
7062 tmp = READ32(cpu->mem_if->data, start);
7063 registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1));
7064 SPSR = cpu->SPSR;
7065 armcpu_switchMode(cpu, SPSR.bits.mode);
7066 cpu->CPSR=SPSR;
7067 cpu->next_instruction = registres[15];
7068 c += waitState[(start>>24)&0xF];
7069
7070 return c + 2;
7071 }
7072
7073 static u32 FASTCALL OP_LDMIB2_W(armcpu_t *cpu)
7074 {
7075 u32 i = cpu->instruction;
7076 u32 c = 0;
7077
7078 u32 oldmode;
7079 u32 start = cpu->R[REG_POS(i,16)];
7080 u32 * registres;
7081 u32 * waitState;
7082 u32 tmp;
7083 Status_Reg SPSR;
7084
7085 if(BIT15(i)==0)
7086 {
7087 if(cpu->CPSR.bits.mode==USR)
7088 return 2;
7089 oldmode = armcpu_switchMode(cpu, SYS);
7090 }
7091
7092 registres = cpu->R;
7093 waitState = MMU.MMU_WAIT32[cpu->proc_ID];
7094
7095 OP_L_IB(0, start);
7096 OP_L_IB(1, start);
7097 OP_L_IB(2, start);
7098 OP_L_IB(3, start);
7099 OP_L_IB(4, start);
7100 OP_L_IB(5, start);
7101 OP_L_IB(6, start);
7102 OP_L_IB(7, start);
7103 OP_L_IB(8, start);
7104 OP_L_IB(9, start);
7105 OP_L_IB(10, start);
7106 OP_L_IB(11, start);
7107 OP_L_IB(12, start);
7108 OP_L_IB(13, start);
7109 OP_L_IB(14, start);
7110
7111 if(BIT15(i)==0)
7112 {
7113 armcpu_switchMode(cpu, oldmode);
7114 registres[REG_POS(i,16)] = start;
7115
7116 return c + 2;
7117 }
7118
7119 registres[REG_POS(i,16)] = start + 4;
7120 tmp = READ32(cpu->mem_if->data, start + 4);
7121 registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1));
7122 cpu->CPSR = cpu->SPSR;
7123 cpu->next_instruction = registres[15];
7124 SPSR = cpu->SPSR;
7125 armcpu_switchMode(cpu, SPSR.bits.mode);
7126 cpu->CPSR=SPSR;
7127 c += waitState[(start>>24)&0xF];
7128
7129 return c + 2;
7130 }
7131
7132 static u32 FASTCALL OP_LDMDA2_W(armcpu_t *cpu)
7133 {
7134 u32 i = cpu->instruction;
7135 u32 c = 0;
7136
7137 u32 oldmode;
7138 u32 start = cpu->R[REG_POS(i,16)];
7139 u32 * registres;
7140 u32 * waitState;
7141 Status_Reg SPSR;
7142 // execute = FALSE;
7143 if(BIT15(i)==0)
7144 {
7145 if(cpu->CPSR.bits.mode==USR)
7146 return 2;
7147 oldmode = armcpu_switchMode(cpu, SYS);
7148 }
7149
7150 registres = cpu->R;
7151 waitState = MMU.MMU_WAIT32[cpu->proc_ID];
7152
7153 if(BIT15(i))
7154 {
7155 u32 tmp = READ32(cpu->mem_if->data, start);
7156 registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1));
7157 c += waitState[(start>>24)&0xF];
7158 start -= 4;
7159 cpu->next_instruction = registres[15];
7160 }
7161
7162 OP_L_DA(14, start);
7163 OP_L_DA(13, start);
7164 OP_L_DA(12, start);
7165 OP_L_DA(11, start);
7166 OP_L_DA(10, start);
7167 OP_L_DA(9, start);
7168 OP_L_DA(8, start);
7169 OP_L_DA(7, start);
7170 OP_L_DA(6, start);
7171 OP_L_DA(5, start);
7172 OP_L_DA(4, start);
7173 OP_L_DA(3, start);
7174 OP_L_DA(2, start);
7175 OP_L_DA(1, start);
7176 OP_L_DA(0, start);
7177
7178 registres[REG_POS(i,16)] = start;
7179
7180 if(BIT15(i)==0)
7181 {
7182 armcpu_switchMode(cpu, oldmode);
7183 return c + 2;
7184 }
7185
7186 SPSR = cpu->SPSR;
7187 armcpu_switchMode(cpu, SPSR.bits.mode);
7188 cpu->CPSR=SPSR;
7189 return c + 2;
7190 }
7191
7192 static u32 FASTCALL OP_LDMDB2_W(armcpu_t *cpu)
7193 {
7194 u32 i = cpu->instruction;
7195 u32 c = 0;
7196
7197 u32 oldmode;
7198 u32 start = cpu->R[REG_POS(i,16)];
7199 u32 * registres;
7200 u32 * waitState;
7201 Status_Reg SPSR;
7202 // execute = FALSE;
7203 if(BIT15(i)==0)
7204 {
7205 if(cpu->CPSR.bits.mode==USR)
7206 return 2;
7207 oldmode = armcpu_switchMode(cpu, SYS);
7208 }
7209
7210 registres = cpu->R;
7211 waitState = MMU.MMU_WAIT32[cpu->proc_ID];
7212
7213 if(BIT15(i))
7214 {
7215 u32 tmp;
7216 start -= 4;
7217 tmp = READ32(cpu->mem_if->data, start);
7218 c += waitState[(start>>24)&0xF];
7219 registres[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1));
7220 cpu->CPSR = cpu->SPSR;
7221 cpu->next_instruction = registres[15];
7222 }
7223
7224 OP_L_DB(14, start);
7225 OP_L_DB(13, start);
7226 OP_L_DB(12, start);
7227 OP_L_DB(11, start);
7228 OP_L_DB(10, start);
7229 OP_L_DB(9, start);
7230 OP_L_DB(8, start);
7231 OP_L_DB(7, start);
7232 OP_L_DB(6, start);
7233 OP_L_DB(5, start);
7234 OP_L_DB(4, start);
7235 OP_L_DB(3, start);
7236 OP_L_DB(2, start);
7237 OP_L_DB(1, start);
7238 OP_L_DB(0, start);
7239
7240 registres[REG_POS(i,16)] = start;
7241
7242 if(BIT15(i)==0)
7243 {
7244 armcpu_switchMode(cpu, oldmode);
7245 return c + 2;
7246 }
7247
7248 SPSR = cpu->SPSR;
7249 armcpu_switchMode(cpu, SPSR.bits.mode);
7250 cpu->CPSR=SPSR;
7251 return c + 2;
7252 }
7253
7254 //------------------------------STM----------------------------------
7255
7256 static u32 FASTCALL OP_STMIA(armcpu_t *cpu)
7257 {
7258 u32 i = cpu->instruction, c = 0, b;
7259 u32 start = cpu->R[REG_POS(i,16)];
7260
7261 for(b=0; b<16; ++b)
7262 {
7263 if(BIT_N(i, b))
7264 {
7265 WRITE32(cpu->mem_if->data, start, cpu->R[b]);
7266 c += MMU.MMU_WAIT32[cpu->proc_ID][(start>>24)&0xF];
7267 start += 4;
7268 }
7269 }
7270 return c + 1;
7271 }
7272
7273 static u32 FASTCALL OP_STMIB(armcpu_t *cpu)
7274 {
7275 u32 i = cpu->instruction, c = 0, b;
7276 u32 start = cpu->R[REG_POS(i,16)];
7277
7278 for(b=0; b<16; ++b)
7279 {
7280 if(BIT_N(i, b))
7281 {
7282 start += 4;
7283 WRITE32(cpu->mem_if->data, start, cpu->R[b]);
7284 c += MMU.MMU_WAIT32[cpu->proc_ID][(start>>24)&0xF];
7285 }
7286 }
7287 return c + 1;
7288 }
7289
7290 static u32 FASTCALL OP_STMDA(armcpu_t *cpu)
7291 {
7292 u32 i = cpu->instruction, c = 0, b;
7293 u32 start = cpu->R[REG_POS(i,16)];
7294
7295 for(b=0; b<16; ++b)
7296 {
7297 if(BIT_N(i, 15-b))
7298 {
7299 WRITE32(cpu->mem_if->data, start, cpu->R[15-b]);
7300 c += MMU.MMU_WAIT32[cpu->proc_ID][(start>>24)&0xF];
7301 start -= 4;
7302 }
7303 }
7304 return c + 1;
7305 }
7306
7307 static u32 FASTCALL OP_STMDB(armcpu_t *cpu)
7308 {
7309 u32 i = cpu->instruction, c = 0, b;
7310 u32 start = cpu->R[REG_POS(i,16)];
7311
7312 for(b=0; b<16; ++b)
7313 {
7314 if(BIT_N(i, 15-b))
7315 {
7316 start -= 4;
7317 WRITE32(cpu->mem_if->data, start, cpu->R[15-b]);
7318 c += MMU.MMU_WAIT32[cpu->proc_ID][(start>>24)&0xF];
7319 }
7320 }
7321 return c + 1;
7322 }
7323
7324 static u32 FASTCALL OP_STMIA_W(armcpu_t *cpu)
7325 {
7326 u32 i = cpu->instruction, c = 0, b;
7327 u32 start = cpu->R[REG_POS(i,16)];
7328
7329 for(b=0; b<16; ++b)
7330 {
7331 if(BIT_N(i, b))
7332 {
7333 WRITE32(cpu->mem_if->data, start, cpu->R[b]);
7334 c += MMU.MMU_WAIT32[cpu->proc_ID][(start>>24)&0xF];
7335 start += 4;
7336 }
7337 }
7338
7339 cpu->R[REG_POS(i,16)] = start;
7340 return c + 1;
7341 }
7342
7343 static u32 FASTCALL OP_STMIB_W(armcpu_t *cpu)
7344 {
7345 u32 i = cpu->instruction, c = 0, b;
7346 u32 start = cpu->R[REG_POS(i,16)];
7347
7348 for(b=0; b<16; ++b)
7349 {
7350 if(BIT_N(i, b))
7351 {
7352 start += 4;
7353 WRITE32(cpu->mem_if->data, start, cpu->R[b]);
7354 c += MMU.MMU_WAIT32[cpu->proc_ID][(start>>24)&0xF];
7355 }
7356 }
7357 cpu->R[REG_POS(i,16)] = start;
7358 return c + 1;
7359 }
7360
7361 static u32 FASTCALL OP_STMDA_W(armcpu_t *cpu)
7362 {
7363 u32 i = cpu->instruction, c = 0, b;
7364 u32 start = cpu->R[REG_POS(i,16)];
7365
7366 for(b=0; b<16; ++b)
7367 {
7368 if(BIT_N(i, 15-b))
7369 {
7370 WRITE32(cpu->mem_if->data, start, cpu->R[15-b]);
7371 c += MMU.MMU_WAIT32[cpu->proc_ID][(start>>24)&0xF];
7372 start -= 4;
7373 }
7374 }
7375
7376 cpu->R[REG_POS(i,16)] = start;
7377 return c + 1;
7378 }
7379
7380 static u32 FASTCALL OP_STMDB_W(armcpu_t *cpu)
7381 {
7382 u32 i = cpu->instruction, c = 0, b;
7383 u32 start = cpu->R[REG_POS(i,16)];
7384
7385 for(b=0; b<16; ++b)
7386 {
7387 if(BIT_N(i, 15-b))
7388 {
7389 start -= 4;
7390 WRITE32(cpu->mem_if->data, start, cpu->R[15-b]);
7391 c += MMU.MMU_WAIT32[cpu->proc_ID][(start>>24)&0xF];
7392 }
7393 }
7394
7395 cpu->R[REG_POS(i,16)] = start;
7396 return c + 1;
7397 }
7398
7399 static u32 FASTCALL OP_STMIA2(armcpu_t *cpu)
7400 {
7401 u32 i, c, b;
7402 u32 start;
7403 u32 oldmode;
7404
7405 if(cpu->CPSR.bits.mode==USR)
7406 return 2;
7407
7408 i = cpu->instruction;
7409 c = 0;
7410 start = cpu->R[REG_POS(i,16)];
7411 oldmode = armcpu_switchMode(cpu, SYS);
7412
7413 //execute = FALSE;
7414 LOG("Untested opcode: OP_STMIA2");
7415
7416 for(b=0; b<16; ++b)
7417 {
7418 if(BIT_N(i, b))
7419 {
7420 WRITE32(cpu->mem_if->data, start, cpu->R[b]);
7421 c += MMU.MMU_WAIT32[cpu->proc_ID][(start>>24)&0xF];
7422 start += 4;
7423 }
7424 }
7425
7426 armcpu_switchMode(cpu, oldmode);
7427 return c + 1;
7428 }
7429
7430 static u32 FASTCALL OP_STMIB2(armcpu_t *cpu)
7431 {
7432 u32 i, c, b;
7433 u32 start;
7434 u32 oldmode;
7435
7436 if(cpu->CPSR.bits.mode==USR)
7437 return 2;
7438
7439 i = cpu->instruction;
7440 c = 0;
7441 start = cpu->R[REG_POS(i,16)];
7442 oldmode = armcpu_switchMode(cpu, SYS);
7443
7444 //execute = FALSE;
7445 LOG("Untested opcode: OP_STMIB2");
7446
7447 for(b=0; b<16; ++b)
7448 {
7449 if(BIT_N(i, b))
7450 {
7451 start += 4;
7452 WRITE32(cpu->mem_if->data, start, cpu->R[b]);
7453 c += MMU.MMU_WAIT32[cpu->proc_ID][(start>>24)&0xF];
7454 }
7455 }
7456
7457 armcpu_switchMode(cpu, oldmode);
7458 return c + 1;
7459 }
7460
7461 static u32 FASTCALL OP_STMDA2(armcpu_t *cpu)
7462 {
7463 u32 i, c, b;
7464 u32 start;
7465 u32 oldmode;
7466
7467 if(cpu->CPSR.bits.mode==USR)
7468 return 2;
7469
7470 i = cpu->instruction;
7471 c = 0;
7472 start = cpu->R[REG_POS(i,16)];
7473 oldmode = armcpu_switchMode(cpu, SYS);
7474
7475 //execute = FALSE;
7476 LOG("Untested opcode: OP_STMDA2");
7477
7478 for(b=0; b<16; ++b)
7479 {
7480 if(BIT_N(i, 15-b))
7481 {
7482 WRITE32(cpu->mem_if->data, start, cpu->R[15-b]);
7483 c += MMU.MMU_WAIT32[cpu->proc_ID][(start>>24)&0xF];
7484 start -= 4;
7485 }
7486 }
7487
7488 armcpu_switchMode(cpu, oldmode);
7489 return c + 1;
7490 }
7491
7492 static u32 FASTCALL OP_STMDB2(armcpu_t *cpu)
7493 {
7494 u32 i, c, b;
7495 u32 start;
7496 u32 oldmode;
7497
7498 if(cpu->CPSR.bits.mode==USR)
7499 return 2;
7500 i = cpu->instruction;
7501 c=0;
7502 start = cpu->R[REG_POS(i,16)];
7503 oldmode = armcpu_switchMode(cpu, SYS);
7504
7505 for(b=0; b<16; ++b)
7506 {
7507 if(BIT_N(i, 15-b))
7508 {
7509 start -= 4;
7510 WRITE32(cpu->mem_if->data, start, cpu->R[15-b]);
7511 c += MMU.MMU_WAIT32[cpu->proc_ID][(start>>24)&0xF];
7512 }
7513 }
7514
7515 armcpu_switchMode(cpu, oldmode);
7516 return c + 1;
7517 }
7518
7519 static u32 FASTCALL OP_STMIA2_W(armcpu_t *cpu)
7520 {
7521 u32 i, c, b;
7522 u32 start;
7523 u32 oldmode;
7524
7525 if(cpu->CPSR.bits.mode==USR)
7526 return 2;
7527
7528 i = cpu->instruction;
7529 c=0;
7530 start = cpu->R[REG_POS(i,16)];
7531 oldmode = armcpu_switchMode(cpu, SYS);
7532
7533 //execute = FALSE;
7534 LOG("Untested opcode: OP_STMIA2_W");
7535
7536 for(b=0; b<16; ++b)
7537 {
7538 if(BIT_N(i, b))
7539 {
7540 WRITE32(cpu->mem_if->data, start, cpu->R[b]);
7541 c += MMU.MMU_WAIT32[cpu->proc_ID][(start>>24)&0xF];
7542 start += 4;
7543 }
7544 }
7545
7546 cpu->R[REG_POS(i,16)] = start;
7547
7548 armcpu_switchMode(cpu, oldmode);
7549 return c + 1;
7550 }
7551
7552 static u32 FASTCALL OP_STMIB2_W(armcpu_t *cpu)
7553 {
7554 u32 i, c, b;
7555 u32 start;
7556 u32 oldmode;
7557
7558 if(cpu->CPSR.bits.mode==USR)
7559 return 2;
7560 i = cpu->instruction;
7561 c=0;
7562 start = cpu->R[REG_POS(i,16)];
7563 oldmode = armcpu_switchMode(cpu, SYS);
7564
7565 for(b=0; b<16; ++b)
7566 {
7567 if(BIT_N(i, b))
7568 {
7569 start += 4;
7570 WRITE32(cpu->mem_if->data, start, cpu->R[b]);
7571 c += MMU.MMU_WAIT32[cpu->proc_ID][(start>>24)&0xF];
7572 }
7573 }
7574 armcpu_switchMode(cpu, oldmode);
7575 cpu->R[REG_POS(i,16)] = start;
7576
7577 return c + 1;
7578 }
7579
7580 static u32 FASTCALL OP_STMDA2_W(armcpu_t *cpu)
7581 {
7582 u32 i, c, b;
7583 u32 start;
7584 u32 oldmode;
7585
7586 if(cpu->CPSR.bits.mode==USR)
7587 return 2;
7588
7589 i = cpu->instruction;
7590 c = 0;
7591 start = cpu->R[REG_POS(i,16)];
7592 oldmode = armcpu_switchMode(cpu, SYS);
7593 //execute = FALSE;
7594 LOG("Untested opcode: OP_STMDA2_W");
7595
7596 for(b=0; b<16; ++b)
7597 {
7598 if(BIT_N(i, 15-b))
7599 {
7600 WRITE32(cpu->mem_if->data, start, cpu->R[15-b]);
7601 c += MMU.MMU_WAIT32[cpu->proc_ID][(start>>24)&0xF];
7602 start -= 4;
7603 }
7604 }
7605
7606 cpu->R[REG_POS(i,16)] = start;
7607
7608 armcpu_switchMode(cpu, oldmode);
7609 return c + 1;
7610 }
7611
7612 static u32 FASTCALL OP_STMDB2_W(armcpu_t *cpu)
7613 {
7614 u32 i, c, b;
7615 u32 start;
7616 u32 oldmode;
7617
7618 if(cpu->CPSR.bits.mode==USR)
7619 return 2;
7620
7621 i = cpu->instruction;
7622 c = 0;
7623
7624 start = cpu->R[REG_POS(i,16)];
7625 oldmode = armcpu_switchMode(cpu, SYS);
7626
7627 //execute = FALSE;
7628 LOG("Untested opcode: OP_STMDB2_W");
7629
7630 for(b=0; b<16; ++b)
7631 {
7632 if(BIT_N(i, 15-b))
7633 {
7634 start -= 4;
7635 WRITE32(cpu->mem_if->data, start, cpu->R[15-b]);
7636 c += MMU.MMU_WAIT32[cpu->proc_ID][(start>>24)&0xF];
7637 }
7638 }
7639
7640 cpu->R[REG_POS(i,16)] = start;
7641
7642 armcpu_switchMode(cpu, oldmode);
7643 return c + 1;
7644 }
7645
7646 /*
7647 *
7648 * The Enhanced DSP Extension LDRD and STRD instructions.
7649 *
7650 */
7651 static u32 FASTCALL
7652 OP_LDRD_STRD_POST_INDEX( armcpu_t *cpu) {
7653 u32 i = cpu->instruction;
7654 u32 Rd_num = REG_POS( i, 12);
7655 u32 addr = cpu->R[REG_POS(i,16)];
7656 u32 index;
7657
7658 /* I bit - immediate or register */
7659 if ( BIT22(i))
7660 index = IMM_OFF;
7661 else
7662 index = cpu->R[REG_POS(i,0)];
7663
7664 /* U bit - add or subtract */
7665 if ( BIT23(i))
7666 cpu->R[REG_POS(i,16)] += index;
7667 else
7668 cpu->R[REG_POS(i,16)] -= index;
7669
7670 if ( !(Rd_num & 0x1)) {
7671 /* Store/Load */
7672 if ( BIT5(i)) {
7673 WRITE32(cpu->mem_if->data, addr, cpu->R[Rd_num]);
7674 WRITE32(cpu->mem_if->data, addr + 4, cpu->R[Rd_num + 1]);
7675 }
7676 else {
7677 cpu->R[Rd_num] = READ32(cpu->mem_if->data, addr);
7678 cpu->R[Rd_num + 1] = READ32(cpu->mem_if->data, addr + 4);
7679 }
7680 }
7681
7682 return 3 + (MMU.MMU_WAIT32[cpu->proc_ID][(addr>>24)&0xF] * 2);
7683 }
7684
7685 static u32 FASTCALL
7686 OP_LDRD_STRD_OFFSET_PRE_INDEX( armcpu_t *cpu) {
7687 u32 i = cpu->instruction;
7688 u32 Rd_num = REG_POS( i, 12);
7689 u32 addr = cpu->R[REG_POS(i,16)];
7690 u32 index;
7691
7692 /* I bit - immediate or register */
7693 if ( BIT22(i))
7694 index = IMM_OFF;
7695 else
7696 index = cpu->R[REG_POS(i,0)];
7697
7698 /* U bit - add or subtract */
7699 if ( BIT23(i)) {
7700 addr += index;
7701
7702 /* W bit - writeback */
7703 if ( BIT21(i))
7704 cpu->R[REG_POS(i,16)] = addr;
7705 }
7706 else {
7707 addr -= index;
7708
7709 /* W bit - writeback */
7710 if ( BIT21(i))
7711 cpu->R[REG_POS(i,16)] = addr;
7712 }
7713
7714 if ( !(Rd_num & 0x1)) {
7715 /* Store/Load */
7716 if ( BIT5(i)) {
7717 WRITE32(cpu->mem_if->data, addr, cpu->R[Rd_num]);
7718 WRITE32(cpu->mem_if->data, addr + 4, cpu->R[Rd_num + 1]);
7719 }
7720 else {
7721 cpu->R[Rd_num] = READ32(cpu->mem_if->data, addr);
7722 cpu->R[Rd_num + 1] = READ32(cpu->mem_if->data, addr + 4);
7723 }
7724 }
7725
7726 return 3 + (MMU.MMU_WAIT32[cpu->proc_ID][(addr>>24)&0xF] * 2);
7727 }
7728
7729
7730
7731 //---------------------STC----------------------------------
7732
7733 static u32 FASTCALL OP_STC_P_IMM_OFF(armcpu_t *cpu)
7734 {
7735 {
7736 /* the NDS has no coproc that responses to a STC, no feedback is given to the arm */
7737 return 2;
7738 }
7739 }
7740
7741 static u32 FASTCALL OP_STC_M_IMM_OFF(armcpu_t *cpu)
7742 {
7743 {
7744 /* the NDS has no coproc that responses to a STC, no feedback is given to the arm */
7745 return 2;
7746 }
7747 }
7748
7749 static u32 FASTCALL OP_STC_P_PREIND(armcpu_t *cpu)
7750 {
7751 {
7752 /* the NDS has no coproc that responses to a STC, no feedback is given to the arm */
7753 return 2;
7754 }
7755 }
7756
7757 static u32 FASTCALL OP_STC_M_PREIND(armcpu_t *cpu)
7758 {
7759 {
7760 /* the NDS has no coproc that responses to a STC, no feedback is given to the arm */
7761 return 2;
7762 }
7763 }
7764
7765 static u32 FASTCALL OP_STC_P_POSTIND(armcpu_t *cpu)
7766 {
7767 {
7768 /* the NDS has no coproc that responses to a STC, no feedback is given to the arm */
7769 return 2;
7770 }
7771 }
7772
7773 static u32 FASTCALL OP_STC_M_POSTIND(armcpu_t *cpu)
7774 {
7775 {
7776 /* the NDS has no coproc that responses to a STC, no feedback is given to the arm */
7777 return 2;
7778 }
7779 }
7780
7781 static u32 FASTCALL OP_STC_OPTION(armcpu_t *cpu)
7782 {
7783 {
7784 /* the NDS has no coproc that responses to a STC, no feedback is given to the arm */
7785 return 2;
7786 }
7787 }
7788
7789 //---------------------LDC----------------------------------
7790
7791 static u32 FASTCALL OP_LDC_P_IMM_OFF(armcpu_t *cpu)
7792 {
7793 {
7794 /* the NDS has no coproc that responses to a LDC, no feedback is given to the arm */
7795 return 2;
7796 }
7797 }
7798
7799 static u32 FASTCALL OP_LDC_M_IMM_OFF(armcpu_t *cpu)
7800 {
7801 {
7802 /* the NDS has no coproc that responses to a LDC, no feedback is given to the arm */
7803 return 2;
7804 }
7805 }
7806
7807 static u32 FASTCALL OP_LDC_P_PREIND(armcpu_t *cpu)
7808 {
7809 {
7810 /* the NDS has no coproc that responses to a LDC, no feedback is given to the arm */
7811 return 2;
7812 }
7813 }
7814
7815 static u32 FASTCALL OP_LDC_M_PREIND(armcpu_t *cpu)
7816 {
7817 {
7818 /* the NDS has no coproc that responses to a LDC, no feedback is given to the arm */
7819 return 2;
7820 }
7821 }
7822
7823 static u32 FASTCALL OP_LDC_P_POSTIND(armcpu_t *cpu)
7824 {
7825 {
7826 /* the NDS has no coproc that responses to a LDC, no feedback is given to the arm */
7827 return 2;
7828 }
7829 }
7830
7831 static u32 FASTCALL OP_LDC_M_POSTIND(armcpu_t *cpu)
7832 {
7833 {
7834 /* the NDS has no coproc that responses to a LDC, no feedback is given to the arm */
7835 return 2;
7836 }
7837 }
7838
7839 static u32 FASTCALL OP_LDC_OPTION(armcpu_t *cpu)
7840 {
7841 {
7842 /* the NDS has no coproc that responses to a LDC, no feedback is given to the arm */
7843 return 2;
7844 }
7845 }
7846
7847 //----------------MCR-----------------------
7848
7849 static u32 FASTCALL OP_MCR(armcpu_t *cpu)
7850 {
7851 u32 i = cpu->instruction;
7852 u32 cpnum = REG_POS(i, 8);
7853
7854 if(!cpu->coproc[cpnum])
7855 {
7856 execute = FALSE;
7857 return 2;
7858 }
7859
7860 armcp15_moveARM2CP((armcp15_t*)cpu->coproc[cpnum], cpu->R[REG_POS(i, 12)], REG_POS(i, 16), REG_POS(i, 0), (i>>21)&7, (i>>5)&7);
7861 //cpu->coproc[cpnum]->moveARM2CP(cpu->R[REG_POS(i, 12)], REG_POS(i, 16), REG_POS(i, 0), (i>>21)&7, (i>>5)&7);
7862 return 2;
7863 }
7864
7865 //----------------MRC-----------------------
7866
7867 static u32 FASTCALL OP_MRC(armcpu_t *cpu)
7868 {
7869 u32 i = cpu->instruction;
7870 u32 cpnum = REG_POS(i, 8);
7871
7872 if(!cpu->coproc[cpnum])
7873 {
7874 execute = FALSE;
7875 return 2;
7876 }
7877
7878 armcp15_moveCP2ARM((armcp15_t*)cpu->coproc[cpnum], &cpu->R[REG_POS(i, 12)], REG_POS(i, 16), REG_POS(i, 0), (i>>21)&7, (i>>5)&7);
7879 //cpu->coproc[cpnum]->moveCP2ARM(&cpu->R[REG_POS(i, 12)], REG_POS(i, 16), REG_POS(i, 0), (i>>21)&7, (i>>5)&7);
7880 return 4;
7881 }
7882
7883 //--------------SWI-------------------------------
7884 static u32 FASTCALL OP_SWI(armcpu_t *cpu)
7885 {
7886 if (((cpu->intVector != 0) ^ (cpu->proc_ID == ARMCPU_ARM9)))
7887 {
7888 /* TODO (#1#): translocated SWI vectors */
7889 /* we use an irq thats not in the irq tab, as
7890 it was replaced duie to a changed intVector */
7891 Status_Reg tmp = cpu->CPSR;
7892 armcpu_switchMode(cpu, SVC); /* enter svc mode */
7893 cpu->R[14] = cpu->R[15] - 4; /* jump to swi Vector */
7894 cpu->SPSR = tmp; /* save old CPSR as new SPSR */
7895 cpu->CPSR.bits.T = 0; /* handle as ARM32 code */
7896 cpu->CPSR.bits.I = cpu->SPSR.bits.I; /* keep int disable flag */
7897 cpu->R[15] = cpu->intVector + 0x08;
7898 cpu->next_instruction = cpu->R[15];
7899 return 4;
7900 }
7901 else
7902 {
7903 u32 swinum = (cpu->instruction>>16)&0x1F;
7904 return cpu->swi_tab[swinum](cpu) + 3;
7905 }
7906 }
7907
7908 //----------------BKPT-------------------------
7909 static u32 FASTCALL OP_BKPT(armcpu_t *cpu)
7910 {
7911 execute = FALSE;
7912 return 4;
7913 }
7914
7915 //----------------CDP-----------------------
7916
7917 static u32 FASTCALL OP_CDP(armcpu_t *cpu)
7918 {
7919 execute = FALSE;
7920 return 4;
7921 }
7922
7923 #define TYPE_RETOUR u32
7924 #define PARAMETRES armcpu_t *cpu
7925 #define CALLTYPE FASTCALL
7926 #define NOM_TAB arm_instructions_set
7927
7928 #include "instruction_tabdef.inc"