Mercurial > audlegacy-plugins
comparison src/psf2/psx.c @ 2954:f1482af6384c
Warning clean.
| author | William Pitcock <nenolod@atheme.org> |
|---|---|
| date | Wed, 15 Oct 2008 14:31:23 -0500 |
| parents | 62cc6d667119 |
| children | 6d8892d78ded |
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| 2953:2cbc458d8286 | 2954:f1482af6384c |
|---|---|
| 151 0,14,44, 8, /* memory #1 window (left, middle) */ | 151 0,14,44, 8, /* memory #1 window (left, middle) */ |
| 152 45,14,35, 8, /* memory #2 window (lower) */ | 152 45,14,35, 8, /* memory #2 window (lower) */ |
| 153 0,23,80, 1 /* command line window (bottom rows) */ | 153 0,23,80, 1 /* command line window (bottom rows) */ |
| 154 }; | 154 }; |
| 155 | 155 |
| 156 static const char *delayn[] = | |
| 157 { | |
| 158 "pc", "at", "v0", "v1", "a0", "a1", "a2", "a3", | |
| 159 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
| 160 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
| 161 "t8", "t9", "k0", "k1", "gp", "sp", "fp", "ra", | |
| 162 "pc" | |
| 163 }; | |
| 164 | |
| 165 #define REGPC ( 32 ) | 156 #define REGPC ( 32 ) |
| 166 | 157 |
| 167 typedef struct | 158 typedef struct |
| 168 { | 159 { |
| 169 UINT32 op; | 160 UINT32 op; |
| 1653 // printf( "%08x: unknown opcode %08x (prev %08x, RA %08x)\n", mipscpu.pc, mipscpu.op, mipscpu.prevpc, mipscpu.r[31] ); | 1644 // printf( "%08x: unknown opcode %08x (prev %08x, RA %08x)\n", mipscpu.pc, mipscpu.op, mipscpu.prevpc, mipscpu.r[31] ); |
| 1654 // mips_stop(); | 1645 // mips_stop(); |
| 1655 // mips_exception( EXC_RI ); | 1646 // mips_exception( EXC_RI ); |
| 1656 break; | 1647 break; |
| 1657 } | 1648 } |
| 1658 skipinterp: | |
| 1659 mips_ICount--; | 1649 mips_ICount--; |
| 1660 } while( mips_ICount > 0 ); | 1650 } while( mips_ICount > 0 ); |
| 1661 | 1651 |
| 1662 return cycles - mips_ICount; | 1652 return cycles - mips_ICount; |
| 1663 } | 1653 } |
| 2958 case CPUINFO_PTR_DISASSEMBLE: info->disassemble = mips_dasm; break; | 2948 case CPUINFO_PTR_DISASSEMBLE: info->disassemble = mips_dasm; break; |
| 2959 case CPUINFO_PTR_IRQ_CALLBACK: info->irqcallback = mipscpu.irq_callback; break; | 2949 case CPUINFO_PTR_IRQ_CALLBACK: info->irqcallback = mipscpu.irq_callback; break; |
| 2960 case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &mips_ICount; break; | 2950 case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &mips_ICount; break; |
| 2961 case CPUINFO_PTR_REGISTER_LAYOUT: info->p = mips_reg_layout; break; | 2951 case CPUINFO_PTR_REGISTER_LAYOUT: info->p = mips_reg_layout; break; |
| 2962 case CPUINFO_PTR_WINDOW_LAYOUT: info->p = mips_win_layout; break; | 2952 case CPUINFO_PTR_WINDOW_LAYOUT: info->p = mips_win_layout; break; |
| 2963 | |
| 2964 /* --- the following bits of info are returned as NULL-terminated strings --- */ | |
| 2965 #if 0 | |
| 2966 case CPUINFO_STR_NAME: strcpy(info->s = cpuintrf_temp_str(), "PSX CPU"); break; | |
| 2967 case CPUINFO_STR_CORE_FAMILY: strcpy(info->s = cpuintrf_temp_str(), "mipscpu"); break; | |
| 2968 case CPUINFO_STR_CORE_VERSION: strcpy(info->s = cpuintrf_temp_str(), "1.4"); break; | |
| 2969 case CPUINFO_STR_CORE_FILE: strcpy(info->s = cpuintrf_temp_str(), __FILE__); break; | |
| 2970 case CPUINFO_STR_CORE_CREDITS: strcpy(info->s = cpuintrf_temp_str(), "Copyright 2003 smf"); break; | |
| 2971 | |
| 2972 case CPUINFO_STR_FLAGS: strcpy(info->s = cpuintrf_temp_str(), " "); break; | |
| 2973 | |
| 2974 case CPUINFO_STR_REGISTER + MIPS_PC: sprintf( info->s = cpuintrf_temp_str(), "pc :%08x", mipscpu.pc ); break; | |
| 2975 case CPUINFO_STR_REGISTER + MIPS_DELAYV: sprintf( info->s = cpuintrf_temp_str(), "delay :%08x", mipscpu.delayv ); break; | |
| 2976 case CPUINFO_STR_REGISTER + MIPS_DELAYR: sprintf( info->s = cpuintrf_temp_str(), "delay %s:%02x", delayn[ mipscpu.delayr ], mipscpu.delayr ); break; | |
| 2977 case CPUINFO_STR_REGISTER + MIPS_HI: sprintf( info->s = cpuintrf_temp_str(), "hi :%08x", mipscpu.hi ); break; | |
| 2978 case CPUINFO_STR_REGISTER + MIPS_LO: sprintf( info->s = cpuintrf_temp_str(), "lo :%08x", mipscpu.lo ); break; | |
| 2979 case CPUINFO_STR_REGISTER + MIPS_R0: sprintf( info->s = cpuintrf_temp_str(), "zero :%08x", mipscpu.r[ 0 ] ); break; | |
| 2980 case CPUINFO_STR_REGISTER + MIPS_R1: sprintf( info->s = cpuintrf_temp_str(), "at :%08x", mipscpu.r[ 1 ] ); break; | |
| 2981 case CPUINFO_STR_REGISTER + MIPS_R2: sprintf( info->s = cpuintrf_temp_str(), "v0 :%08x", mipscpu.r[ 2 ] ); break; | |
| 2982 case CPUINFO_STR_REGISTER + MIPS_R3: sprintf( info->s = cpuintrf_temp_str(), "v1 :%08x", mipscpu.r[ 3 ] ); break; | |
| 2983 case CPUINFO_STR_REGISTER + MIPS_R4: sprintf( info->s = cpuintrf_temp_str(), "a0 :%08x", mipscpu.r[ 4 ] ); break; | |
| 2984 case CPUINFO_STR_REGISTER + MIPS_R5: sprintf( info->s = cpuintrf_temp_str(), "a1 :%08x", mipscpu.r[ 5 ] ); break; | |
| 2985 case CPUINFO_STR_REGISTER + MIPS_R6: sprintf( info->s = cpuintrf_temp_str(), "a2 :%08x", mipscpu.r[ 6 ] ); break; | |
| 2986 case CPUINFO_STR_REGISTER + MIPS_R7: sprintf( info->s = cpuintrf_temp_str(), "a3 :%08x", mipscpu.r[ 7 ] ); break; | |
| 2987 case CPUINFO_STR_REGISTER + MIPS_R8: sprintf( info->s = cpuintrf_temp_str(), "t0 :%08x", mipscpu.r[ 8 ] ); break; | |
| 2988 case CPUINFO_STR_REGISTER + MIPS_R9: sprintf( info->s = cpuintrf_temp_str(), "t1 :%08x", mipscpu.r[ 9 ] ); break; | |
| 2989 case CPUINFO_STR_REGISTER + MIPS_R10: sprintf( info->s = cpuintrf_temp_str(), "t2 :%08x", mipscpu.r[ 10 ] ); break; | |
| 2990 case CPUINFO_STR_REGISTER + MIPS_R11: sprintf( info->s = cpuintrf_temp_str(), "t3 :%08x", mipscpu.r[ 11 ] ); break; | |
| 2991 case CPUINFO_STR_REGISTER + MIPS_R12: sprintf( info->s = cpuintrf_temp_str(), "t4 :%08x", mipscpu.r[ 12 ] ); break; | |
| 2992 case CPUINFO_STR_REGISTER + MIPS_R13: sprintf( info->s = cpuintrf_temp_str(), "t5 :%08x", mipscpu.r[ 13 ] ); break; | |
| 2993 case CPUINFO_STR_REGISTER + MIPS_R14: sprintf( info->s = cpuintrf_temp_str(), "t6 :%08x", mipscpu.r[ 14 ] ); break; | |
| 2994 case CPUINFO_STR_REGISTER + MIPS_R15: sprintf( info->s = cpuintrf_temp_str(), "t7 :%08x", mipscpu.r[ 15 ] ); break; | |
| 2995 case CPUINFO_STR_REGISTER + MIPS_R16: sprintf( info->s = cpuintrf_temp_str(), "s0 :%08x", mipscpu.r[ 16 ] ); break; | |
| 2996 case CPUINFO_STR_REGISTER + MIPS_R17: sprintf( info->s = cpuintrf_temp_str(), "s1 :%08x", mipscpu.r[ 17 ] ); break; | |
| 2997 case CPUINFO_STR_REGISTER + MIPS_R18: sprintf( info->s = cpuintrf_temp_str(), "s2 :%08x", mipscpu.r[ 18 ] ); break; | |
| 2998 case CPUINFO_STR_REGISTER + MIPS_R19: sprintf( info->s = cpuintrf_temp_str(), "s3 :%08x", mipscpu.r[ 19 ] ); break; | |
| 2999 case CPUINFO_STR_REGISTER + MIPS_R20: sprintf( info->s = cpuintrf_temp_str(), "s4 :%08x", mipscpu.r[ 20 ] ); break; | |
| 3000 case CPUINFO_STR_REGISTER + MIPS_R21: sprintf( info->s = cpuintrf_temp_str(), "s5 :%08x", mipscpu.r[ 21 ] ); break; | |
| 3001 case CPUINFO_STR_REGISTER + MIPS_R22: sprintf( info->s = cpuintrf_temp_str(), "s6 :%08x", mipscpu.r[ 22 ] ); break; | |
| 3002 case CPUINFO_STR_REGISTER + MIPS_R23: sprintf( info->s = cpuintrf_temp_str(), "s7 :%08x", mipscpu.r[ 23 ] ); break; | |
| 3003 case CPUINFO_STR_REGISTER + MIPS_R24: sprintf( info->s = cpuintrf_temp_str(), "t8 :%08x", mipscpu.r[ 24 ] ); break; | |
| 3004 case CPUINFO_STR_REGISTER + MIPS_R25: sprintf( info->s = cpuintrf_temp_str(), "t9 :%08x", mipscpu.r[ 25 ] ); break; | |
| 3005 case CPUINFO_STR_REGISTER + MIPS_R26: sprintf( info->s = cpuintrf_temp_str(), "k0 :%08x", mipscpu.r[ 26 ] ); break; | |
| 3006 case CPUINFO_STR_REGISTER + MIPS_R27: sprintf( info->s = cpuintrf_temp_str(), "k1 :%08x", mipscpu.r[ 27 ] ); break; | |
| 3007 case CPUINFO_STR_REGISTER + MIPS_R28: sprintf( info->s = cpuintrf_temp_str(), "gp :%08x", mipscpu.r[ 28 ] ); break; | |
| 3008 case CPUINFO_STR_REGISTER + MIPS_R29: sprintf( info->s = cpuintrf_temp_str(), "sp :%08x", mipscpu.r[ 29 ] ); break; | |
| 3009 case CPUINFO_STR_REGISTER + MIPS_R30: sprintf( info->s = cpuintrf_temp_str(), "fp :%08x", mipscpu.r[ 30 ] ); break; | |
| 3010 case CPUINFO_STR_REGISTER + MIPS_R31: sprintf( info->s = cpuintrf_temp_str(), "ra :%08x", mipscpu.r[ 31 ] ); break; | |
| 3011 case CPUINFO_STR_REGISTER + MIPS_CP0R0: sprintf( info->s = cpuintrf_temp_str(), "Index :%08x", mipscpu.cp0r[ 0 ] ); break; | |
| 3012 case CPUINFO_STR_REGISTER + MIPS_CP0R1: sprintf( info->s = cpuintrf_temp_str(), "Random :%08x", mipscpu.cp0r[ 1 ] ); break; | |
| 3013 case CPUINFO_STR_REGISTER + MIPS_CP0R2: sprintf( info->s = cpuintrf_temp_str(), "EntryLo :%08x", mipscpu.cp0r[ 2 ] ); break; | |
| 3014 case CPUINFO_STR_REGISTER + MIPS_CP0R3: sprintf( info->s = cpuintrf_temp_str(), "cp0r3 :%08x", mipscpu.cp0r[ 3 ] ); break; | |
| 3015 case CPUINFO_STR_REGISTER + MIPS_CP0R4: sprintf( info->s = cpuintrf_temp_str(), "Context :%08x", mipscpu.cp0r[ 4 ] ); break; | |
| 3016 case CPUINFO_STR_REGISTER + MIPS_CP0R5: sprintf( info->s = cpuintrf_temp_str(), "cp0r5 :%08x", mipscpu.cp0r[ 5 ] ); break; | |
| 3017 case CPUINFO_STR_REGISTER + MIPS_CP0R6: sprintf( info->s = cpuintrf_temp_str(), "cp0r6 :%08x", mipscpu.cp0r[ 6 ] ); break; | |
| 3018 case CPUINFO_STR_REGISTER + MIPS_CP0R7: sprintf( info->s = cpuintrf_temp_str(), "cp0r7 :%08x", mipscpu.cp0r[ 7 ] ); break; | |
| 3019 case CPUINFO_STR_REGISTER + MIPS_CP0R8: sprintf( info->s = cpuintrf_temp_str(), "BadVAddr:%08x", mipscpu.cp0r[ 8 ] ); break; | |
| 3020 case CPUINFO_STR_REGISTER + MIPS_CP0R9: sprintf( info->s = cpuintrf_temp_str(), "cp0r9 :%08x", mipscpu.cp0r[ 9 ] ); break; | |
| 3021 case CPUINFO_STR_REGISTER + MIPS_CP0R10: sprintf( info->s = cpuintrf_temp_str(), "EntryHi :%08x", mipscpu.cp0r[ 10 ] ); break; | |
| 3022 case CPUINFO_STR_REGISTER + MIPS_CP0R11: sprintf( info->s = cpuintrf_temp_str(), "cp0r11 :%08x", mipscpu.cp0r[ 11 ] ); break; | |
| 3023 case CPUINFO_STR_REGISTER + MIPS_CP0R12: sprintf( info->s = cpuintrf_temp_str(), "SR :%08x", mipscpu.cp0r[ 12 ] ); break; | |
| 3024 case CPUINFO_STR_REGISTER + MIPS_CP0R13: sprintf( info->s = cpuintrf_temp_str(), "Cause :%08x", mipscpu.cp0r[ 13 ] ); break; | |
| 3025 case CPUINFO_STR_REGISTER + MIPS_CP0R14: sprintf( info->s = cpuintrf_temp_str(), "EPC :%08x", mipscpu.cp0r[ 14 ] ); break; | |
| 3026 case CPUINFO_STR_REGISTER + MIPS_CP0R15: sprintf( info->s = cpuintrf_temp_str(), "PRId :%08x", mipscpu.cp0r[ 15 ] ); break; | |
| 3027 case CPUINFO_STR_REGISTER + MIPS_CP0R16: sprintf( info->s = cpuintrf_temp_str(), "cp0r16 :%08x", mipscpu.cp0r[ 16 ] ); break; | |
| 3028 case CPUINFO_STR_REGISTER + MIPS_CP0R17: sprintf( info->s = cpuintrf_temp_str(), "cp0r17 :%08x", mipscpu.cp0r[ 17 ] ); break; | |
| 3029 case CPUINFO_STR_REGISTER + MIPS_CP0R18: sprintf( info->s = cpuintrf_temp_str(), "cp0r18 :%08x", mipscpu.cp0r[ 18 ] ); break; | |
| 3030 case CPUINFO_STR_REGISTER + MIPS_CP0R19: sprintf( info->s = cpuintrf_temp_str(), "cp0r19 :%08x", mipscpu.cp0r[ 19 ] ); break; | |
| 3031 case CPUINFO_STR_REGISTER + MIPS_CP0R20: sprintf( info->s = cpuintrf_temp_str(), "cp0r20 :%08x", mipscpu.cp0r[ 20 ] ); break; | |
| 3032 case CPUINFO_STR_REGISTER + MIPS_CP0R21: sprintf( info->s = cpuintrf_temp_str(), "cp0r21 :%08x", mipscpu.cp0r[ 21 ] ); break; | |
| 3033 case CPUINFO_STR_REGISTER + MIPS_CP0R22: sprintf( info->s = cpuintrf_temp_str(), "cp0r22 :%08x", mipscpu.cp0r[ 22 ] ); break; | |
| 3034 case CPUINFO_STR_REGISTER + MIPS_CP0R23: sprintf( info->s = cpuintrf_temp_str(), "cp0r23 :%08x", mipscpu.cp0r[ 23 ] ); break; | |
| 3035 case CPUINFO_STR_REGISTER + MIPS_CP0R24: sprintf( info->s = cpuintrf_temp_str(), "cp0r24 :%08x", mipscpu.cp0r[ 24 ] ); break; | |
| 3036 case CPUINFO_STR_REGISTER + MIPS_CP0R25: sprintf( info->s = cpuintrf_temp_str(), "cp0r25 :%08x", mipscpu.cp0r[ 25 ] ); break; | |
| 3037 case CPUINFO_STR_REGISTER + MIPS_CP0R26: sprintf( info->s = cpuintrf_temp_str(), "cp0r26 :%08x", mipscpu.cp0r[ 26 ] ); break; | |
| 3038 case CPUINFO_STR_REGISTER + MIPS_CP0R27: sprintf( info->s = cpuintrf_temp_str(), "cp0r27 :%08x", mipscpu.cp0r[ 27 ] ); break; | |
| 3039 case CPUINFO_STR_REGISTER + MIPS_CP0R28: sprintf( info->s = cpuintrf_temp_str(), "cp0r28 :%08x", mipscpu.cp0r[ 28 ] ); break; | |
| 3040 case CPUINFO_STR_REGISTER + MIPS_CP0R29: sprintf( info->s = cpuintrf_temp_str(), "cp0r29 :%08x", mipscpu.cp0r[ 29 ] ); break; | |
| 3041 case CPUINFO_STR_REGISTER + MIPS_CP0R30: sprintf( info->s = cpuintrf_temp_str(), "cp0r30 :%08x", mipscpu.cp0r[ 30 ] ); break; | |
| 3042 case CPUINFO_STR_REGISTER + MIPS_CP0R31: sprintf( info->s = cpuintrf_temp_str(), "cp0r31 :%08x", mipscpu.cp0r[ 31 ] ); break; | |
| 3043 case CPUINFO_STR_REGISTER + MIPS_CP2DR0: sprintf( info->s = cpuintrf_temp_str(), "vxy0 :%08x", mipscpu.cp2dr[ 0 ].d ); break; | |
| 3044 case CPUINFO_STR_REGISTER + MIPS_CP2DR1: sprintf( info->s = cpuintrf_temp_str(), "vz0 :%08x", mipscpu.cp2dr[ 1 ].d ); break; | |
| 3045 case CPUINFO_STR_REGISTER + MIPS_CP2DR2: sprintf( info->s = cpuintrf_temp_str(), "vxy1 :%08x", mipscpu.cp2dr[ 2 ].d ); break; | |
| 3046 case CPUINFO_STR_REGISTER + MIPS_CP2DR3: sprintf( info->s = cpuintrf_temp_str(), "vz1 :%08x", mipscpu.cp2dr[ 3 ].d ); break; | |
| 3047 case CPUINFO_STR_REGISTER + MIPS_CP2DR4: sprintf( info->s = cpuintrf_temp_str(), "vxy2 :%08x", mipscpu.cp2dr[ 4 ].d ); break; | |
| 3048 case CPUINFO_STR_REGISTER + MIPS_CP2DR5: sprintf( info->s = cpuintrf_temp_str(), "vz2 :%08x", mipscpu.cp2dr[ 5 ].d ); break; | |
| 3049 case CPUINFO_STR_REGISTER + MIPS_CP2DR6: sprintf( info->s = cpuintrf_temp_str(), "rgb :%08x", mipscpu.cp2dr[ 6 ].d ); break; | |
| 3050 case CPUINFO_STR_REGISTER + MIPS_CP2DR7: sprintf( info->s = cpuintrf_temp_str(), "otz :%08x", mipscpu.cp2dr[ 7 ].d ); break; | |
| 3051 case CPUINFO_STR_REGISTER + MIPS_CP2DR8: sprintf( info->s = cpuintrf_temp_str(), "ir0 :%08x", mipscpu.cp2dr[ 8 ].d ); break; | |
| 3052 case CPUINFO_STR_REGISTER + MIPS_CP2DR9: sprintf( info->s = cpuintrf_temp_str(), "ir1 :%08x", mipscpu.cp2dr[ 9 ].d ); break; | |
| 3053 case CPUINFO_STR_REGISTER + MIPS_CP2DR10: sprintf( info->s = cpuintrf_temp_str(), "ir2 :%08x", mipscpu.cp2dr[ 10 ].d ); break; | |
| 3054 case CPUINFO_STR_REGISTER + MIPS_CP2DR11: sprintf( info->s = cpuintrf_temp_str(), "ir3 :%08x", mipscpu.cp2dr[ 11 ].d ); break; | |
| 3055 case CPUINFO_STR_REGISTER + MIPS_CP2DR12: sprintf( info->s = cpuintrf_temp_str(), "sxy0 :%08x", mipscpu.cp2dr[ 12 ].d ); break; | |
| 3056 case CPUINFO_STR_REGISTER + MIPS_CP2DR13: sprintf( info->s = cpuintrf_temp_str(), "sxy1 :%08x", mipscpu.cp2dr[ 13 ].d ); break; | |
| 3057 case CPUINFO_STR_REGISTER + MIPS_CP2DR14: sprintf( info->s = cpuintrf_temp_str(), "sxy2 :%08x", mipscpu.cp2dr[ 14 ].d ); break; | |
| 3058 case CPUINFO_STR_REGISTER + MIPS_CP2DR15: sprintf( info->s = cpuintrf_temp_str(), "sxyp :%08x", mipscpu.cp2dr[ 15 ].d ); break; | |
| 3059 case CPUINFO_STR_REGISTER + MIPS_CP2DR16: sprintf( info->s = cpuintrf_temp_str(), "sz0 :%08x", mipscpu.cp2dr[ 16 ].d ); break; | |
| 3060 case CPUINFO_STR_REGISTER + MIPS_CP2DR17: sprintf( info->s = cpuintrf_temp_str(), "sz1 :%08x", mipscpu.cp2dr[ 17 ].d ); break; | |
| 3061 case CPUINFO_STR_REGISTER + MIPS_CP2DR18: sprintf( info->s = cpuintrf_temp_str(), "sz2 :%08x", mipscpu.cp2dr[ 18 ].d ); break; | |
| 3062 case CPUINFO_STR_REGISTER + MIPS_CP2DR19: sprintf( info->s = cpuintrf_temp_str(), "sz3 :%08x", mipscpu.cp2dr[ 19 ].d ); break; | |
| 3063 case CPUINFO_STR_REGISTER + MIPS_CP2DR20: sprintf( info->s = cpuintrf_temp_str(), "rgb0 :%08x", mipscpu.cp2dr[ 20 ].d ); break; | |
| 3064 case CPUINFO_STR_REGISTER + MIPS_CP2DR21: sprintf( info->s = cpuintrf_temp_str(), "rgb1 :%08x", mipscpu.cp2dr[ 21 ].d ); break; | |
| 3065 case CPUINFO_STR_REGISTER + MIPS_CP2DR22: sprintf( info->s = cpuintrf_temp_str(), "rgb2 :%08x", mipscpu.cp2dr[ 22 ].d ); break; | |
| 3066 case CPUINFO_STR_REGISTER + MIPS_CP2DR23: sprintf( info->s = cpuintrf_temp_str(), "res1 :%08x", mipscpu.cp2dr[ 23 ].d ); break; | |
| 3067 case CPUINFO_STR_REGISTER + MIPS_CP2DR24: sprintf( info->s = cpuintrf_temp_str(), "mac0 :%08x", mipscpu.cp2dr[ 24 ].d ); break; | |
| 3068 case CPUINFO_STR_REGISTER + MIPS_CP2DR25: sprintf( info->s = cpuintrf_temp_str(), "mac1 :%08x", mipscpu.cp2dr[ 25 ].d ); break; | |
| 3069 case CPUINFO_STR_REGISTER + MIPS_CP2DR26: sprintf( info->s = cpuintrf_temp_str(), "mac2 :%08x", mipscpu.cp2dr[ 26 ].d ); break; | |
| 3070 case CPUINFO_STR_REGISTER + MIPS_CP2DR27: sprintf( info->s = cpuintrf_temp_str(), "mac3 :%08x", mipscpu.cp2dr[ 27 ].d ); break; | |
| 3071 case CPUINFO_STR_REGISTER + MIPS_CP2DR28: sprintf( info->s = cpuintrf_temp_str(), "irgb :%08x", mipscpu.cp2dr[ 28 ].d ); break; | |
| 3072 case CPUINFO_STR_REGISTER + MIPS_CP2DR29: sprintf( info->s = cpuintrf_temp_str(), "orgb :%08x", mipscpu.cp2dr[ 29 ].d ); break; | |
| 3073 case CPUINFO_STR_REGISTER + MIPS_CP2DR30: sprintf( info->s = cpuintrf_temp_str(), "lzcs :%08x", mipscpu.cp2dr[ 30 ].d ); break; | |
| 3074 case CPUINFO_STR_REGISTER + MIPS_CP2DR31: sprintf( info->s = cpuintrf_temp_str(), "lzcr :%08x", mipscpu.cp2dr[ 31 ].d ); break; | |
| 3075 case CPUINFO_STR_REGISTER + MIPS_CP2CR0: sprintf( info->s = cpuintrf_temp_str(), "r11r12 :%08x", mipscpu.cp2cr[ 0 ].d ); break; | |
| 3076 case CPUINFO_STR_REGISTER + MIPS_CP2CR1: sprintf( info->s = cpuintrf_temp_str(), "r13r21 :%08x", mipscpu.cp2cr[ 1 ].d ); break; | |
| 3077 case CPUINFO_STR_REGISTER + MIPS_CP2CR2: sprintf( info->s = cpuintrf_temp_str(), "r22r23 :%08x", mipscpu.cp2cr[ 2 ].d ); break; | |
| 3078 case CPUINFO_STR_REGISTER + MIPS_CP2CR3: sprintf( info->s = cpuintrf_temp_str(), "r31r32 :%08x", mipscpu.cp2cr[ 3 ].d ); break; | |
| 3079 case CPUINFO_STR_REGISTER + MIPS_CP2CR4: sprintf( info->s = cpuintrf_temp_str(), "r33 :%08x", mipscpu.cp2cr[ 4 ].d ); break; | |
| 3080 case CPUINFO_STR_REGISTER + MIPS_CP2CR5: sprintf( info->s = cpuintrf_temp_str(), "trx :%08x", mipscpu.cp2cr[ 5 ].d ); break; | |
| 3081 case CPUINFO_STR_REGISTER + MIPS_CP2CR6: sprintf( info->s = cpuintrf_temp_str(), "try :%08x", mipscpu.cp2cr[ 6 ].d ); break; | |
| 3082 case CPUINFO_STR_REGISTER + MIPS_CP2CR7: sprintf( info->s = cpuintrf_temp_str(), "trz :%08x", mipscpu.cp2cr[ 7 ].d ); break; | |
| 3083 case CPUINFO_STR_REGISTER + MIPS_CP2CR8: sprintf( info->s = cpuintrf_temp_str(), "l11l12 :%08x", mipscpu.cp2cr[ 8 ].d ); break; | |
| 3084 case CPUINFO_STR_REGISTER + MIPS_CP2CR9: sprintf( info->s = cpuintrf_temp_str(), "l13l21 :%08x", mipscpu.cp2cr[ 9 ].d ); break; | |
| 3085 case CPUINFO_STR_REGISTER + MIPS_CP2CR10: sprintf( info->s = cpuintrf_temp_str(), "l22l23 :%08x", mipscpu.cp2cr[ 10 ].d ); break; | |
| 3086 case CPUINFO_STR_REGISTER + MIPS_CP2CR11: sprintf( info->s = cpuintrf_temp_str(), "l31l32 :%08x", mipscpu.cp2cr[ 11 ].d ); break; | |
| 3087 case CPUINFO_STR_REGISTER + MIPS_CP2CR12: sprintf( info->s = cpuintrf_temp_str(), "l33 :%08x", mipscpu.cp2cr[ 12 ].d ); break; | |
| 3088 case CPUINFO_STR_REGISTER + MIPS_CP2CR13: sprintf( info->s = cpuintrf_temp_str(), "rbk :%08x", mipscpu.cp2cr[ 13 ].d ); break; | |
| 3089 case CPUINFO_STR_REGISTER + MIPS_CP2CR14: sprintf( info->s = cpuintrf_temp_str(), "gbk :%08x", mipscpu.cp2cr[ 14 ].d ); break; | |
| 3090 case CPUINFO_STR_REGISTER + MIPS_CP2CR15: sprintf( info->s = cpuintrf_temp_str(), "bbk :%08x", mipscpu.cp2cr[ 15 ].d ); break; | |
| 3091 case CPUINFO_STR_REGISTER + MIPS_CP2CR16: sprintf( info->s = cpuintrf_temp_str(), "lr1lr2 :%08x", mipscpu.cp2cr[ 16 ].d ); break; | |
| 3092 case CPUINFO_STR_REGISTER + MIPS_CP2CR17: sprintf( info->s = cpuintrf_temp_str(), "lr31g1 :%08x", mipscpu.cp2cr[ 17 ].d ); break; | |
| 3093 case CPUINFO_STR_REGISTER + MIPS_CP2CR18: sprintf( info->s = cpuintrf_temp_str(), "lg2lg3 :%08x", mipscpu.cp2cr[ 18 ].d ); break; | |
| 3094 case CPUINFO_STR_REGISTER + MIPS_CP2CR19: sprintf( info->s = cpuintrf_temp_str(), "lb1lb2 :%08x", mipscpu.cp2cr[ 19 ].d ); break; | |
| 3095 case CPUINFO_STR_REGISTER + MIPS_CP2CR20: sprintf( info->s = cpuintrf_temp_str(), "lb3 :%08x", mipscpu.cp2cr[ 20 ].d ); break; | |
| 3096 case CPUINFO_STR_REGISTER + MIPS_CP2CR21: sprintf( info->s = cpuintrf_temp_str(), "rfc :%08x", mipscpu.cp2cr[ 21 ].d ); break; | |
| 3097 case CPUINFO_STR_REGISTER + MIPS_CP2CR22: sprintf( info->s = cpuintrf_temp_str(), "gfc :%08x", mipscpu.cp2cr[ 22 ].d ); break; | |
| 3098 case CPUINFO_STR_REGISTER + MIPS_CP2CR23: sprintf( info->s = cpuintrf_temp_str(), "bfc :%08x", mipscpu.cp2cr[ 23 ].d ); break; | |
| 3099 case CPUINFO_STR_REGISTER + MIPS_CP2CR24: sprintf( info->s = cpuintrf_temp_str(), "ofx :%08x", mipscpu.cp2cr[ 24 ].d ); break; | |
| 3100 case CPUINFO_STR_REGISTER + MIPS_CP2CR25: sprintf( info->s = cpuintrf_temp_str(), "ofy :%08x", mipscpu.cp2cr[ 25 ].d ); break; | |
| 3101 case CPUINFO_STR_REGISTER + MIPS_CP2CR26: sprintf( info->s = cpuintrf_temp_str(), "h :%08x", mipscpu.cp2cr[ 26 ].d ); break; | |
| 3102 case CPUINFO_STR_REGISTER + MIPS_CP2CR27: sprintf( info->s = cpuintrf_temp_str(), "dqa :%08x", mipscpu.cp2cr[ 27 ].d ); break; | |
| 3103 case CPUINFO_STR_REGISTER + MIPS_CP2CR28: sprintf( info->s = cpuintrf_temp_str(), "dqb :%08x", mipscpu.cp2cr[ 28 ].d ); break; | |
| 3104 case CPUINFO_STR_REGISTER + MIPS_CP2CR29: sprintf( info->s = cpuintrf_temp_str(), "zsf3 :%08x", mipscpu.cp2cr[ 29 ].d ); break; | |
| 3105 case CPUINFO_STR_REGISTER + MIPS_CP2CR30: sprintf( info->s = cpuintrf_temp_str(), "zsf4 :%08x", mipscpu.cp2cr[ 30 ].d ); break; | |
| 3106 case CPUINFO_STR_REGISTER + MIPS_CP2CR31: sprintf( info->s = cpuintrf_temp_str(), "flag :%08x", mipscpu.cp2cr[ 31 ].d ); break; | |
| 3107 #endif | |
| 3108 } | 2953 } |
| 3109 } | 2954 } |
| 3110 | 2955 |
| 3111 uint32 mips_get_cause(void) | 2956 uint32 mips_get_cause(void) |
| 3112 { | 2957 { |