359
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1 /*
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2 * Adplug - Replayer for many OPL2/OPL3 audio file formats.
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3 * Copyright (C) 1999, 2000, 2001 Simon Peter, <dn.tlp@gmx.net>, et al.
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4 *
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5 * This library is free software; you can redistribute it and/or
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6 * modify it under the terms of the GNU Lesser General Public
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7 * License as published by the Free Software Foundation; either
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8 * version 2.1 of the License, or (at your option) any later version.
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9 *
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10 * This library is distributed in the hope that it will be useful,
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11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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13 * Lesser General Public License for more details.
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14 *
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15 * You should have received a copy of the GNU Lesser General Public
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16 * License along with this library; if not, write to the Free Software
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17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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18 *
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19 *
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20 * realopl.cpp - Real hardware OPL, by Simon Peter (dn.tlp@gmx.net)
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21 */
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22
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23 #include <conio.h>
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24 #include "realopl.h"
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25
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26 #ifdef _MSC_VER
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27 #define INP _inp
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28 #define OUTP _outp
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29 #elif defined(__WATCOMC__)
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30 #define INP inp
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31 #define OUTP outp
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32 #endif
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33
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34 /*
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35 * chris: TODO: This isn't quite right. According to Jeff Lee's doc:
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36 *
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37 * "After writing to the register port, you must wait twelve cycles before
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38 * sending the data; after writing the data, eighty-four cycles must elapse
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39 * before any other sound card operation may be performed.
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40 *
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41 * | The AdLib manual gives the wait times in microseconds: three point three
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42 * | (3.3) microseconds for the address, and twenty-three (23) microseconds
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43 * | for the data.
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44 * |
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45 * | The most accurate method of producing the delay is to read the register
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46 * | port six times after writing to the register port, and read the register
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47 * | port thirty-five times after writing to the data port."
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48 *
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49 *
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50 * In other words, the delay constants represented by {SHORT|LONG}DELAY below
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51 * aren't given in microseconds, but rather direct reads (INB) from the Adlib
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52 * I/O ports.
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53 *
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54 * Translation: SHORTDELAY should be 6, and LONGDELAY is just fine. :-)
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55 */
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56
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57 #define SHORTDELAY 6 // short delay in I/O port-reads after OPL hardware output
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58 #define LONGDELAY 35 // long delay in I/O port-reads after OPL hardware output
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59
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60 // the 9 operators as expected by the OPL2
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61 static const unsigned char op_table[9] = {0x00, 0x01, 0x02, 0x08, 0x09, 0x0a, 0x10, 0x11, 0x12};
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62
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63 CRealopl::CRealopl(unsigned short initport): adlport(initport), hardvol(0), bequiet(false), nowrite(false)
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64 {
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65 for(int i=0;i<22;i++) {
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66 hardvols[i][0] = 0;
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67 hardvols[i][1] = 0;
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68 }
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69 }
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70
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71 bool CRealopl::detect()
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72 {
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73 unsigned char stat1,stat2,i;
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74
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75 hardwrite(4,0x60); hardwrite(4,0x80);
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76 stat1 = INP(adlport);
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77 hardwrite(2,0xff); hardwrite(4,0x21);
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78 for(i=0;i<80;i++) // wait for adlib
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79 INP(adlport);
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80 stat2 = INP(adlport);
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81 hardwrite(4,0x60); hardwrite(4,0x80);
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82
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83 if(((stat1 & 0xe0) == 0) && ((stat2 & 0xe0) == 0xc0))
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84 return true;
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85 else
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86 return false;
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87 }
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88
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89 void CRealopl::setvolume(int volume)
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90 {
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91 int i;
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92
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93 hardvol = volume;
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94 for(i=0;i<9;i++) {
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95 hardwrite(0x43+op_table[i],((hardvols[op_table[i]+3][0] & 63) + volume) > 63 ? 63 : hardvols[op_table[i]+3][0] + volume);
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96 if(hardvols[i][1] & 1) // modulator too?
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97 hardwrite(0x40+op_table[i],((hardvols[op_table[i]][0] & 63) + volume) > 63 ? 63 : hardvols[op_table[i]][0] + volume);
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98 }
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99 }
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100
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101 void CRealopl::setquiet(bool quiet)
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102 {
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103 bequiet = quiet;
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104
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105 if(quiet) {
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106 oldvol = hardvol;
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107 setvolume(63);
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108 } else
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109 setvolume(oldvol);
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110 }
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111
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112 void CRealopl::hardwrite(int reg, int val)
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113 {
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114 int i;
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115
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116 OUTP(adlport,reg); // set register
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117 for(i=0;i<SHORTDELAY;i++) // wait for adlib
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118 INP(adlport);
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119 OUTP(adlport+1,val); // set value
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120 for(i=0;i<LONGDELAY;i++) // wait for adlib
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121 INP(adlport);
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122 }
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123
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124 void CRealopl::write(int reg, int val)
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125 {
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126 int i;
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127
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128 if(nowrite)
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129 return;
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130
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131 if(bequiet && (reg >= 0xb0 && reg <= 0xb8)) // filter all key-on commands
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132 val &= ~32;
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133 if(reg >= 0x40 && reg <= 0x55) // cache volumes
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134 hardvols[reg-0x40][0] = val;
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135 if(reg >= 0xc0 && reg <= 0xc8)
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136 hardvols[reg-0xc0][1] = val;
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137 if(hardvol) // reduce volume
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138 for(i=0;i<9;i++) {
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139 if(reg == 0x43 + op_table[i])
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140 val = ((val & 63) + hardvol) > 63 ? 63 : val + hardvol;
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141 else
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142 if((reg == 0x40 + op_table[i]) && (hardvols[i][1] & 1))
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143 val = ((val & 63) + hardvol) > 63 ? 63 : val + hardvol;
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144 }
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145
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146 hardwrite(reg,val);
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147 }
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148
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149 void CRealopl::init()
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150 {
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151 int i;
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152
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153 for (i=0;i<9;i++) { // stop instruments
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154 hardwrite(0xb0 + i,0); // key off
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155 hardwrite(0x80 + op_table[i],0xff); // fastest release
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156 }
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157 hardwrite(0xbd,0); // clear misc. register
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158 }
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