annotate lisp/url/.cvsignore @ 93195:096de5eb1d54

(verilog-auto-output) (verilog-auto-input, verilog-auto-inout, verilog-auto) (verilog-delete-auto): Add optional regular expression to AUTOINPUT/AUTOOUTPUT/AUTOINOUT. (verilog-signals-matching-regexp): New internal function for signal matching.
author Dan Nicolaescu <dann@ics.uci.edu>
date Tue, 25 Mar 2008 15:45:49 +0000
parents 3fb37923e567
children
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54695
3fb37923e567 Initial revision
Stefan Monnier <monnier@iro.umontreal.ca>
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1 Makefile
3fb37923e567 Initial revision
Stefan Monnier <monnier@iro.umontreal.ca>
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2 auto-autoloads.el
3fb37923e567 Initial revision
Stefan Monnier <monnier@iro.umontreal.ca>
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3 custom-load.el
3fb37923e567 Initial revision
Stefan Monnier <monnier@iro.umontreal.ca>
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4 url-auto.el