79545
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1 ;; verilog-mode.el --- major mode for editing verilog source in Emacs
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2 ;;
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3 ;; $Id: verilog-mode.el 377 2007-12-07 17:21:25Z wsnyder $
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4
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5 ;; Copyright (C) 1996-2007 Free Software Foundation, Inc.
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6
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7 ;; Author: Michael McNamara (mac@verilog.com)
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8 ;; http://www.verilog.com
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9 ;;
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10 ;; AUTO features, signal, modsig; by: Wilson Snyder
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11 ;; (wsnyder@wsnyder.org)
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12 ;; http://www.veripool.com
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13 ;; Keywords: languages
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14
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15 ;; This program is free software; you can redistribute it and/or modify
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16 ;; it under the terms of the GNU General Public License as published by
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17 ;; the Free Software Foundation; either version 2 of the License, or
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18 ;; (at your option) any later version.
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19
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20 ;; This program is distributed in the hope that it will be useful,
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21 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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22 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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23 ;; GNU General Public License for more details.
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24
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25 ;; You should have received a copy of the GNU General Public License
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26 ;; along with this program; if not, write to the Free Software
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27 ;; Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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28
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29 ;;; Commentary:
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30
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31 ;; This mode borrows heavily from the Pascal-mode and the cc-mode of emacs
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32
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33 ;; USAGE
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34 ;; =====
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35
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36 ;; A major mode for editing Verilog HDL source code. When you have
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37 ;; entered Verilog mode, you may get more info by pressing C-h m. You
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38 ;; may also get online help describing various functions by: C-h f
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39 ;; <Name of function you want described>
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40
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41 ;; KNOWN BUGS / BUG REPORTS
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42 ;; =======================
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43
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44 ;; Verilog is a rapidly evolving language, and hence this mode is
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45 ;; under continuous development. Hence this is beta code, and likely
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46 ;; has bugs. Please report any and all bugs to me at mac@verilog.com.
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47 ;; Please use verilog-submit-bug-report to submit a report; type C-c
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48 ;; C-b to invoke this and as a result I will have a much easier time
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49 ;; of reproducing the bug you find, and hence fixing it.
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50
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51 ;; INSTALLING THE MODE
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52 ;; ===================
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53
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54 ;; An older version of this mode may be already installed as a part of
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55 ;; your environment, and one method of updating would be to update
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56 ;; your emacs environment. Sometimes this is difficult for local
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57 ;; political/control reasons, and hence you can always install a
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58 ;; private copy (or even a shared copy) which overrides the system
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59 ;; default.
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60
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61 ;; You can get step by step help in installing this file by going to
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62 ;; <http://www.verilog.com/emacs_install.html>
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63
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64 ;; The short list of installation instructions are: To set up
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65 ;; automatic verilog mode, put this file in your load path, and put
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66 ;; the following in code (please un comment it first!) in your
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67 ;; .emacs, or in your site's site-load.el
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68
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69 ; (autoload 'verilog-mode "verilog-mode" "Verilog mode" t )
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70 ; (setq auto-mode-alist (cons '("\\.v\\'" . verilog-mode) auto-mode-alist))
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71 ; (setq auto-mode-alist (cons '("\\.dv\\'" . verilog-mode) auto-mode-alist))
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72
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73 ;; If you want to customize Verilog mode to fit your needs better,
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74 ;; you may add these lines (the values of the variables presented
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75 ;; here are the defaults). Note also that if you use an emacs that
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76 ;; supports custom, it's probably better to use the custom menu to
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77 ;; edit these.
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78 ;;
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79 ;; Be sure to examine at the help for verilog-auto, and the other
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80 ;; verilog-auto-* functions for some major coding time savers.
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81 ;;
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82 ; ;; User customization for Verilog mode
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83 ; (setq verilog-indent-level 3
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84 ; verilog-indent-level-module 3
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85 ; verilog-indent-level-declaration 3
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86 ; verilog-indent-level-behavioral 3
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87 ; verilog-indent-level-directive 1
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88 ; verilog-case-indent 2
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89 ; verilog-auto-newline t
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90 ; verilog-auto-indent-on-newline t
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91 ; verilog-tab-always-indent t
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92 ; verilog-auto-endcomments t
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93 ; verilog-minimum-comment-distance 40
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94 ; verilog-indent-begin-after-if t
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95 ; verilog-auto-lineup '(all)
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96 ; verilog-highlight-p1800-keywords nil
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97 ; verilog-linter "my_lint_shell_command"
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98 ; )
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99
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100 ;;
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101
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102 ;;; History:
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103 ;;
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104 ;;
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105 ;;; Code:
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106
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107 (provide 'verilog-mode)
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108
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109 ;; This variable will always hold the version number of the mode
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110 (defconst verilog-mode-version (substring "$$Revision: 377 $$" 12 -3)
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111 "Version of this verilog mode.")
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112 (defconst verilog-mode-release-date (substring "$$Date: 2007-12-07 12:21:25 -0500 (Fri, 07 Dec 2007) $$" 8 -3)
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113 "Version of this verilog mode.")
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114
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115 (defun verilog-version ()
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116 "Inform caller of the version of this file."
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117 (interactive)
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118 (message (concat "Using verilog-mode version " verilog-mode-version) ))
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119
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120 ;; Insure we have certain packages, and deal with it if we don't
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121 (if (fboundp 'eval-when-compile)
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122 (eval-when-compile
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123 (require 'verilog-mode)
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124 (condition-case nil
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125 (require 'imenu)
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126 (error nil))
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127 (condition-case nil
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128 (require 'reporter)
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129 (error nil))
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130 (condition-case nil
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131 (require 'easymenu)
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132 (error nil))
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133 (condition-case nil
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134 (require 'regexp-opt)
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135 (error nil))
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136 (condition-case nil
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137 (load "skeleton") ;; bug in 19.28 through 19.30 skeleton.el, not provided.
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138 (error nil))
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139 (condition-case nil
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140 (require 'vc)
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141 (error nil))
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142 (condition-case nil
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143 (if (fboundp 'when)
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144 nil ;; fab
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145 (defmacro when (var &rest body)
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146 (` (cond ( (, var) (,@ body))))))
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147 (error nil))
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148 (condition-case nil
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149 (if (fboundp 'unless)
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150 nil ;; fab
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151 (defmacro unless (var &rest body)
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152 (` (if (, var) nil (,@ body)))))
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153 (error nil))
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154 (condition-case nil
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155 (if (fboundp 'store-match-data)
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156 nil ;; fab
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157 (defmacro store-match-data (&rest args) nil))
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158 (error nil))
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159 (condition-case nil
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160 (if (boundp 'current-menubar)
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161 nil ;; great
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162 (progn
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163 (defmacro set-buffer-menubar (&rest args) nil)
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164 (defmacro add-submenu (&rest args) nil))
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165 )
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166 (error nil))
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167 (condition-case nil
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168 (if (fboundp 'zmacs-activate-region)
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169 nil ;; great
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170 (defmacro zmacs-activate-region (&rest args) nil))
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171 (error nil))
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172 (condition-case nil
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173 (if (fboundp 'char-before)
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174 nil ;; great
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175 (defmacro char-before (&rest body)
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176 (` (char-after (1- (point))))))
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177 (error nil))
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178 ;; Requires to define variables that would be "free" warnings
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179 (condition-case nil
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180 (require 'font-lock)
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181 (error nil))
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182 (condition-case nil
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183 (require 'compile)
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184 (error nil))
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185 (condition-case nil
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186 (require 'custom)
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187 (error nil))
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188 (condition-case nil
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189 (require 'dinotrace)
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190 (error nil))
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191 (condition-case nil
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192 (if (fboundp 'dinotrace-unannotate-all)
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193 nil ;; great
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194 (defun dinotrace-unannotate-all (&rest args) nil))
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195 (error nil))
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196 (condition-case nil
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197 (if (fboundp 'customize-apropos)
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198 nil ;; great
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199 (defun customize-apropos (&rest args) nil))
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200 (error nil))
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201 (condition-case nil
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202 (if (fboundp 'match-string-no-properties)
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203 nil ;; great
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204 (defsubst match-string-no-properties (num &optional string)
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205 "Return string of text matched by last search, without text properties.
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206 NUM specifies which parenthesized expression in the last regexp.
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207 Value is nil if NUMth pair didn't match, or there were less than NUM pairs.
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208 Zero means the entire text matched by the whole regexp or whole string.
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209 STRING should be given if the last search was by `string-match' on STRING."
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210 (if (match-beginning num)
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211 (if string
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212 (let ((result
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213 (substring string (match-beginning num) (match-end num))))
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214 (set-text-properties 0 (length result) nil result)
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215 result)
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216 (buffer-substring-no-properties (match-beginning num)
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217 (match-end num)
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218 (current-buffer)
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219 )))))
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220 (error nil))
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221 (if (and (featurep 'custom) (fboundp 'custom-declare-variable))
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222 nil ;; We've got what we needed
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223 ;; We have the old custom-library, hack around it!
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224 (defmacro defgroup (&rest args) nil)
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225 (defmacro customize (&rest args)
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226 (message "Sorry, Customize is not available with this version of emacs"))
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227 (defmacro defcustom (var value doc &rest args)
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228 (` (defvar (, var) (, value) (, doc))))
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229 )
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230 (if (fboundp 'defface)
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231 nil ; great!
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232 (defmacro defface (var value doc &rest args)
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233 (` (make-face (, var))))
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234 )
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235
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236 (if (and (featurep 'custom) (fboundp 'customize-group))
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237 nil ;; We've got what we needed
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238 ;; We have an intermediate custom-library, hack around it!
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239 (defmacro customize-group (var &rest args)
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240 (`(customize (, var) )))
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241 )
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242
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243 ))
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244 ;; Provide a regular expression optimization routine, using regexp-opt
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245 ;; if provided by the user's elisp libraries
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246 (eval-and-compile
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247 (if (fboundp 'regexp-opt)
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248 ;; regexp-opt is defined, does it take 3 or 2 arguments?
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249 (if (fboundp 'function-max-args)
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250 (case (function-max-args `regexp-opt)
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251 ( 3 ;; It takes 3
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252 (condition-case nil ; Hide this defun from emacses
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253 ;with just a two input regexp
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254 (defun verilog-regexp-opt (a b)
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255 "Deal with differing number of required arguments for `regexp-opt'.
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256 Call 'regexp-opt' on A and B."
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257 (regexp-opt a b 't)
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258 )
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259 (error nil))
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260 )
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261 ( 2 ;; It takes 2
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262 (defun verilog-regexp-opt (a b)
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263 "Call 'regexp-opt' on A and B."
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264 (regexp-opt a b))
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265 )
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266 ( t nil))
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267 ;; We can't tell; assume it takes 2
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268 (defun verilog-regexp-opt (a b)
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269 "Call 'regexp-opt' on A and B."
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270 (regexp-opt a b))
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271 )
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272 ;; There is no regexp-opt, provide our own
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273 (defun verilog-regexp-opt (strings &optional paren shy)
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274 (let ((open (if paren "\\(" "")) (close (if paren "\\)" "")))
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275 (concat open (mapconcat 'regexp-quote strings "\\|") close)))
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276 ))
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277
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278 (eval-when-compile
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279 (defun verilog-regexp-words (a)
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280 "Call 'regexp-opt' with word delimiters."
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281 (concat "\\<" (verilog-regexp-opt a t) "\\>")))
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282
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283 (defun verilog-regexp-words (a)
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284 "Call 'regexp-opt' with word delimiters for the words A."
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285 (concat "\\<" (verilog-regexp-opt a t) "\\>"))
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286
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287 (defun verilog-customize ()
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288 "Link to customize screen for Verilog."
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289 (interactive)
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290 (customize-group 'verilog-mode))
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291
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292 (defun verilog-font-customize ()
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293 "Link to customize fonts used for Verilog."
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294 (interactive)
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295 (customize-apropos "font-lock-*" 'faces))
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296
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297 (defgroup verilog-mode nil
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298 "Facilitates easy editing of Verilog source text"
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299 :group 'languages)
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300
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301 ; (defgroup verilog-mode-fonts nil
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302 ; "Facilitates easy customization fonts used in Verilog source text"
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303 ; :link '(customize-apropos "font-lock-*" 'faces)
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304 ; :group 'verilog-mode)
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305
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306 (defgroup verilog-mode-indent nil
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307 "Customize indentation and highlighting of verilog source text"
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308 :group 'verilog-mode)
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309
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310 (defgroup verilog-mode-actions nil
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311 "Customize actions on verilog source text"
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312 :group 'verilog-mode)
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313
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314 (defgroup verilog-mode-auto nil
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315 "Customize AUTO actions when expanding verilog source text"
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316 :group 'verilog-mode)
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317
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318 (defcustom verilog-linter
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319 "echo 'No verilog-linter set, see \"M-x describe-variable verilog-linter\"'"
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320 "*Unix program and arguments to call to run a lint checker on verilog source.
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321 Depending on the `verilog-set-compile-command', this may be invoked when
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322 you type \\[compile]. When the compile completes, \\[next-error] will take
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323 you to the next lint error."
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324 :type 'string
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325 :group 'verilog-mode-actions)
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326
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327 (defcustom verilog-coverage
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328 "echo 'No verilog-coverage set, see \"M-x describe-variable verilog-coverage\"'"
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329 "*Program and arguments to use to annotate for coverage verilog source.
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330 Depending on the `verilog-set-compile-command', this may be invoked when
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331 you type \\[compile]. When the compile completes, \\[next-error] will take
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332 you to the next lint error."
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333 :type 'string
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334 :group 'verilog-mode-actions)
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335
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336 (defcustom verilog-simulator
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337 "echo 'No verilog-simulator set, see \"M-x describe-variable verilog-simulator\"'"
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338 "*Program and arguments to use to interpret verilog source.
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339 Depending on the `verilog-set-compile-command', this may be invoked when
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340 you type \\[compile]. When the compile completes, \\[next-error] will take
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341 you to the next lint error."
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342 :type 'string
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343 :group 'verilog-mode-actions)
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344
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345 (defcustom verilog-compiler
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346 "echo 'No verilog-compiler set, see \"M-x describe-variable verilog-compiler\"'"
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347 "*Program and arguments to use to compile verilog source.
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348 Depending on the `verilog-set-compile-command', this may be invoked when
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349 you type \\[compile]. When the compile completes, \\[next-error] will take
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350 you to the next lint error."
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351 :type 'string
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352 :group 'verilog-mode-actions)
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353
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354 (defvar verilog-tool 'verilog-linter
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355 "Which tool to use for building compiler-command.
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356 Either nil, `verilog-linter, `verilog-coverage, `verilog-simulator, or
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357 `verilog-compiler. Alternatively use the \"Choose Compilation Action\"
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358 menu. See `verilog-set-compile-command' for more information.")
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359
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360 (defcustom verilog-highlight-translate-off nil
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361 "*Non-nil means background-highlight code excluded from translation.
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362 That is, all code between \"// synopsys translate_off\" and
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363 \"// synopsys translate_on\" is highlighted using a different background color
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364 \(face `verilog-font-lock-translate-off-face').
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365
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366 Note: This will slow down on-the-fly fontification (and thus editing).
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367
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368 Note: Activate the new setting in a Verilog buffer by re-fontifying it (menu
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369 entry \"Fontify Buffer\"). XEmacs: turn off and on font locking."
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370 :type 'boolean
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371 :group 'verilog-mode-indent)
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372
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373 (defcustom verilog-indent-level 3
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374 "*Indentation of Verilog statements with respect to containing block."
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375 :group 'verilog-mode-indent
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376 :type 'integer)
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377
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378 (defcustom verilog-indent-level-module 3
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379 "*Indentation of Module level Verilog statements. (eg always, initial)
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380 Set to 0 to get initial and always statements lined up on the left side of
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381 your screen."
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382 :group 'verilog-mode-indent
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383 :type 'integer)
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384
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385 (defcustom verilog-indent-level-declaration 3
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386 "*Indentation of declarations with respect to containing block.
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387 Set to 0 to get them list right under containing block."
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388 :group 'verilog-mode-indent
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389 :type 'integer)
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390
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391 (defcustom verilog-indent-declaration-macros nil
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392 "*How to treat macro expansions in a declaration.
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393 If nil, indent as:
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394 input [31:0] a;
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395 input `CP;
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396 output c;
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397 If non nil, treat as:
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398 input [31:0] a;
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399 input `CP ;
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400 output c;"
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401 :group 'verilog-mode-indent
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402 :type 'boolean)
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403
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404 (defcustom verilog-indent-lists t
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405 "*How to treat indenting items in a list.
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406 If t (the default), indent as:
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407 always @( posedge a or
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408 reset ) begin
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409
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410 If nil, treat as:
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411 always @( posedge a or
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412 reset ) begin"
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413 :group 'verilog-mode-indent
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414 :type 'boolean)
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415
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416 (defcustom verilog-indent-level-behavioral 3
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417 "*Absolute indentation of first begin in a task or function block.
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418 Set to 0 to get such code to start at the left side of the screen."
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419 :group 'verilog-mode-indent
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420 :type 'integer)
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421
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422 (defcustom verilog-indent-level-directive 1
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423 "*Indentation to add to each level of `ifdef declarations.
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424 Set to 0 to have all directives start at the left side of the screen."
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425 :group 'verilog-mode-indent
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426 :type 'integer)
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427
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428 (defcustom verilog-cexp-indent 2
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429 "*Indentation of Verilog statements split across lines."
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430 :group 'verilog-mode-indent
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431 :type 'integer)
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432
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433 (defcustom verilog-case-indent 2
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434 "*Indentation for case statements."
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435 :group 'verilog-mode-indent
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436 :type 'integer)
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437
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438 (defcustom verilog-auto-newline t
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439 "*True means automatically newline after semicolons."
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440 :group 'verilog-mode-indent
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441 :type 'boolean)
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442
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443 (defcustom verilog-auto-indent-on-newline t
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444 "*True means automatically indent line after newline."
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445 :group 'verilog-mode-indent
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446 :type 'boolean)
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447
|
|
448 (defcustom verilog-tab-always-indent t
|
|
449 "*True means TAB should always re-indent the current line.
|
|
450 Nil means TAB will only reindent when at the beginning of the line."
|
|
451 :group 'verilog-mode-indent
|
|
452 :type 'boolean)
|
|
453
|
|
454 (defcustom verilog-tab-to-comment nil
|
|
455 "*True means TAB moves to the right hand column in preparation for a comment."
|
|
456 :group 'verilog-mode-actions
|
|
457 :type 'boolean)
|
|
458
|
|
459 (defcustom verilog-indent-begin-after-if t
|
|
460 "*If true, indent begin statements following if, else, while, for and repeat.
|
|
461 Otherwise, line them up."
|
|
462 :group 'verilog-mode-indent
|
|
463 :type 'boolean )
|
|
464
|
|
465
|
|
466 (defcustom verilog-align-ifelse nil
|
|
467 "*If true, align `else' under matching `if'.
|
|
468 Otherwise else is lined up with first character on line holding matching if."
|
|
469 :group 'verilog-mode-indent
|
|
470 :type 'boolean )
|
|
471
|
|
472 (defcustom verilog-minimum-comment-distance 10
|
|
473 "*Minimum distance (in lines) between begin and end required before a comment.
|
|
474 Setting this variable to zero results in every end acquiring a comment; the
|
|
475 default avoids too many redundant comments in tight quarters"
|
|
476 :group 'verilog-mode-indent
|
|
477 :type 'integer)
|
|
478
|
|
479 (defcustom verilog-auto-lineup '(declaration)
|
|
480 "*Algorithm for lining up statements on multiple lines.
|
|
481
|
|
482 If this list contains the symbol 'all', then all line ups described below
|
|
483 are done.
|
|
484
|
|
485 If this list contains the symbol 'declaration', then declarations are lined up
|
|
486 with any preceding declarations, taking into account widths and the like, so
|
|
487 for example the code:
|
|
488 reg [31:0] a;
|
|
489 reg b;
|
|
490 would become
|
|
491 reg [31:0] a;
|
|
492 reg b;
|
|
493
|
|
494 If this list contains the symbol 'assignment', then assignments are lined up
|
|
495 with any preceding assignments, so for example the code
|
|
496 a_long_variable = b + c;
|
|
497 d = e + f;
|
|
498 would become
|
|
499 a_long_variable = b + c;
|
|
500 d = e + f;"
|
|
501
|
|
502 ;; The following is not implemented:
|
|
503 ;If this list contains the symbol 'case', then case items are lined up
|
|
504 ;with any preceding case items, so for example the code
|
|
505 ; case (a) begin
|
|
506 ; a_long_state : a = 3;
|
|
507 ; b: a = 4;
|
|
508 ; endcase
|
|
509 ;would become
|
|
510 ; case (a) begin
|
|
511 ; a_long_state : a = 3;
|
|
512 ; b : a = 4;
|
|
513 ; endcase
|
|
514 ;
|
|
515
|
|
516 :group 'verilog-mode-indent
|
|
517 :type 'list )
|
|
518
|
|
519 (defcustom verilog-highlight-p1800-keywords nil
|
|
520 "*If true highlight words newly reserved by IEEE-1800 in
|
|
521 verilog-font-lock-p1800-face in order to gently suggest changing where
|
|
522 these words are used as variables to something else. Nil means highlight
|
|
523 these words as appropriate for the SystemVerilog IEEE-1800 standard. Note
|
|
524 that changing this will require restarting emacs to see the effect as font
|
|
525 color choices are cached by emacs"
|
|
526 :group 'verilog-mode-indent
|
|
527 :type 'boolean)
|
|
528
|
|
529 (defcustom verilog-auto-endcomments t
|
|
530 "*True means insert a comment /* ... */ after 'end's.
|
|
531 The name of the function or case will be set between the braces."
|
|
532 :group 'verilog-mode-actions
|
|
533 :type 'boolean )
|
|
534
|
|
535 (defcustom verilog-auto-read-includes nil
|
|
536 "*True means to automatically read includes before AUTOs.
|
|
537 This will do a `verilog-read-defines' and `verilog-read-includes' before
|
|
538 each AUTO expansion. This makes it easier to embed defines and includes,
|
|
539 but can result in very slow reading times if there are many or large
|
|
540 include files."
|
|
541 :group 'verilog-mode-actions
|
|
542 :type 'boolean )
|
|
543
|
|
544 (defcustom verilog-auto-save-policy nil
|
|
545 "*Non-nil indicates action to take when saving a Verilog buffer with AUTOs.
|
|
546 A value of `force' will always do a \\[verilog-auto] automatically if
|
|
547 needed on every save. A value of `detect' will do \\[verilog-auto]
|
|
548 automatically when it thinks necessary. A value of `ask' will query the
|
|
549 user when it thinks updating is needed.
|
|
550
|
|
551 You should not rely on the 'ask or 'detect policies, they are safeguards
|
|
552 only. They do not detect when AUTOINSTs need to be updated because a
|
|
553 sub-module's port list has changed."
|
|
554 :group 'verilog-mode-actions
|
|
555 :type '(choice (const nil) (const ask) (const detect) (const force)))
|
|
556
|
|
557 (defcustom verilog-auto-star-expand t
|
|
558 "*Non-nil indicates to expand a SystemVerilog .* instance ports.
|
|
559 They will be expanded in the same way as if there was a AUTOINST in the
|
|
560 instantiation. See also `verilog-auto-star' and `verilog-auto-star-save'."
|
|
561 :group 'verilog-mode-actions
|
|
562 :type 'boolean)
|
|
563
|
|
564 (defcustom verilog-auto-star-save nil
|
|
565 "*Non-nil indicates to save to disk SystemVerilog .* instance expansions.
|
|
566 Nil indicates direct connections will be removed before saving. Only
|
|
567 meaningful to those created due to `verilog-auto-star-expand' being set.
|
|
568
|
|
569 Instead of setting this, you may want to use /*AUTOINST*/, which will
|
|
570 always be saved."
|
|
571 :group 'verilog-mode-actions
|
|
572 :type 'boolean)
|
|
573
|
|
574 (defvar verilog-auto-update-tick nil
|
|
575 "Modification tick at which autos were last performed.")
|
|
576
|
|
577 (defvar verilog-auto-last-file-locals nil
|
|
578 "Text from file-local-variables during last evaluation.")
|
|
579
|
|
580 (defvar verilog-error-regexp-add-didit nil)
|
|
581 (defvar verilog-error-regexp nil)
|
|
582 (setq verilog-error-regexp-add-didit nil
|
|
583 verilog-error-regexp
|
|
584 '(
|
|
585 ; SureLint
|
|
586 ;; ("[^\n]*\\[\\([^:]+\\):\\([0-9]+\\)\\]" 1 2)
|
|
587 ; Most SureFire tools
|
|
588 ("\\(WARNING\\|ERROR\\|INFO\\)[^:]*: \\([^,]+\\), \\(line \\|\\)\\([0-9]+\\):" 2 4 )
|
|
589 ("\
|
|
590 \\([a-zA-Z]?:?[^:( \t\n]+\\)[:(][ \t]*\\([0-9]+\\)\\([) \t]\\|\
|
|
591 :\\([^0-9\n]\\|\\([0-9]+:\\)\\)\\)" 1 2 5)
|
|
592 ; xsim
|
|
593 ; Error! in file /homes/mac/Axis/Xsim/test.v at line 13 [OBJ_NOT_DECLARED]
|
|
594 ("\\(Error\\|Warning\\).*in file (\\([^ \t]+\\) at line *\\([0-9]+\\))" 2 3)
|
|
595 ; vcs
|
|
596 ("\\(Error\\|Warning\\):[^(]*(\\([^ \t]+\\) line *\\([0-9]+\\))" 2 3)
|
|
597 ("Warning:.*(port.*(\\([^ \t]+\\) line \\([0-9]+\\))" 1 2)
|
|
598 ("\\(Error\\|Warning\\):[\n.]*\\([^ \t]+\\) *\\([0-9]+\\):" 2 3)
|
|
599 ("syntax error:.*\n\\([^ \t]+\\) *\\([0-9]+\\):" 1 2)
|
|
600 ; Verilator
|
|
601 ("%?\\(Error\\|Warning\\)\\(-[^:]+\\|\\):[\n ]*\\([^ \t:]+\\):\\([0-9]+\\):" 3 4)
|
|
602 ("%?\\(Error\\|Warning\\)\\(-[^:]+\\|\\):[\n ]*\\([^ \t:]+\\):\\([0-9]+\\):" 3 4)
|
|
603 ; vxl
|
|
604 ("\\(Error\\|Warning\\)!.*\n?.*\"\\([^\"]+\\)\", \\([0-9]+\\)" 2 3)
|
|
605 ("([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+\\([0-9]+\\):.*$" 1 2) ; vxl
|
|
606 ("([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+line[ \t]+\\([0-9]+\\):.*$" 1 2)
|
|
607 ; nc-verilog
|
|
608 (".*\\*[WE],[0-9A-Z]+ (\\([^ \t,]+\\),\\([0-9]+\\)|" 1 2)
|
|
609 ; Leda
|
|
610 ("In file \\([^ \t]+\\)[ \t]+line[ \t]+\\([0-9]+\\):\n[^\n]*\n[^\n]*\n\\[\\(Warning\\|Error\\|Failure\\)\\][^\n]*" 1 2)
|
|
611 )
|
|
612 ; "*List of regexps for verilog compilers, like verilint. See compilation-error-regexp-alist for the formatting."
|
|
613 )
|
|
614
|
|
615 (defvar verilog-error-font-lock-keywords
|
|
616 '(
|
|
617 ("[^\n]*\\[\\([^:]+\\):\\([0-9]+\\)\\]" 1 bold t)
|
|
618 ("[^\n]*\\[\\([^:]+\\):\\([0-9]+\\)\\]" 2 bold t)
|
|
619
|
|
620 ("\\(WARNING\\|ERROR\\|INFO\\): \\([^,]+\\), line \\([0-9]+\\):" 2 bold t)
|
|
621 ("\\(WARNING\\|ERROR\\|INFO\\): \\([^,]+\\), line \\([0-9]+\\):" 3 bold t)
|
|
622
|
|
623 ("\
|
|
624 \\([a-zA-Z]?:?[^:( \t\n]+\\)[:(][ \t]*\\([0-9]+\\)\\([) \t]\\|\
|
|
625 :\\([^0-9\n]\\|\\([0-9]+:\\)\\)\\)" 1 bold t)
|
|
626 ("\
|
|
627 \\([a-zA-Z]?:?[^:( \t\n]+\\)[:(][ \t]*\\([0-9]+\\)\\([) \t]\\|\
|
|
628 :\\([^0-9\n]\\|\\([0-9]+:\\)\\)\\)" 1 bold t)
|
|
629
|
|
630 ("\\(Error\\|Warning\\):[^(]*(\\([^ \t]+\\) line *\\([0-9]+\\))" 2 bold t)
|
|
631 ("\\(Error\\|Warning\\):[^(]*(\\([^ \t]+\\) line *\\([0-9]+\\))" 3 bold t)
|
|
632
|
|
633 ("%?\\(Error\\|Warning\\)\\(-[^:]+\\|\\):[\n ]*\\([^ \t:]+\\):\\([0-9]+\\):" 3 bold t)
|
|
634 ("%?\\(Error\\|Warning\\)\\(-[^:]+\\|\\):[\n ]*\\([^ \t:]+\\):\\([0-9]+\\):" 4 bold t)
|
|
635
|
|
636 ("Warning:.*(port.*(\\([^ \t]+\\) line \\([0-9]+\\))" 1 bold t)
|
|
637 ("Warning:.*(port.*(\\([^ \t]+\\) line \\([0-9]+\\))" 1 bold t)
|
|
638
|
|
639 ("\\(Error\\|Warning\\):[\n.]*\\([^ \t]+\\) *\\([0-9]+\\):" 2 bold t)
|
|
640 ("\\(Error\\|Warning\\):[\n.]*\\([^ \t]+\\) *\\([0-9]+\\):" 3 bold t)
|
|
641
|
|
642 ("syntax error:.*\n\\([^ \t]+\\) *\\([0-9]+\\):" 1 bold t)
|
|
643 ("syntax error:.*\n\\([^ \t]+\\) *\\([0-9]+\\):" 2 bold t)
|
|
644 ; vxl
|
|
645 ("\\(Error\\|Warning\\)!.*\n?.*\"\\([^\"]+\\)\", \\([0-9]+\\)" 2 bold t)
|
|
646 ("\\(Error\\|Warning\\)!.*\n?.*\"\\([^\"]+\\)\", \\([0-9]+\\)" 2 bold t)
|
|
647
|
|
648 ("([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+\\([0-9]+\\):.*$" 1 bold t)
|
|
649 ("([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+\\([0-9]+\\):.*$" 2 bold t)
|
|
650
|
|
651 ("([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+line[ \t]+\\([0-9]+\\):.*$" 1 bold t)
|
|
652 ("([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+line[ \t]+\\([0-9]+\\):.*$" 2 bold t)
|
|
653 ; nc-verilog
|
|
654 (".*[WE],[0-9A-Z]+ (\\([^ \t,]+\\),\\([0-9]+\\)|" 1 bold t)
|
|
655 (".*[WE],[0-9A-Z]+ (\\([^ \t,]+\\),\\([0-9]+\\)|" 2 bold t)
|
|
656 ; Leda
|
|
657 ("In file \\([^ \t]+\\)[ \t]+line[ \t]+\\([0-9]+\\):\n[^\n]*\n[^\n]*\n\\[\\(Warning\\|Error\\|Failure\\)\\][^\n]*" 1 bold t)
|
|
658 ("In file \\([^ \t]+\\)[ \t]+line[ \t]+\\([0-9]+\\):\n[^\n]*\n[^\n]*\n\\[\\(Warning\\|Error\\|Failure\\)\\][^\n]*" 2 bold t)
|
|
659 )
|
|
660 "*Keywords to also highlight in Verilog *compilation* buffers."
|
|
661 )
|
|
662
|
|
663 (defcustom verilog-library-flags '("")
|
|
664 "*List of standard Verilog arguments to use for /*AUTOINST*/.
|
|
665 These arguments are used to find files for `verilog-auto', and match
|
|
666 the flags accepted by a standard Verilog-XL simulator.
|
|
667
|
|
668 -f filename Reads more `verilog-library-flags' from the filename.
|
|
669 +incdir+dir Adds the directory to `verilog-library-directories'.
|
|
670 -Idir Adds the directory to `verilog-library-directories'.
|
|
671 -y dir Adds the directory to `verilog-library-directories'.
|
|
672 +libext+.v Adds the extensions to `verilog-library-extensions'.
|
|
673 -v filename Adds the filename to `verilog-library-files'.
|
|
674
|
|
675 filename Adds the filename to `verilog-library-files'.
|
|
676 This is not recommended, -v is a better choice.
|
|
677
|
|
678 You might want these defined in each file; put at the *END* of your file
|
|
679 something like:
|
|
680
|
|
681 // Local Variables:
|
|
682 // verilog-library-flags:(\"-y dir -y otherdir\")
|
|
683 // End:
|
|
684
|
|
685 Verilog-mode attempts to detect changes to this local variable, but they
|
|
686 are only insured to be correct when the file is first visited. Thus if you
|
|
687 have problems, use \\[find-alternate-file] RET to have these take effect.
|
|
688
|
|
689 See also the variables mentioned above."
|
|
690 :group 'verilog-mode-auto
|
|
691 :type '(repeat string))
|
|
692
|
|
693 (defcustom verilog-library-directories '(".")
|
|
694 "*List of directories when looking for files for /*AUTOINST*/.
|
|
695 The directory may be relative to the current file, or absolute.
|
|
696 Environment variables are also expanded in the directory names.
|
|
697 Having at least the current directory is a good idea.
|
|
698
|
|
699 You might want these defined in each file; put at the *END* of your file
|
|
700 something like:
|
|
701
|
|
702 // Local Variables:
|
|
703 // verilog-library-directories:(\".\" \"subdir\" \"subdir2\")
|
|
704 // End:
|
|
705
|
|
706 Verilog-mode attempts to detect changes to this local variable, but they
|
|
707 are only insured to be correct when the file is first visited. Thus if you
|
|
708 have problems, use \\[find-alternate-file] RET to have these take effect.
|
|
709
|
|
710 See also `verilog-library-flags', `verilog-library-files'
|
|
711 and `verilog-library-extensions'."
|
|
712 :group 'verilog-mode-auto
|
|
713 :type '(repeat file))
|
|
714
|
|
715 (defcustom verilog-library-files '()
|
|
716 "*List of files to search for modules when looking for AUTOINST files.
|
|
717 This is a complete path, usually to a technology file with many standard
|
|
718 cells defined in it.
|
|
719
|
|
720 You might want these defined in each file; put at the *END* of your file
|
|
721 something like:
|
|
722
|
|
723 // Local Variables:
|
|
724 // verilog-library-files:(\"/some/path/technology.v\" \"/some/path/tech2.v\")
|
|
725 // End:
|
|
726
|
|
727 Verilog-mode attempts to detect changes to this local variable, but they
|
|
728 are only insured to be correct when the file is first visited. Thus if you
|
|
729 have problems, use \\[find-alternate-file] RET to have these take effect.
|
|
730
|
|
731 See also `verilog-library-flags', `verilog-library-directories'."
|
|
732 :group 'verilog-mode-auto
|
|
733 :type '(repeat directory))
|
|
734
|
|
735 (defcustom verilog-library-extensions '(".v")
|
|
736 "*List of extensions to use when looking for files for /*AUTOINST*/.
|
|
737 See also `verilog-library-flags', `verilog-library-directories'."
|
|
738 :type '(repeat string)
|
|
739 :group 'verilog-mode-auto)
|
|
740
|
|
741 (defcustom verilog-active-low-regexp nil
|
|
742 "*If set, treat signals matching this regexp as active low.
|
|
743 This is used for AUTORESET and AUTOTIEOFF. For proper behavior,
|
|
744 you will probably also need `verilog-auto-reset-widths' set."
|
|
745 :group 'verilog-mode-auto
|
|
746 :type 'string)
|
|
747
|
|
748 (defcustom verilog-auto-sense-include-inputs nil
|
|
749 "*If true, AUTOSENSE should include all inputs.
|
|
750 If nil, only inputs that are NOT output signals in the same block are
|
|
751 included."
|
|
752 :type 'boolean
|
|
753 :group 'verilog-mode-auto)
|
|
754
|
|
755 (defcustom verilog-auto-sense-defines-constant nil
|
|
756 "*If true, AUTOSENSE should assume all defines represent constants.
|
|
757 When true, the defines will not be included in sensitivity lists. To
|
|
758 maintain compatibility with other sites, this should be set at the bottom
|
|
759 of each verilog file that requires it, rather than being set globally."
|
|
760 :type 'boolean
|
|
761 :group 'verilog-mode-auto)
|
|
762
|
|
763 (defcustom verilog-auto-reset-widths t
|
|
764 "*If true, AUTORESET should determine the width of signals.
|
|
765 This is then used to set the width of the zero (32'h0 for example). This
|
|
766 is required by some lint tools that aren't smart enough to ignore widths of
|
|
767 the constant zero. This may result in ugly code when parameters determine
|
|
768 the MSB or LSB of a signal inside a AUTORESET."
|
|
769 :type 'boolean
|
|
770 :group 'verilog-mode-auto)
|
|
771
|
|
772 (defcustom verilog-assignment-delay ""
|
|
773 "*Text used for delays in delayed assignments. Add a trailing space if set."
|
|
774 :type 'string
|
|
775 :group 'verilog-mode-auto)
|
|
776
|
|
777 (defcustom verilog-auto-inst-vector t
|
|
778 "*If true, when creating default ports with AUTOINST, use bus subscripts.
|
|
779 If nil, skip the subscript when it matches the entire bus as declared in
|
|
780 the module (AUTOWIRE signals always are subscripted, you must manually
|
|
781 declare the wire to have the subscripts removed.) Nil may speed up some
|
|
782 simulators, but is less general and harder to read, so avoid."
|
|
783 :group 'verilog-mode-auto
|
|
784 :type 'boolean )
|
|
785
|
|
786 (defcustom verilog-auto-inst-template-numbers nil
|
|
787 "*If true, when creating templated ports with AUTOINST, add a comment.
|
|
788 The comment will add the line number of the template that was used for that
|
|
789 port declaration. Setting this aids in debugging, but nil is suggested for
|
|
790 regular use to prevent large numbers of merge conflicts."
|
|
791 :group 'verilog-mode-auto
|
|
792 :type 'boolean )
|
|
793
|
|
794 (defvar verilog-auto-inst-column 40
|
|
795 "Column number for first part of auto-inst.")
|
|
796
|
|
797 (defcustom verilog-auto-input-ignore-regexp nil
|
|
798 "*If set, when creating AUTOINPUT list, ignore signals matching this regexp.
|
|
799 See the \\[verilog-faq] for examples on using this."
|
|
800 :group 'verilog-mode-auto
|
|
801 :type 'string )
|
|
802
|
|
803 (defcustom verilog-auto-inout-ignore-regexp nil
|
|
804 "*If set, when creating AUTOINOUT list, ignore signals matching this regexp.
|
|
805 See the \\[verilog-faq] for examples on using this."
|
|
806 :group 'verilog-mode-auto
|
|
807 :type 'string )
|
|
808
|
|
809 (defcustom verilog-auto-output-ignore-regexp nil
|
|
810 "*If set, when creating AUTOOUTPUT list, ignore signals matching this regexp.
|
|
811 See the \\[verilog-faq] for examples on using this."
|
|
812 :group 'verilog-mode-auto
|
|
813 :type 'string )
|
|
814
|
|
815 (defcustom verilog-auto-unused-ignore-regexp nil
|
|
816 "*If set, when creating AUTOUNUSED list, ignore signals matching this regexp.
|
|
817 See the \\[verilog-faq] for examples on using this."
|
|
818 :group 'verilog-mode-auto
|
|
819 :type 'string )
|
|
820
|
|
821 (defcustom verilog-typedef-regexp nil
|
|
822 "*If non-nil, regular expression that matches Verilog-2001 typedef names.
|
|
823 For example, \"_t$\" matches typedefs named with _t, as in the C language."
|
|
824 :group 'verilog-mode-auto
|
|
825 :type 'string )
|
|
826
|
|
827 (defcustom verilog-mode-hook 'verilog-set-compile-command
|
|
828 "*Hook (List of functions) run after verilog mode is loaded."
|
|
829 :type 'hook
|
|
830 :group 'verilog-mode)
|
|
831
|
|
832 (defcustom verilog-auto-hook nil
|
|
833 "*Hook run after `verilog-mode' updates AUTOs."
|
|
834 :type 'hook
|
|
835 :group 'verilog-mode-auto)
|
|
836
|
|
837 (defcustom verilog-before-auto-hook nil
|
|
838 "*Hook run before `verilog-mode' updates AUTOs."
|
|
839 :type 'hook
|
|
840 :group 'verilog-mode-auto)
|
|
841
|
|
842 (defcustom verilog-delete-auto-hook nil
|
|
843 "*Hook run after `verilog-mode' deletes AUTOs."
|
|
844 :type 'hook
|
|
845 :group 'verilog-mode-auto)
|
|
846
|
|
847 (defcustom verilog-before-delete-auto-hook nil
|
|
848 "*Hook run before `verilog-mode' deletes AUTOs."
|
|
849 :type 'hook
|
|
850 :group 'verilog-mode-auto)
|
|
851
|
|
852 (defcustom verilog-getopt-flags-hook nil
|
|
853 "*Hook run after `verilog-getopt-flags' determines the Verilog option lists."
|
|
854 :type 'hook
|
|
855 :group 'verilog-mode-auto)
|
|
856
|
|
857 (defcustom verilog-before-getopt-flags-hook nil
|
|
858 "*Hook run before `verilog-getopt-flags' determines the Verilog option lists."
|
|
859 :type 'hook
|
|
860 :group 'verilog-mode-auto)
|
|
861
|
|
862 (defvar verilog-imenu-generic-expression
|
|
863 '((nil "^\\s-*\\(\\(m\\(odule\\|acromodule\\)\\)\\|primitive\\)\\s-+\\([a-zA-Z0-9_.:]+\\)" 4)
|
|
864 ("*Vars*" "^\\s-*\\(reg\\|wire\\)\\s-+\\(\\|\\[[^]]+\\]\\s-+\\)\\([A-Za-z0-9_]+\\)" 3))
|
|
865 "Imenu expression for Verilog-mode. See `imenu-generic-expression'.")
|
|
866
|
|
867 ;;
|
|
868 ;; provide a verilog-header function.
|
|
869 ;; Customization variables:
|
|
870 ;;
|
|
871 (defvar verilog-date-scientific-format nil
|
|
872 "*If non-nil, dates are written in scientific format (e.g. 1997/09/17).
|
|
873 If nil, in European format (e.g. 17.09.1997). The brain-dead American
|
|
874 format (e.g. 09/17/1997) is not supported.")
|
|
875
|
|
876 (defvar verilog-company nil
|
|
877 "*Default name of Company for verilog header.
|
|
878 If set will become buffer local.")
|
|
879
|
|
880 (defvar verilog-project nil
|
|
881 "*Default name of Project for verilog header.
|
|
882 If set will become buffer local.")
|
|
883
|
|
884 (define-abbrev-table 'verilog-mode-abbrev-table ())
|
|
885
|
|
886 (defvar verilog-mode-map ()
|
|
887 "Keymap used in Verilog mode.")
|
|
888 (if verilog-mode-map
|
|
889 ()
|
|
890 (setq verilog-mode-map (make-sparse-keymap))
|
|
891 (define-key verilog-mode-map ";" 'electric-verilog-semi)
|
|
892 (define-key verilog-mode-map [(control 59)] 'electric-verilog-semi-with-comment)
|
|
893 (define-key verilog-mode-map ":" 'electric-verilog-colon)
|
|
894 ;;(define-key verilog-mode-map "=" 'electric-verilog-equal)
|
|
895 (define-key verilog-mode-map "\`" 'electric-verilog-tick)
|
|
896 (define-key verilog-mode-map "\t" 'electric-verilog-tab)
|
|
897 (define-key verilog-mode-map "\r" 'electric-verilog-terminate-line)
|
|
898 ;; backspace/delete key bindings
|
|
899 (define-key verilog-mode-map [backspace] 'backward-delete-char-untabify)
|
|
900 (unless (boundp 'delete-key-deletes-forward) ; XEmacs variable
|
|
901 (define-key verilog-mode-map [delete] 'delete-char)
|
|
902 (define-key verilog-mode-map [(meta delete)] 'kill-word))
|
|
903 (define-key verilog-mode-map "\M-\C-b" 'electric-verilog-backward-sexp)
|
|
904 (define-key verilog-mode-map "\M-\C-f" 'electric-verilog-forward-sexp)
|
|
905 (define-key verilog-mode-map "\M-\r" `electric-verilog-terminate-and-indent)
|
|
906 (define-key verilog-mode-map "\M-\t" 'verilog-complete-word)
|
|
907 (define-key verilog-mode-map "\M-?" 'verilog-show-completions)
|
|
908 (define-key verilog-mode-map [(meta control h)] 'verilog-mark-defun)
|
|
909 (define-key verilog-mode-map "\C-c\`" 'verilog-lint-off)
|
|
910 (define-key verilog-mode-map "\C-c\*" 'verilog-delete-auto-star-implicit)
|
|
911 (define-key verilog-mode-map "\C-c\C-r" 'verilog-label-be)
|
|
912 (define-key verilog-mode-map "\C-c\C-i" 'verilog-pretty-declarations)
|
|
913 (define-key verilog-mode-map "\C-c=" 'verilog-pretty-expr)
|
|
914 (define-key verilog-mode-map "\C-c\C-b" 'verilog-submit-bug-report)
|
|
915 (define-key verilog-mode-map "\M-*" 'verilog-star-comment)
|
|
916 (define-key verilog-mode-map "\C-c\C-c" 'verilog-comment-region)
|
|
917 (define-key verilog-mode-map "\C-c\C-u" 'verilog-uncomment-region)
|
|
918 (define-key verilog-mode-map "\M-\C-a" 'verilog-beg-of-defun)
|
|
919 (define-key verilog-mode-map "\M-\C-e" 'verilog-end-of-defun)
|
|
920 (define-key verilog-mode-map "\C-c\C-d" 'verilog-goto-defun)
|
|
921 (define-key verilog-mode-map "\C-c\C-k" 'verilog-delete-auto)
|
|
922 (define-key verilog-mode-map "\C-c\C-a" 'verilog-auto)
|
|
923 (define-key verilog-mode-map "\C-c\C-s" 'verilog-auto-save-compile)
|
|
924 (define-key verilog-mode-map "\C-c\C-z" 'verilog-inject-auto)
|
|
925 (define-key verilog-mode-map "\C-c\C-e" 'verilog-expand-vector)
|
|
926 (define-key verilog-mode-map "\C-c\C-h" 'verilog-header)
|
|
927 )
|
|
928
|
|
929 ;; menus
|
|
930 (defvar verilog-xemacs-menu
|
|
931 '("Verilog"
|
|
932 ("Choose Compilation Action"
|
|
933 ["None"
|
|
934 (progn
|
|
935 (setq verilog-tool nil)
|
|
936 (verilog-set-compile-command))
|
|
937 :style radio
|
|
938 :selected (equal verilog-tool nil)]
|
|
939 ["Lint"
|
|
940 (progn
|
|
941 (setq verilog-tool 'verilog-linter)
|
|
942 (verilog-set-compile-command))
|
|
943 :style radio
|
|
944 :selected (equal verilog-tool `verilog-linter)]
|
|
945 ["Coverage"
|
|
946 (progn
|
|
947 (setq verilog-tool 'verilog-coverage)
|
|
948 (verilog-set-compile-command))
|
|
949 :style radio
|
|
950 :selected (equal verilog-tool `verilog-coverage)]
|
|
951 ["Simulator"
|
|
952 (progn
|
|
953 (setq verilog-tool 'verilog-simulator)
|
|
954 (verilog-set-compile-command))
|
|
955 :style radio
|
|
956 :selected (equal verilog-tool `verilog-simulator)]
|
|
957 ["Compiler"
|
|
958 (progn
|
|
959 (setq verilog-tool 'verilog-compiler)
|
|
960 (verilog-set-compile-command))
|
|
961 :style radio
|
|
962 :selected (equal verilog-tool `verilog-compiler)]
|
|
963 )
|
|
964 ("Move"
|
|
965 ["Beginning of function" verilog-beg-of-defun t]
|
|
966 ["End of function" verilog-end-of-defun t]
|
|
967 ["Mark function" verilog-mark-defun t]
|
|
968 ["Goto function/module" verilog-goto-defun t]
|
|
969 ["Move to beginning of block" electric-verilog-backward-sexp t]
|
|
970 ["Move to end of block" electric-verilog-forward-sexp t]
|
|
971 )
|
|
972 ("Comments"
|
|
973 ["Comment Region" verilog-comment-region t]
|
|
974 ["UnComment Region" verilog-uncomment-region t]
|
|
975 ["Multi-line comment insert" verilog-star-comment t]
|
|
976 ["Lint error to comment" verilog-lint-off t]
|
|
977 )
|
|
978 "----"
|
|
979 ["Compile" compile t]
|
|
980 ["AUTO, Save, Compile" verilog-auto-save-compile t]
|
|
981 ["Next Compile Error" next-error t]
|
|
982 ["Ignore Lint Warning at point" verilog-lint-off t]
|
|
983 "----"
|
|
984 ["Line up declarations around point" verilog-pretty-declarations t]
|
|
985 ["Line up equations around point" verilog-pretty-expr t]
|
|
986 ["Redo/insert comments on every end" verilog-label-be t]
|
|
987 ["Expand [x:y] vector line" verilog-expand-vector t]
|
|
988 ["Insert begin-end block" verilog-insert-block t]
|
|
989 ["Complete word" verilog-complete-word t]
|
|
990 "----"
|
|
991 ["Recompute AUTOs" verilog-auto t]
|
|
992 ["Kill AUTOs" verilog-delete-auto t]
|
|
993 ["Inject AUTOs" verilog-inject-auto t]
|
|
994 ("AUTO Help..."
|
|
995 ["AUTO General" (describe-function 'verilog-auto) t]
|
|
996 ["AUTO Library Flags" (describe-variable 'verilog-library-flags) t]
|
|
997 ["AUTO Library Path" (describe-variable 'verilog-library-directories) t]
|
|
998 ["AUTO Library Files" (describe-variable 'verilog-library-files) t]
|
|
999 ["AUTO Library Extensions" (describe-variable 'verilog-library-extensions) t]
|
|
1000 ["AUTO `define Reading" (describe-function 'verilog-read-defines) t]
|
|
1001 ["AUTO `include Reading" (describe-function 'verilog-read-includes) t]
|
|
1002 ["AUTOARG" (describe-function 'verilog-auto-arg) t]
|
|
1003 ["AUTOASCIIENUM" (describe-function 'verilog-auto-ascii-enum) t]
|
|
1004 ["AUTOINOUTMODULE" (describe-function 'verilog-auto-inout-module) t]
|
|
1005 ["AUTOINOUT" (describe-function 'verilog-auto-inout) t]
|
|
1006 ["AUTOINPUT" (describe-function 'verilog-auto-input) t]
|
|
1007 ["AUTOINST" (describe-function 'verilog-auto-inst) t]
|
|
1008 ["AUTOINST (.*)" (describe-function 'verilog-auto-star) t]
|
|
1009 ["AUTOINSTPARAM" (describe-function 'verilog-auto-inst-param) t]
|
|
1010 ["AUTOOUTPUT" (describe-function 'verilog-auto-output) t]
|
|
1011 ["AUTOOUTPUTEVERY" (describe-function 'verilog-auto-output-every) t]
|
|
1012 ["AUTOREG" (describe-function 'verilog-auto-reg) t]
|
|
1013 ["AUTOREGINPUT" (describe-function 'verilog-auto-reg-input) t]
|
|
1014 ["AUTORESET" (describe-function 'verilog-auto-reset) t]
|
|
1015 ["AUTOSENSE" (describe-function 'verilog-auto-sense) t]
|
|
1016 ["AUTOTIEOFF" (describe-function 'verilog-auto-tieoff) t]
|
|
1017 ["AUTOUNUSED" (describe-function 'verilog-auto-unused) t]
|
|
1018 ["AUTOWIRE" (describe-function 'verilog-auto-wire) t]
|
|
1019 )
|
|
1020 "----"
|
|
1021 ["Submit bug report" verilog-submit-bug-report t]
|
|
1022 ["Version and FAQ" verilog-faq t]
|
|
1023 ["Customize Verilog Mode..." verilog-customize t]
|
|
1024 ["Customize Verilog Fonts & Colors" verilog-font-customize t]
|
|
1025 )
|
|
1026 "Emacs menu for VERILOG mode."
|
|
1027 )
|
|
1028 (defvar verilog-statement-menu
|
|
1029 '("Statements"
|
|
1030 ["Header" verilog-sk-header t]
|
|
1031 ["Comment" verilog-sk-comment t]
|
|
1032 "----"
|
|
1033 ["Module" verilog-sk-module t]
|
|
1034 ["Primitive" verilog-sk-primitive t]
|
|
1035 "----"
|
|
1036 ["Input" verilog-sk-input t]
|
|
1037 ["Output" verilog-sk-output t]
|
|
1038 ["Inout" verilog-sk-inout t]
|
|
1039 ["Wire" verilog-sk-wire t]
|
|
1040 ["Reg" verilog-sk-reg t]
|
|
1041 ["Define thing under point as a register" verilog-sk-define-signal t]
|
|
1042 "----"
|
|
1043 ["Initial" verilog-sk-initial t]
|
|
1044 ["Always" verilog-sk-always t]
|
|
1045 ["Function" verilog-sk-function t]
|
|
1046 ["Task" verilog-sk-task t]
|
|
1047 ["Specify" verilog-sk-specify t]
|
|
1048 ["Generate" verilog-sk-generate t]
|
|
1049 "----"
|
|
1050 ["Begin" verilog-sk-begin t]
|
|
1051 ["If" verilog-sk-if t]
|
|
1052 ["(if) else" verilog-sk-else-if t]
|
|
1053 ["For" verilog-sk-for t]
|
|
1054 ["While" verilog-sk-while t]
|
|
1055 ["Fork" verilog-sk-fork t]
|
|
1056 ["Repeat" verilog-sk-repeat t]
|
|
1057 ["Case" verilog-sk-case t]
|
|
1058 ["Casex" verilog-sk-casex t]
|
|
1059 ["Casez" verilog-sk-casez t]
|
|
1060 )
|
|
1061 "Menu for statement templates in Verilog."
|
|
1062 )
|
|
1063
|
|
1064 (easy-menu-define verilog-menu verilog-mode-map "Menu for Verilog mode"
|
|
1065 verilog-xemacs-menu)
|
|
1066 (easy-menu-define verilog-stmt-menu verilog-mode-map "Menu for statement templates in Verilog."
|
|
1067 verilog-statement-menu)
|
|
1068
|
|
1069 (defvar verilog-mode-abbrev-table nil
|
|
1070 "Abbrev table in use in Verilog-mode buffers.")
|
|
1071
|
|
1072 (define-abbrev-table 'verilog-mode-abbrev-table ())
|
|
1073
|
|
1074 ;; compilation program
|
|
1075 (defun verilog-set-compile-command ()
|
|
1076 "Function to compute shell command to compile verilog.
|
|
1077
|
|
1078 This reads `verilog-tool' and sets `compile-command'. This specifies the
|
|
1079 program that executes when you type \\[compile] or
|
|
1080 \\[verilog-auto-save-compile].
|
|
1081
|
|
1082 By default `verilog-tool' uses a Makefile if one exists in the current
|
|
1083 directory. If not, it is set to the `verilog-linter', `verilog-coverage',
|
|
1084 `verilog-simulator', or `verilog-compiler' variables, as selected with the
|
|
1085 Verilog -> \"Choose Compilation Action\" menu.
|
|
1086
|
|
1087 You should set `verilog-tool' or the other variables to the path and
|
|
1088 arguments for your Verilog simulator. For example:
|
|
1089 \"vcs -p123 -O\"
|
|
1090 or a string like:
|
|
1091 \"(cd /tmp; surecov %s)\".
|
|
1092
|
|
1093 In the former case, the path to the current buffer is concat'ed to the
|
|
1094 value of `verilog-tool'; in the later, the path to the current buffer is
|
|
1095 substituted for the %s.
|
|
1096
|
|
1097 Where __FILE__ appears in the string, the buffer-file-name of the current
|
|
1098 buffer, without the directory portion, will be substituted."
|
|
1099 (interactive)
|
|
1100 (cond
|
|
1101 ((or (file-exists-p "makefile") ;If there is a makefile, use it
|
|
1102 (file-exists-p "Makefile"))
|
|
1103 (make-local-variable 'compile-command)
|
|
1104 (setq compile-command "make "))
|
|
1105 (t
|
|
1106 (make-local-variable 'compile-command)
|
|
1107 (setq compile-command
|
|
1108 (if verilog-tool
|
|
1109 (if (string-match "%s" (eval verilog-tool))
|
|
1110 (format (eval verilog-tool) (or buffer-file-name ""))
|
|
1111 (concat (eval verilog-tool) " " (or buffer-file-name "")))
|
|
1112 ""))))
|
|
1113 (verilog-modify-compile-command))
|
|
1114
|
|
1115 (defun verilog-modify-compile-command ()
|
|
1116 "Replace meta-information in `compile-command'.
|
|
1117 Where __FILE__ appears in the string, the current buffer's file-name,
|
|
1118 without the directory portion, will be substituted."
|
|
1119 (when (and
|
|
1120 (stringp compile-command)
|
|
1121 (string-match "\\b__FILE__\\b" compile-command))
|
|
1122 (make-local-variable 'compile-command)
|
|
1123 (setq compile-command
|
|
1124 (verilog-string-replace-matches
|
|
1125 "\\b__FILE__\\b" (file-name-nondirectory (buffer-file-name))
|
|
1126 t t compile-command))))
|
|
1127
|
|
1128 (defun verilog-error-regexp-add ()
|
|
1129 "Add the messages to the `compilation-error-regexp-alist'.
|
|
1130 Called by `compilation-mode-hook'. This allows \\[next-error] to find the errors."
|
|
1131 (if (not verilog-error-regexp-add-didit)
|
|
1132 (progn
|
|
1133 (setq verilog-error-regexp-add-didit t)
|
|
1134 (setq-default compilation-error-regexp-alist
|
|
1135 (append verilog-error-regexp
|
|
1136 (default-value 'compilation-error-regexp-alist)))
|
|
1137 ;; Could be buffer local at this point; maybe also in let; change all three
|
|
1138 (setq compilation-error-regexp-alist (default-value 'compilation-error-regexp-alist))
|
|
1139 (set (make-local-variable 'compilation-error-regexp-alist)
|
|
1140 (default-value 'compilation-error-regexp-alist))
|
|
1141 )))
|
|
1142
|
|
1143 (add-hook 'compilation-mode-hook 'verilog-error-regexp-add)
|
|
1144
|
|
1145 (defconst verilog-directive-re
|
|
1146 ;; "`case" "`default" "`define" "`define" "`else" "`endfor" "`endif"
|
|
1147 ;; "`endprotect" "`endswitch" "`endwhile" "`for" "`format" "`if" "`ifdef"
|
|
1148 ;; "`ifndef" "`include" "`let" "`protect" "`switch" "`timescale"
|
|
1149 ;; "`time_scale" "`undef" "`while"
|
|
1150 "\\<`\\(case\\|def\\(ault\\|ine\\(\\)?\\)\\|e\\(lse\\|nd\\(for\\|if\\|protect\\|switch\\|while\\)\\)\\|for\\(mat\\)?\\|i\\(f\\(def\\|ndef\\)?\\|nclude\\)\\|let\\|protect\\|switch\\|time\\(_scale\\|scale\\)\\|undef\\|while\\)\\>")
|
|
1151
|
|
1152 (defconst verilog-directive-begin
|
|
1153 "\\<`\\(for\\|i\\(f\\|fdef\\|fndef\\)\\|switch\\|while\\)\\>")
|
|
1154
|
|
1155 (defconst verilog-directive-middle
|
|
1156 "\\<`\\(else\\|default\\|case\\)\\>")
|
|
1157
|
|
1158 (defconst verilog-directive-end
|
|
1159 "`\\(endfor\\|endif\\|endswitch\\|endwhile\\)\\>")
|
|
1160
|
|
1161 (defconst verilog-directive-re-1
|
|
1162 (concat "[ \t]*" verilog-directive-re))
|
|
1163
|
|
1164 ;;
|
|
1165 ;; Regular expressions used to calculate indent, etc.
|
|
1166 ;;
|
|
1167 (defconst verilog-symbol-re "\\<[a-zA-Z_][a-zA-Z_0-9.]*\\>")
|
|
1168 (defconst verilog-case-re "\\(\\<case[xz]?\\>\\|\\<randcase\\>\\)")
|
|
1169 ;; Want to match
|
|
1170 ;; aa :
|
|
1171 ;; aa,bb :
|
|
1172 ;; a[34:32] :
|
|
1173 ;; a,
|
|
1174 ;; b :
|
|
1175
|
|
1176 (defconst verilog-no-indent-begin-re
|
|
1177 "\\<\\(if\\|else\\|while\\|for\\|repeat\\|always\\|always_comb\\|always_ff\\|always_latch\\)\\>")
|
|
1178
|
|
1179 (defconst verilog-ends-re
|
|
1180 ;; Parenthesis indicate type of keyword found
|
|
1181 (concat
|
|
1182 "\\(\\<else\\>\\)\\|" ; 1
|
|
1183 "\\(\\<if\\>\\)\\|" ; 2
|
|
1184 "\\(\\<end\\>\\)\\|" ; 3
|
|
1185 "\\(\\<endcase\\>\\)\\|" ; 4
|
|
1186 "\\(\\<endfunction\\>\\)\\|" ; 5
|
|
1187 "\\(\\<endtask\\>\\)\\|" ; 6
|
|
1188 "\\(\\<endspecify\\>\\)\\|" ; 7
|
|
1189 "\\(\\<endtable\\>\\)\\|" ; 8
|
|
1190 "\\(\\<endgenerate\\>\\)\\|" ; 9
|
|
1191 "\\(\\<join\\(_any\\|_none\\)?\\>\\)\\|" ; 10
|
|
1192 "\\(\\<endclass\\>\\)\\|" ; 11
|
|
1193 "\\(\\<endgroup\\>\\)" ; 12
|
|
1194 ))
|
|
1195
|
|
1196 (defconst verilog-auto-end-comment-lines-re
|
|
1197 ;; Matches to names in this list cause auto-end-commentation
|
|
1198 (concat "\\("
|
|
1199 verilog-directive-re "\\)\\|\\("
|
|
1200 (eval-when-compile
|
|
1201 (verilog-regexp-words
|
|
1202 `( "begin"
|
|
1203 "else"
|
|
1204 "end"
|
|
1205 "endcase"
|
|
1206 "endclass"
|
|
1207 "endclocking"
|
|
1208 "endgroup"
|
|
1209 "endfunction"
|
|
1210 "endmodule"
|
|
1211 "endprogram"
|
|
1212 "endprimitive"
|
|
1213 "endinterface"
|
|
1214 "endpackage"
|
|
1215 "endsequence"
|
|
1216 "endspecify"
|
|
1217 "endtable"
|
|
1218 "endtask"
|
|
1219 "join"
|
|
1220 "join_any"
|
|
1221 "join_none"
|
|
1222 "module"
|
|
1223 "macromodule"
|
|
1224 "primitive"
|
|
1225 "interface"
|
|
1226 "package")))
|
|
1227 "\\)"))
|
|
1228
|
|
1229 ;;; NOTE: verilog-leap-to-head expects that verilog-end-block-re and
|
|
1230 ;;; verilog-end-block-ordered-re matches exactly the same strings.
|
|
1231 (defconst verilog-end-block-ordered-re
|
|
1232 ;; Parenthesis indicate type of keyword found
|
|
1233 (concat "\\(\\<endcase\\>\\)\\|" ; 1
|
|
1234 "\\(\\<end\\>\\)\\|" ; 2
|
|
1235 "\\(\\<end" ; 3, but not used
|
|
1236 "\\(" ; 4, but not used
|
|
1237 "\\(function\\)\\|" ; 5
|
|
1238 "\\(task\\)\\|" ; 6
|
|
1239 "\\(module\\)\\|" ; 7
|
|
1240 "\\(primitive\\)\\|" ; 8
|
|
1241 "\\(interface\\)\\|" ; 9
|
|
1242 "\\(package\\)\\|" ; 10
|
|
1243 "\\(class\\)\\|" ; 11
|
|
1244 "\\(group\\)\\|" ; 12
|
|
1245 "\\(program\\)\\|" ; 13
|
|
1246 "\\(sequence\\)\\|" ; 14
|
|
1247 "\\(clocking\\)\\|" ; 15
|
|
1248 "\\)\\>\\)"))
|
|
1249 (defconst verilog-end-block-re
|
|
1250 (eval-when-compile
|
|
1251 (verilog-regexp-words
|
|
1252
|
|
1253 `("end" ;; closes begin
|
|
1254 "endcase" ;; closes any of case, casex casez or randcase
|
|
1255 "join" "join_any" "join_none" ;; closes fork
|
|
1256 "endclass"
|
|
1257 "endtable"
|
|
1258 "endspecify"
|
|
1259 "endfunction"
|
|
1260 "endgenerate"
|
|
1261 "endtask"
|
|
1262 "endgroup"
|
|
1263 "endproperty"
|
|
1264 "endinterface"
|
|
1265 "endpackage"
|
|
1266 "endprogram"
|
|
1267 "endsequence"
|
|
1268 "endclocking"
|
|
1269 )
|
|
1270 )))
|
|
1271
|
|
1272
|
|
1273 (defconst verilog-endcomment-reason-re
|
|
1274 ;; Parenthesis indicate type of keyword found
|
|
1275 (concat
|
|
1276 "\\(\\<fork\\>\\)\\|"
|
|
1277 "\\(\\<begin\\>\\)\\|"
|
|
1278 "\\(\\<if\\>\\)\\|"
|
|
1279 "\\(\\<clocking\\>\\)\\|"
|
|
1280 "\\(\\<else\\>\\)\\|"
|
|
1281 "\\(\\<end\\>.*\\<else\\>\\)\\|"
|
|
1282 "\\(\\<task\\>\\)\\|"
|
|
1283 "\\(\\<function\\>\\)\\|"
|
|
1284 "\\(\\<initial\\>\\)\\|"
|
|
1285 "\\(\\<interface\\>\\)\\|"
|
|
1286 "\\(\\<package\\>\\)\\|"
|
|
1287 "\\(\\<final\\>\\)\\|"
|
|
1288 "\\(\\<always\\>\\(\[ \t\]*@\\)?\\)\\|"
|
|
1289 "\\(\\<always_comb\\>\\(\[ \t\]*@\\)?\\)\\|"
|
|
1290 "\\(\\<always_ff\\>\\(\[ \t\]*@\\)?\\)\\|"
|
|
1291 "\\(\\<always_latch\\>\\(\[ \t\]*@\\)?\\)\\|"
|
|
1292 "\\(@\\)\\|"
|
|
1293 "\\(\\<while\\>\\)\\|"
|
|
1294 "\\(\\<for\\(ever\\|each\\)?\\>\\)\\|"
|
|
1295 "\\(\\<repeat\\>\\)\\|\\(\\<wait\\>\\)\\|"
|
|
1296 "#"))
|
|
1297
|
|
1298 (defconst verilog-named-block-re "begin[ \t]*:")
|
|
1299
|
|
1300 ;; These words begin a block which can occur inside a module which should be indented,
|
|
1301 ;; and closed with the respective word from the end-block list
|
|
1302
|
|
1303 (defconst verilog-beg-block-re
|
|
1304 (eval-when-compile
|
|
1305 (verilog-regexp-words
|
|
1306 `("begin"
|
|
1307 "case" "casex" "casez" "randcase"
|
|
1308 "clocking"
|
|
1309 "generate"
|
|
1310 "fork"
|
|
1311 "function"
|
|
1312 "property"
|
|
1313 "specify"
|
|
1314 "table"
|
|
1315 "task"
|
|
1316 ))))
|
|
1317 ;; These are the same words, in a specific order in the regular
|
|
1318 ;; expression so that matching will work nicely for
|
|
1319 ;; verilog-forward-sexp and verilog-calc-indent
|
|
1320
|
|
1321 (defconst verilog-beg-block-re-ordered
|
|
1322 ( concat "\\<"
|
|
1323 "\\(begin\\)" ;1
|
|
1324 "\\|\\(randcase\\|\\(unique\\s-+\\|priority\\s-+\\)?case[xz]?\\)" ; 2
|
|
1325 ;; "\\|\\(randcase\\|case[xz]?\\)" ; 2
|
|
1326 "\\|\\(fork\\)" ;3
|
|
1327 "\\|\\(class\\)" ;4
|
|
1328 "\\|\\(table\\)" ;5
|
|
1329 "\\|\\(specify\\)" ;6
|
|
1330 "\\|\\(function\\)" ;7
|
|
1331 "\\|\\(task\\)" ;8
|
|
1332 "\\|\\(generate\\)" ;9
|
|
1333 "\\|\\(covergroup\\)" ;10
|
|
1334 "\\|\\(property\\)" ;11
|
|
1335 "\\|\\(\\(rand\\)?sequence\\)" ;12
|
|
1336 "\\|\\(clocking\\)" ;13
|
|
1337 "\\>"))
|
|
1338
|
|
1339 (defconst verilog-end-block-ordered-rry
|
|
1340 [ "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)\\|\\(\\<endcase\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)"
|
|
1341 "\\(\\<randcase\\>\\|\\<case[xz]?\\>\\)\\|\\(\\<endcase\\>\\)"
|
|
1342 "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)"
|
|
1343 "\\(\\<class\\>\\)\\|\\(\\<endclass\\>\\)"
|
|
1344 "\\(\\<table\\>\\)\\|\\(\\<endtable\\>\\)"
|
|
1345 "\\(\\<specify\\>\\)\\|\\(\\<endspecify\\>\\)"
|
|
1346 "\\(\\<function\\>\\)\\|\\(\\<endfunction\\>\\)"
|
|
1347 "\\(\\<generate\\>\\)\\|\\(\\<endgenerate\\>\\)"
|
|
1348 "\\(\\<task\\>\\)\\|\\(\\<endtask\\>\\)"
|
|
1349 "\\(\\<covergroup\\>\\)\\|\\(\\<endgroup\\>\\)"
|
|
1350 "\\(\\<property\\>\\)\\|\\(\\<endproperty\\>\\)"
|
|
1351 "\\(\\<\\(rand\\)?sequence\\>\\)\\|\\(\\<endsequence\\>\\)"
|
|
1352 "\\(\\<clocking\\>\\)\\|\\(\\<endclocking\\>\\)"
|
|
1353 ] )
|
|
1354
|
|
1355 (defconst verilog-nameable-item-re
|
|
1356 (eval-when-compile
|
|
1357 (verilog-regexp-words
|
|
1358 `("begin"
|
|
1359 "fork"
|
|
1360 "join" "join_any" "join_none"
|
|
1361 "end"
|
|
1362 "endcase"
|
|
1363 "endconfig"
|
|
1364 "endclass"
|
|
1365 "endclocking"
|
|
1366 "endfunction"
|
|
1367 "endgenerate"
|
|
1368 "endmodule"
|
|
1369 "endprimative"
|
|
1370 "endinterface"
|
|
1371 "endpackage"
|
|
1372 "endspecify"
|
|
1373 "endtable"
|
|
1374 "endtask" )
|
|
1375 )))
|
|
1376
|
|
1377 (defconst verilog-declaration-opener
|
|
1378 (eval-when-compile
|
|
1379 (verilog-regexp-words
|
|
1380 `("module" "begin" "task" "function"))))
|
|
1381
|
|
1382 (defconst verilog-declaration-prefix-re
|
|
1383 (eval-when-compile
|
|
1384 (verilog-regexp-words
|
|
1385 `(
|
|
1386 ;; port direction
|
|
1387 "inout" "input" "output" "ref"
|
|
1388 ;; changeableness
|
|
1389 "const" "static" "protected" "local"
|
|
1390 ;; parameters
|
|
1391 "localparam" "parameter" "var"
|
|
1392 ;; type creation
|
|
1393 "typedef"
|
|
1394 ))))
|
|
1395 (defconst verilog-declaration-core-re
|
|
1396 (eval-when-compile
|
|
1397 (verilog-regexp-words
|
|
1398 `(
|
|
1399 ;; integer_atom_type
|
|
1400 "byte" "shortint" "int" "longint" "integer" "time"
|
|
1401 ;; integer_vector_type
|
|
1402 "bit" "logic" "reg"
|
|
1403 ;; non_integer_type
|
|
1404 "shortreal" "real" "realtime"
|
|
1405 ;; net_type
|
|
1406 "supply0" "supply1" "tri" "triand" "trior" "trireg" "tri0" "tri1" "uwire" "wire" "wand" "wor"
|
|
1407 ;; misc
|
|
1408 "string" "event" "chandle" "virtual" "enum" "genvar"
|
|
1409 "struct" "union"
|
|
1410 ;; builtin classes
|
|
1411 "mailbox" "semaphore"
|
|
1412 ))))
|
|
1413 (defconst verilog-declaration-re
|
|
1414 (concat "\\(" verilog-declaration-prefix-re "\\s-*\\)?" verilog-declaration-core-re))
|
|
1415 (defconst verilog-range-re "\\(\\[[^]]*\\]\\s-*\\)+")
|
|
1416 (defconst verilog-optional-signed-re "\\s-*\\(signed\\)?")
|
|
1417 (defconst verilog-optional-signed-range-re
|
|
1418 (concat
|
|
1419 "\\s-*\\(\\<\\(reg\\|wire\\)\\>\\s-*\\)?\\(\\<signed\\>\\s-*\\)?\\(" verilog-range-re "\\)?"))
|
|
1420 (defconst verilog-macroexp-re "`\\sw+")
|
|
1421
|
|
1422 (defconst verilog-delay-re "#\\s-*\\(\\([0-9_]+\\('s?[hdxbo][0-9a-fA-F_xz]+\\)?\\)\\|\\(([^()]*)\\)\\|\\(\\sw+\\)\\)")
|
|
1423 (defconst verilog-declaration-re-2-no-macro
|
|
1424 (concat "\\s-*" verilog-declaration-re
|
|
1425 "\\s-*\\(\\(" verilog-optional-signed-range-re "\\)\\|\\(" verilog-delay-re "\\)"
|
|
1426 "\\)?"))
|
|
1427 (defconst verilog-declaration-re-2-macro
|
|
1428 (concat "\\s-*" verilog-declaration-re
|
|
1429 "\\s-*\\(\\(" verilog-optional-signed-range-re "\\)\\|\\(" verilog-delay-re "\\)"
|
|
1430 "\\|\\(" verilog-macroexp-re "\\)"
|
|
1431 "\\)?"))
|
|
1432 (defconst verilog-declaration-re-1-macro
|
|
1433 (concat "^" verilog-declaration-re-2-macro))
|
|
1434
|
|
1435 (defconst verilog-declaration-re-1-no-macro (concat "^" verilog-declaration-re-2-no-macro))
|
|
1436
|
|
1437 (defconst verilog-defun-re
|
|
1438 (eval-when-compile (verilog-regexp-words `("macromodule" "module" "class" "program" "interface" "package" "primitive" "config"))))
|
|
1439 (defconst verilog-end-defun-re
|
|
1440 (eval-when-compile (verilog-regexp-words `("endmodule" "endclass" "endprogram" "endinterface" "endpackage" "endprimitive" "endconfig"))))
|
|
1441 (defconst verilog-zero-indent-re
|
|
1442 (concat verilog-defun-re "\\|" verilog-end-defun-re))
|
|
1443
|
|
1444 (defconst verilog-behavioral-block-beg-re
|
|
1445 (concat "\\(\\<initial\\>\\|\\<final\\>\\|\\<always\\>\\|\\<always_comb\\>\\|\\<always_ff\\>\\|"
|
|
1446 "\\<always_latch\\>\\|\\<function\\>\\|\\<task\\>\\)"))
|
|
1447
|
|
1448 (defconst verilog-indent-re
|
|
1449 (eval-when-compile
|
|
1450 (verilog-regexp-words
|
|
1451 `(
|
|
1452 "{"
|
|
1453 "always" "always_latch" "always_ff" "always_comb"
|
|
1454 "begin" "end"
|
|
1455 ; "unique" "priority"
|
|
1456 "case" "casex" "casez" "randcase" "endcase"
|
|
1457 "class" "endclass"
|
|
1458 "clocking" "endclocking"
|
|
1459 "config" "endconfig"
|
|
1460 "covergroup" "endgroup"
|
|
1461 "fork" "join" "join_any" "join_none"
|
|
1462 "function" "endfunction"
|
|
1463 "final"
|
|
1464 "generate" "endgenerate"
|
|
1465 "initial"
|
|
1466 "interface" "endinterface"
|
|
1467 "module" "macromodule" "endmodule"
|
|
1468 "package" "endpackage"
|
|
1469 "primitive" "endprimative"
|
|
1470 "program" "endprogram"
|
|
1471 "property" "endproperty"
|
|
1472 "sequence" "randsequence" "endsequence"
|
|
1473 "specify" "endspecify"
|
|
1474 "table" "endtable"
|
|
1475 "task" "endtask"
|
|
1476 "`case"
|
|
1477 "`default"
|
|
1478 "`define" "`undef"
|
|
1479 "`if" "`ifdef" "`ifndef" "`else" "`endif"
|
|
1480 "`while" "`endwhile"
|
|
1481 "`for" "`endfor"
|
|
1482 "`format"
|
|
1483 "`include"
|
|
1484 "`let"
|
|
1485 "`protect" "`endprotect"
|
|
1486 "`switch" "`endswitch"
|
|
1487 "`timescale"
|
|
1488 "`time_scale"
|
|
1489 ))))
|
|
1490
|
|
1491 (defconst verilog-defun-level-re
|
|
1492 (eval-when-compile
|
|
1493 (verilog-regexp-words
|
|
1494 `(
|
|
1495 "module" "macromodule" "primitive" "class" "program" "initial" "final" "always" "always_comb"
|
|
1496 "always_ff" "always_latch" "endtask" "endfunction" "interface" "package"
|
|
1497 "config"))))
|
|
1498
|
|
1499 (defconst verilog-defun-level-not-generate-re
|
|
1500 (eval-when-compile
|
|
1501 (verilog-regexp-words
|
|
1502 `(
|
|
1503 "module" "macromodule" "primitive" "class" "program" "interface" "package" "config"))))
|
|
1504
|
|
1505 (defconst verilog-cpp-level-re
|
|
1506 (eval-when-compile
|
|
1507 (verilog-regexp-words
|
|
1508 `(
|
|
1509 "endmodule" "endprimitive" "endinterface" "endpackage" "endprogram" "endclass"
|
|
1510 ))))
|
|
1511 (defconst verilog-extended-case-re "\\(unique\\s-+\\|priority\\s-+\\)?case[xz]?")
|
|
1512 (defconst verilog-extended-complete-re
|
|
1513 (concat "\\(\\<extern\\s-+\\|\\<virtual\\s-+\\|\\<protected\\s-+\\)*\\(\\<function\\>\\|\\<task\\>\\)"
|
|
1514 "\\|\\(\\<typedef\\>\\s-+\\)*\\(\\<struct\\>\\|\\<union\\>\\|\\<class\\>\\)"
|
|
1515 "\\|" verilog-extended-case-re ))
|
|
1516 (defconst verilog-basic-complete-re
|
|
1517 (eval-when-compile
|
|
1518 (verilog-regexp-words
|
|
1519 `(
|
|
1520 "always" "assign" "always_latch" "always_ff" "always_comb" "constraint"
|
|
1521 "import" "initial" "final" "module" "macromodule" "repeat" "randcase" "while"
|
|
1522 "if" "for" "forever" "foreach" "else" "parameter" "do"
|
|
1523 ))))
|
|
1524 (defconst verilog-complete-reg
|
|
1525 (concat
|
|
1526 verilog-extended-complete-re
|
|
1527 "\\|"
|
|
1528 verilog-basic-complete-re))
|
|
1529
|
|
1530 (defconst verilog-end-statement-re
|
|
1531 (concat "\\(" verilog-beg-block-re "\\)\\|\\("
|
|
1532 verilog-end-block-re "\\)"))
|
|
1533
|
|
1534 (defconst verilog-endcase-re
|
|
1535 (concat verilog-case-re "\\|"
|
|
1536 "\\(endcase\\)\\|"
|
|
1537 verilog-defun-re
|
|
1538 ))
|
|
1539
|
|
1540 (defconst verilog-exclude-str-start "/* -----\\/----- EXCLUDED -----\\/-----"
|
|
1541 "String used to mark beginning of excluded text.")
|
|
1542 (defconst verilog-exclude-str-end " -----/\\----- EXCLUDED -----/\\----- */"
|
|
1543 "String used to mark end of excluded text.")
|
|
1544 (defconst verilog-preprocessor-re
|
|
1545 (eval-when-compile
|
|
1546 (verilog-regexp-words
|
|
1547 `(
|
|
1548 "`define" "`include" "`ifdef" "`ifndef" "`if" "`endif" "`else"
|
|
1549 ))))
|
|
1550
|
|
1551 (defconst verilog-keywords
|
|
1552 '( "`case" "`default" "`define" "`else" "`endfor" "`endif"
|
|
1553 "`endprotect" "`endswitch" "`endwhile" "`for" "`format" "`if" "`ifdef"
|
|
1554 "`ifndef" "`include" "`let" "`protect" "`switch" "`timescale"
|
|
1555 "`time_scale" "`undef" "`while"
|
|
1556
|
|
1557 "after" "alias" "always" "always_comb" "always_ff" "always_latch" "and"
|
|
1558 "assert" "assign" "assume" "automatic" "before" "begin" "bind"
|
|
1559 "bins" "binsof" "bit" "break" "buf" "bufif0" "bufif1" "byte"
|
|
1560 "case" "casex" "casez" "cell" "chandle" "class" "clocking" "cmos"
|
|
1561 "config" "const" "constraint" "context" "continue" "cover"
|
|
1562 "covergroup" "coverpoint" "cross" "deassign" "default" "defparam"
|
|
1563 "design" "disable" "dist" "do" "edge" "else" "end" "endcase"
|
|
1564 "endclass" "endclocking" "endconfig" "endfunction" "endgenerate"
|
|
1565 "endgroup" "endinterface" "endmodule" "endpackage" "endprimitive"
|
|
1566 "endprogram" "endproperty" "endspecify" "endsequence" "endtable"
|
|
1567 "endtask" "enum" "event" "expect" "export" "extends" "extern"
|
|
1568 "final" "first_match" "for" "force" "foreach" "forever" "fork"
|
|
1569 "forkjoin" "function" "generate" "genvar" "highz0" "highz1" "if"
|
|
1570 "iff" "ifnone" "ignore_bins" "illegal_bins" "import" "incdir"
|
|
1571 "include" "initial" "inout" "input" "inside" "instance" "int"
|
|
1572 "integer" "interface" "intersect" "join" "join_any" "join_none"
|
|
1573 "large" "liblist" "library" "local" "localparam" "logic"
|
|
1574 "longint" "macromodule" "mailbox" "matches" "medium" "modport" "module"
|
|
1575 "nand" "negedge" "new" "nmos" "nor" "noshowcancelled" "not"
|
|
1576 "notif0" "notif1" "null" "or" "output" "package" "packed"
|
|
1577 "parameter" "pmos" "posedge" "primitive" "priority" "program"
|
|
1578 "property" "protected" "pull0" "pull1" "pulldown" "pullup"
|
|
1579 "pulsestyle_onevent" "pulsestyle_ondetect" "pure" "rand" "randc"
|
|
1580 "randcase" "randsequence" "rcmos" "real" "realtime" "ref" "reg"
|
|
1581 "release" "repeat" "return" "rnmos" "rpmos" "rtran" "rtranif0"
|
|
1582 "rtranif1" "scalared" "semaphore" "sequence" "shortint" "shortreal"
|
|
1583 "showcancelled" "signed" "small" "solve" "specify" "specparam"
|
|
1584 "static" "string" "strong0" "strong1" "struct" "super" "supply0"
|
|
1585 "supply1" "table" "tagged" "task" "this" "throughout" "time"
|
|
1586 "timeprecision" "timeunit" "tran" "tranif0" "tranif1" "tri"
|
|
1587 "tri0" "tri1" "triand" "trior" "trireg" "type" "typedef" "union"
|
|
1588 "unique" "unsigned" "use" "uwire" "var" "vectored" "virtual" "void"
|
|
1589 "wait" "wait_order" "wand" "weak0" "weak1" "while" "wildcard"
|
|
1590 "wire" "with" "within" "wor" "xnor" "xor"
|
|
1591 )
|
|
1592 "List of Verilog keywords.")
|
|
1593
|
|
1594
|
|
1595 (defconst verilog-emacs-features
|
|
1596 ;; Documentation at the bottom
|
|
1597 (let ((major (and (boundp 'emacs-major-version)
|
|
1598 emacs-major-version))
|
|
1599 (minor (and (boundp 'emacs-minor-version)
|
|
1600 emacs-minor-version))
|
|
1601 flavor comments flock-syntax)
|
|
1602 ;; figure out version numbers if not already discovered
|
|
1603 (and (or (not major) (not minor))
|
|
1604 (string-match "\\([0-9]+\\).\\([0-9]+\\)" emacs-version)
|
|
1605 (setq major (string-to-int (substring emacs-version
|
|
1606 (match-beginning 1)
|
|
1607 (match-end 1)))
|
|
1608 minor (string-to-int (substring emacs-version
|
|
1609 (match-beginning 2)
|
|
1610 (match-end 2)))))
|
|
1611 (if (not (and major minor))
|
|
1612 (error "Cannot figure out the major and minor version numbers"))
|
|
1613 ;; calculate the major version
|
|
1614 (cond
|
|
1615 ((= major 4) (setq major 'v18)) ;Epoch 4
|
|
1616 ((= major 18) (setq major 'v18)) ;Emacs 18
|
|
1617 ((= major 19) (setq major 'v19 ;Emacs 19
|
|
1618 flavor (if (or (string-match "Lucid" emacs-version)
|
|
1619 (string-match "XEmacs" emacs-version))
|
|
1620 'XEmacs 'FSF)))
|
|
1621 ((> major 19) (setq major 'v20
|
|
1622 flavor (if (or (string-match "Lucid" emacs-version)
|
|
1623 (string-match "XEmacs" emacs-version))
|
|
1624 'XEmacs 'FSF)))
|
|
1625 ;; I don't know
|
|
1626 (t (error "Cannot recognize major version number: %s" major)))
|
|
1627 ;; XEmacs 19 uses 8-bit modify-syntax-entry flags, as do all
|
|
1628 ;; patched Emacs 19, Emacs 18, Epoch 4's. Only Emacs 19 uses a
|
|
1629 ;; 1-bit flag. Let's be as smart as we can about figuring this
|
|
1630 ;; out.
|
|
1631 (if (or (eq major 'v20) (eq major 'v19))
|
|
1632 (let ((table (copy-syntax-table)))
|
|
1633 (modify-syntax-entry ?a ". 12345678" table)
|
|
1634 (cond
|
|
1635 ;; XEmacs pre 20 and Emacs pre 19.30 use vectors for syntax tables.
|
|
1636 ((vectorp table)
|
|
1637 (if (= (logand (lsh (aref table ?a) -16) 255) 255)
|
|
1638 (setq comments '8-bit)
|
|
1639 (setq comments '1-bit)))
|
|
1640 ;; XEmacs 20 is known to be 8-bit
|
|
1641 ((eq flavor 'XEmacs) (setq comments '8-bit))
|
|
1642 ;; Emacs 19.30 and beyond are known to be 1-bit
|
|
1643 ((eq flavor 'FSF) (setq comments '1-bit))
|
|
1644 ;; Don't know what this is
|
|
1645 (t (error "Couldn't figure out syntax table format"))
|
|
1646 ))
|
|
1647 ;; Emacs 18 has no support for dual comments
|
|
1648 (setq comments 'no-dual-comments))
|
|
1649 ;; determine whether to use old or new font lock syntax
|
|
1650 ;; We can assume 8-bit syntax table emacsen support new syntax, otherwise
|
|
1651 ;; look for version > 19.30
|
|
1652 (setq flock-syntax
|
|
1653 (if (or (equal comments '8-bit)
|
|
1654 (equal major 'v20)
|
|
1655 (and (equal major 'v19) (> minor 30)))
|
|
1656 'flock-syntax-after-1930
|
|
1657 'flock-syntax-before-1930))
|
|
1658 ;; lets do some minimal sanity checking.
|
|
1659 (if (or
|
|
1660 ;; Emacs before 19.6 had bugs
|
|
1661 (and (eq major 'v19) (eq flavor 'XEmacs) (< minor 6))
|
|
1662 ;; Emacs 19 before 19.21 has known bugs
|
|
1663 (and (eq major 'v19) (eq flavor 'FSF) (< minor 21))
|
|
1664 )
|
|
1665 (with-output-to-temp-buffer "*verilog-mode warnings*"
|
|
1666 (print (format
|
|
1667 "The version of Emacs that you are running, %s,
|
|
1668 has known bugs in its syntax parsing routines which will affect the
|
|
1669 performance of verilog-mode. You should strongly consider upgrading to the
|
|
1670 latest available version. verilog-mode may continue to work, after a
|
|
1671 fashion, but strange indentation errors could be encountered."
|
|
1672 emacs-version))))
|
|
1673 ;; Emacs 18, with no patch is not too good
|
|
1674 (if (and (eq major 'v18) (eq comments 'no-dual-comments))
|
|
1675 (with-output-to-temp-buffer "*verilog-mode warnings*"
|
|
1676 (print (format
|
|
1677 "The version of Emacs 18 you are running, %s,
|
|
1678 has known deficiencies in its ability to handle the dual verilog
|
|
1679 (and C++) comments, (e.g. the // and /* */ comments). This will
|
|
1680 not be much of a problem for you if you only use the /* */ comments,
|
|
1681 but you really should strongly consider upgrading to one of the latest
|
|
1682 Emacs 19's. In Emacs 18, you may also experience performance degradations.
|
|
1683 Emacs 19 has some new built-in routines which will speed things up for you.
|
|
1684 Because of these inherent problems, verilog-mode is not supported
|
|
1685 on emacs-18."
|
|
1686 emacs-version))))
|
|
1687 ;; Emacs 18 with the syntax patches are no longer supported
|
|
1688 (if (and (eq major 'v18) (not (eq comments 'no-dual-comments)))
|
|
1689 (with-output-to-temp-buffer "*verilog-mode warnings*"
|
|
1690 (print (format
|
|
1691 "You are running a syntax patched Emacs 18 variant. While this should
|
|
1692 work for you, you may want to consider upgrading to Emacs 19.
|
|
1693 The syntax patches are no longer supported either for verilog-mode."))))
|
|
1694 (list major comments flock-syntax))
|
|
1695 "A list of features extant in the Emacs you are using.
|
|
1696 There are many flavors of Emacs out there, each with different
|
|
1697 features supporting those needed by `verilog-mode'. Here's the current
|
|
1698 supported list, along with the values for this variable:
|
|
1699
|
|
1700 Vanilla Emacs 18/Epoch 4: (v18 no-dual-comments flock-syntax-before-1930)
|
|
1701 Emacs 18/Epoch 4 (patch2): (v18 8-bit flock-syntax-after-1930)
|
|
1702 XEmacs (formerly Lucid) 19: (v19 8-bit flock-syntax-after-1930)
|
|
1703 XEmacs 20: (v20 8-bit flock-syntax-after-1930)
|
|
1704 Emacs 19.1-19.30: (v19 8-bit flock-syntax-before-1930)
|
|
1705 Emacs 19.31-19.xx: (v19 8-bit flock-syntax-after-1930)
|
|
1706 Emacs20 : (v20 1-bit flock-syntax-after-1930).")
|
|
1707
|
|
1708 (defconst verilog-comment-start-regexp "//\\|/\\*"
|
|
1709 "Dual comment value for `comment-start-regexp'.")
|
|
1710
|
|
1711 (defun verilog-populate-syntax-table (table)
|
|
1712 "Populate the syntax TABLE."
|
|
1713 (modify-syntax-entry ?\\ "\\" table)
|
|
1714 (modify-syntax-entry ?+ "." table)
|
|
1715 (modify-syntax-entry ?- "." table)
|
|
1716 (modify-syntax-entry ?= "." table)
|
|
1717 (modify-syntax-entry ?% "." table)
|
|
1718 (modify-syntax-entry ?< "." table)
|
|
1719 (modify-syntax-entry ?> "." table)
|
|
1720 (modify-syntax-entry ?& "." table)
|
|
1721 (modify-syntax-entry ?| "." table)
|
|
1722 (modify-syntax-entry ?` "w" table)
|
|
1723 (modify-syntax-entry ?_ "w" table)
|
|
1724 (modify-syntax-entry ?\' "." table)
|
|
1725 )
|
|
1726
|
|
1727 (defun verilog-setup-dual-comments (table)
|
|
1728 "Set up TABLE to handle block and line style comments."
|
|
1729 (cond
|
|
1730 ((memq '8-bit verilog-emacs-features)
|
|
1731 ;; XEmacs (formerly Lucid) has the best implementation
|
|
1732 (modify-syntax-entry ?/ ". 1456" table)
|
|
1733 (modify-syntax-entry ?* ". 23" table)
|
|
1734 (modify-syntax-entry ?\n "> b" table)
|
|
1735 )
|
|
1736 ((memq '1-bit verilog-emacs-features)
|
|
1737 ;; Emacs 19 does things differently, but we can work with it
|
|
1738 (modify-syntax-entry ?/ ". 124b" table)
|
|
1739 (modify-syntax-entry ?* ". 23" table)
|
|
1740 (modify-syntax-entry ?\n "> b" table)
|
|
1741 )
|
|
1742 ))
|
|
1743
|
|
1744 (defvar verilog-mode-syntax-table nil
|
|
1745 "Syntax table used in `verilog-mode' buffers.")
|
|
1746
|
|
1747 (defconst verilog-font-lock-keywords nil
|
|
1748 "Default highlighting for Verilog mode.")
|
|
1749
|
|
1750 (defconst verilog-font-lock-keywords-1 nil
|
|
1751 "Subdued level highlighting for Verilog mode.")
|
|
1752
|
|
1753 (defconst verilog-font-lock-keywords-2 nil
|
|
1754 "Medium level highlighting for Verilog mode.
|
|
1755 See also `verilog-font-lock-extra-types'.")
|
|
1756
|
|
1757 (defconst verilog-font-lock-keywords-3 nil
|
|
1758 "Gaudy level highlighting for Verilog mode.
|
|
1759 See also `verilog-font-lock-extra-types'.")
|
|
1760 (defvar verilog-font-lock-translate-off-face
|
|
1761 'verilog-font-lock-translate-off-face
|
|
1762 "Font to use for translated off regions.")
|
|
1763 (defface verilog-font-lock-translate-off-face
|
|
1764 '((((class color)
|
|
1765 (background light))
|
|
1766 (:background "gray90" :italic t ))
|
|
1767 (((class color)
|
|
1768 (background dark))
|
|
1769 (:background "gray10" :italic t ))
|
|
1770 (((class grayscale) (background light))
|
|
1771 (:foreground "DimGray" :italic t))
|
|
1772 (((class grayscale) (background dark))
|
|
1773 (:foreground "LightGray" :italic t))
|
|
1774 (t (:italis t)))
|
|
1775 "Font lock mode face used to background highlight translate-off regions."
|
|
1776 :group 'font-lock-highlighting-faces)
|
|
1777
|
|
1778 (defvar verilog-font-lock-p1800-face
|
|
1779 'verilog-font-lock-p1800-face
|
|
1780 "Font to use for p1800 keywords.")
|
|
1781 (defface verilog-font-lock-p1800-face
|
|
1782 '((((class color)
|
|
1783 (background light))
|
|
1784 (:foreground "DarkOrange3" :bold t ))
|
|
1785 (((class color)
|
|
1786 (background dark))
|
|
1787 (:foreground "orange1" :bold t ))
|
|
1788 (t (:italic t)))
|
|
1789 "Font lock mode face used to highlight P1800 keywords."
|
|
1790 :group 'font-lock-highlighting-faces)
|
|
1791
|
|
1792 (defvar verilog-font-lock-ams-face
|
|
1793 'verilog-font-lock-ams-face
|
|
1794 "Font to use for Analog/Mixed Signal keywords.")
|
|
1795 (defface verilog-font-lock-ams-face
|
|
1796 '((((class color)
|
|
1797 (background light))
|
|
1798 (:foreground "Purple" :bold t ))
|
|
1799 (((class color)
|
|
1800 (background dark))
|
|
1801 (:foreground "orange1" :bold t ))
|
|
1802 (t (:italic t)))
|
|
1803 "Font lock mode face used to highlight AMS keywords."
|
|
1804 :group 'font-lock-highlighting-faces)
|
|
1805
|
|
1806 (let* ((verilog-type-font-keywords
|
|
1807 (eval-when-compile
|
|
1808 (verilog-regexp-opt
|
|
1809 '(
|
|
1810 "and" "bit" "buf" "bufif0" "bufif1" "cmos" "defparam"
|
|
1811 "event" "genvar" "inout" "input" "integer" "localparam"
|
|
1812 "logic" "mailbox" "nand" "nmos" "not" "notif0" "notif1" "or"
|
|
1813 "output" "parameter" "pmos" "pull0" "pull1" "pullup"
|
|
1814 "rcmos" "real" "realtime" "reg" "rnmos" "rpmos" "rtran"
|
|
1815 "rtranif0" "rtranif1" "semaphore" "signed" "struct" "supply"
|
|
1816 "supply0" "supply1" "time" "tran" "tranif0" "tranif1"
|
|
1817 "tri" "tri0" "tri1" "triand" "trior" "trireg" "typedef"
|
|
1818 "uwire" "vectored" "wand" "wire" "wor" "xnor" "xor"
|
|
1819 ) nil )))
|
|
1820
|
|
1821 (verilog-pragma-keywords
|
|
1822 (eval-when-compile
|
|
1823 (verilog-regexp-opt
|
|
1824 '("surefire" "synopsys" "rtl_synthesis" "verilint" ) nil
|
|
1825 )))
|
|
1826
|
|
1827 (verilog-p1800-keywords
|
|
1828 (eval-when-compile
|
|
1829 (verilog-regexp-opt
|
|
1830 '("alias" "assert" "assume" "automatic" "before" "bind"
|
|
1831 "bins" "binsof" "break" "byte" "cell" "chandle" "class"
|
|
1832 "clocking" "config" "const" "constraint" "context" "continue"
|
|
1833 "cover" "covergroup" "coverpoint" "cross" "deassign" "design"
|
|
1834 "dist" "do" "edge" "endclass" "endclocking" "endconfig"
|
|
1835 "endgroup" "endprogram" "endproperty" "endsequence" "enum"
|
|
1836 "expect" "export" "extends" "extern" "first_match" "foreach"
|
|
1837 "forkjoin" "genvar" "highz0" "highz1" "ifnone" "ignore_bins"
|
|
1838 "illegal_bins" "import" "incdir" "include" "inside" "instance"
|
|
1839 "int" "intersect" "large" "liblist" "library" "local" "longint"
|
|
1840 "matches" "medium" "modport" "new" "noshowcancelled" "null"
|
|
1841 "packed" "program" "property" "protected" "pull0" "pull1"
|
|
1842 "pulsestyle_onevent" "pulsestyle_ondetect" "pure" "rand" "randc"
|
|
1843 "randcase" "randsequence" "ref" "release" "return" "scalared"
|
|
1844 "sequence" "shortint" "shortreal" "showcancelled" "small" "solve"
|
|
1845 "specparam" "static" "string" "strong0" "strong1" "struct"
|
|
1846 "super" "tagged" "this" "throughout" "timeprecision" "timeunit"
|
|
1847 "type" "union" "unsigned" "use" "var" "virtual" "void"
|
|
1848 "wait_order" "weak0" "weak1" "wildcard" "with" "within"
|
|
1849 ) nil )))
|
|
1850
|
|
1851 (verilog-ams-keywords
|
|
1852 (eval-when-compile
|
|
1853 (verilog-regexp-opt
|
|
1854 '("above" "abs" "absdelay" "acos" "acosh" "ac_stim"
|
|
1855 "aliasparam" "analog" "analysis" "asin" "asinh" "atan" "atan2" "atanh"
|
|
1856 "branch" "ceil" "connectmodule" "connectrules" "cos" "cosh" "ddt"
|
|
1857 "ddx" "discipline" "driver_update" "enddiscipline" "endconnectrules"
|
|
1858 "endnature" "endparamset" "exclude" "exp" "final_step" "flicker_noise"
|
|
1859 "floor" "flow" "from" "ground" "hypot" "idt" "idtmod" "inf"
|
|
1860 "initial_step" "laplace_nd" "laplace_np" "laplace_zd" "laplace_zp"
|
|
1861 "last_crossing" "limexp" "ln" "log" "max" "min" "nature"
|
|
1862 "net_resolution" "noise_table" "paramset" "potential" "pow" "sin"
|
|
1863 "sinh" "slew" "sqrt" "tan" "tanh" "timer" "transition" "white_noise"
|
|
1864 "wreal" "zi_nd" "zi_np" "zi_zd" ) nil )))
|
|
1865
|
|
1866 (verilog-font-keywords
|
|
1867 (eval-when-compile
|
|
1868 (verilog-regexp-opt
|
|
1869 '(
|
|
1870 "assign" "begin" "case" "casex" "casez" "randcase" "deassign"
|
|
1871 "default" "disable" "else" "end" "endcase" "endfunction"
|
|
1872 "endgenerate" "endinterface" "endmodule" "endprimitive"
|
|
1873 "endspecify" "endtable" "endtask" "final" "for" "force" "return" "break"
|
|
1874 "continue" "forever" "fork" "function" "generate" "if" "iff" "initial"
|
|
1875 "interface" "join" "join_any" "join_none" "macromodule" "module" "negedge"
|
|
1876 "package" "endpackage" "always" "always_comb" "always_ff"
|
|
1877 "always_latch" "posedge" "primitive" "priority" "release"
|
|
1878 "repeat" "specify" "table" "task" "unique" "wait" "while"
|
|
1879 "class" "program" "endclass" "endprogram"
|
|
1880 ) nil ))))
|
|
1881
|
|
1882 (setq verilog-font-lock-keywords
|
|
1883 (list
|
|
1884 ;; Fontify all builtin keywords
|
|
1885 (concat "\\<\\(" verilog-font-keywords "\\|"
|
|
1886 ;; And user/system tasks and functions
|
|
1887 "\\$[a-zA-Z][a-zA-Z0-9_\\$]*"
|
|
1888 "\\)\\>")
|
|
1889 ;; Fontify all types
|
|
1890 (cons (concat "\\<\\(" verilog-type-font-keywords "\\)\\>")
|
|
1891 'font-lock-type-face)
|
|
1892 ;; Fontify IEEE-P1800 keywords appropriately
|
|
1893 (if verilog-highlight-p1800-keywords
|
|
1894 (cons (concat "\\<\\(" verilog-p1800-keywords "\\)\\>")
|
|
1895 'verilog-font-lock-p1800-face)
|
|
1896 (cons (concat "\\<\\(" verilog-p1800-keywords "\\)\\>")
|
|
1897 'font-lock-type-face))
|
|
1898 ;; Fontify Verilog-AMS keywords
|
|
1899 (cons (concat "\\<\\(" verilog-ams-keywords "\\)\\>")
|
|
1900 'verilog-font-lock-ams-face)
|
|
1901 ))
|
|
1902
|
|
1903 (setq verilog-font-lock-keywords-1
|
|
1904 (append verilog-font-lock-keywords
|
|
1905 (list
|
|
1906 ;; Fontify module definitions
|
|
1907 (list
|
|
1908 "\\<\\(\\(macro\\)?module\\|primitive\\|class\\|program\\|interface\\|package\\|task\\)\\>\\s-*\\(\\sw+\\)"
|
|
1909 '(1 font-lock-keyword-face)
|
|
1910 '(3 font-lock-function-name-face 'prepend))
|
|
1911 ;; Fontify function definitions
|
|
1912 (list
|
|
1913 (concat "\\<function\\>\\s-+\\(integer\\|real\\(time\\)?\\|time\\)\\s-+\\(\\sw+\\)" )
|
|
1914 '(1 font-lock-keyword-face)
|
|
1915 '(3 font-lock-reference-face prepend)
|
|
1916 )
|
|
1917 '("\\<function\\>\\s-+\\(\\[[^]]+\\]\\)\\s-+\\(\\sw+\\)"
|
|
1918 (1 font-lock-keyword-face)
|
|
1919 (2 font-lock-reference-face append)
|
|
1920 )
|
|
1921 '("\\<function\\>\\s-+\\(\\sw+\\)"
|
|
1922 1 'font-lock-reference-face append)
|
|
1923 )))
|
|
1924
|
|
1925 (setq verilog-font-lock-keywords-2
|
|
1926 (append verilog-font-lock-keywords-1
|
|
1927 (list
|
|
1928 ;; Fontify pragmas
|
|
1929 (concat "\\(//\\s-*" verilog-pragma-keywords "\\s-.*\\)")
|
|
1930 ;; Fontify escaped names
|
|
1931 '("\\(\\\\\\S-*\\s-\\)" 0 font-lock-function-name-face)
|
|
1932 ;; Fontify macro definitions/ uses
|
|
1933 '("`\\s-*[A-Za-z][A-Za-z0-9_]*" 0 (if (boundp 'font-lock-preprocessor-face)
|
|
1934 'font-lock-preprocessor-face
|
|
1935 'font-lock-type-face))
|
|
1936 ;; Fontify delays/numbers
|
|
1937 '("\\(@\\)\\|\\(#\\s-*\\(\\(\[0-9_.\]+\\('s?[hdxbo][0-9a-fA-F_xz]*\\)?\\)\\|\\(([^()]+)\\|\\sw+\\)\\)\\)"
|
|
1938 0 font-lock-type-face append)
|
|
1939 ;; Fontify instantiation names
|
|
1940 '("\\([A-Za-z][A-Za-z0-9_]+\\)\\s-*(" 1 font-lock-function-name-face)
|
|
1941
|
|
1942 )))
|
|
1943
|
|
1944 (setq verilog-font-lock-keywords-3
|
|
1945 (append verilog-font-lock-keywords-2
|
|
1946 (when verilog-highlight-translate-off
|
|
1947 (list
|
|
1948 ;; Fontify things in translate off regions
|
|
1949 '(verilog-match-translate-off (0 'verilog-font-lock-translate-off-face prepend))
|
|
1950 )))
|
|
1951 )
|
|
1952 )
|
|
1953
|
|
1954
|
|
1955
|
|
1956 (defun verilog-inside-comment-p ()
|
|
1957 "Check if point inside a nested comment."
|
|
1958 (save-excursion
|
|
1959 (let ((st-point (point)) hitbeg)
|
|
1960 (or (search-backward "//" (verilog-get-beg-of-line) t)
|
|
1961 (if (progn
|
|
1962 ;; This is for tricky case //*, we keep searching if /* is proceeded by // on same line
|
|
1963 (while (and (setq hitbeg (search-backward "/*" nil t))
|
|
1964 (progn (forward-char 1) (search-backward "//" (verilog-get-beg-of-line) t))))
|
|
1965 hitbeg)
|
|
1966 (not (search-forward "*/" st-point t)))))))
|
|
1967
|
|
1968 (defun verilog-declaration-end ()
|
|
1969 (search-forward ";"))
|
|
1970
|
|
1971 (defun verilog-point-text (&optional pointnum)
|
|
1972 "Return text describing where POINTNUM or current point is (for errors).
|
|
1973 Use filename, if current buffer being edited shorten to just buffer name."
|
|
1974 (concat (or (and (equal (window-buffer (selected-window)) (current-buffer))
|
|
1975 (buffer-name))
|
|
1976 buffer-file-name
|
|
1977 (buffer-name))
|
|
1978 ":" (int-to-string (count-lines (point-min) (or pointnum (point))))))
|
|
1979
|
|
1980 (defun electric-verilog-backward-sexp ()
|
|
1981 "Move backward over a sexp."
|
|
1982 (interactive)
|
|
1983 ;; before that see if we are in a comment
|
|
1984 (verilog-backward-sexp)
|
|
1985 )
|
|
1986 (defun electric-verilog-forward-sexp ()
|
|
1987 "Move backward over a sexp."
|
|
1988 (interactive)
|
|
1989 ;; before that see if we are in a comment
|
|
1990 (verilog-forward-sexp)
|
|
1991 )
|
|
1992 ;;;used by hs-minor-mode
|
|
1993 (defun verilog-forward-sexp-function (arg)
|
|
1994 (if (< arg 0)
|
|
1995 (verilog-backward-sexp)
|
|
1996 (verilog-forward-sexp)))
|
|
1997
|
|
1998
|
|
1999 (defun verilog-backward-sexp ()
|
|
2000 (let ((reg)
|
|
2001 (elsec 1)
|
|
2002 (found nil)
|
|
2003 (st (point))
|
|
2004 )
|
|
2005 (if (not (looking-at "\\<"))
|
|
2006 (forward-word -1))
|
|
2007 (cond
|
|
2008 ((verilog-skip-backward-comment-or-string)
|
|
2009 )
|
|
2010 ((looking-at "\\<else\\>")
|
|
2011 (setq reg (concat
|
|
2012 verilog-end-block-re
|
|
2013 "\\|\\(\\<else\\>\\)"
|
|
2014 "\\|\\(\\<if\\>\\)"
|
|
2015 ))
|
|
2016 (while (and (not found)
|
|
2017 (verilog-re-search-backward reg nil 'move))
|
|
2018 (cond
|
|
2019 ((match-end 1) ; matched verilog-end-block-re
|
|
2020 ; try to leap back to matching outward block by striding across
|
|
2021 ; indent level changing tokens then immediately
|
|
2022 ; previous line governs indentation.
|
|
2023 (verilog-leap-to-head))
|
|
2024 ((match-end 2) ; else, we're in deep
|
|
2025 (setq elsec (1+ elsec)))
|
|
2026 ((match-end 3) ; found it
|
|
2027 (setq elsec (1- elsec))
|
|
2028 (if (= 0 elsec)
|
|
2029 ;; Now previous line describes syntax
|
|
2030 (setq found 't)
|
|
2031 ))
|
|
2032 )
|
|
2033 )
|
|
2034 )
|
|
2035 ((looking-at verilog-end-block-re)
|
|
2036 (verilog-leap-to-head))
|
|
2037 ((looking-at "\\(endmodule\\>\\)\\|\\(\\<endprimitive\\>\\)\\|\\(\\<endclass\\>\\)\\|\\(\\<endprogram\\>\\)\\|\\(\\<endinterface\\>\\)\\|\\(\\<endpackage\\>\\)")
|
|
2038 (cond
|
|
2039 ((match-end 1)
|
|
2040 (verilog-re-search-backward "\\<\\(macro\\)?module\\>" nil 'move))
|
|
2041 ((match-end 2)
|
|
2042 (verilog-re-search-backward "\\<primitive\\>" nil 'move))
|
|
2043 ((match-end 3)
|
|
2044 (verilog-re-search-backward "\\<class\\>" nil 'move))
|
|
2045 ((match-end 4)
|
|
2046 (verilog-re-search-backward "\\<program\\>" nil 'move))
|
|
2047 ((match-end 5)
|
|
2048 (verilog-re-search-backward "\\<interface\\>" nil 'move))
|
|
2049 ((match-end 6)
|
|
2050 (verilog-re-search-backward "\\<package\\>" nil 'move))
|
|
2051 (t
|
|
2052 (goto-char st)
|
|
2053 (backward-sexp 1))))
|
|
2054 (t
|
|
2055 (goto-char st)
|
|
2056 (backward-sexp))
|
|
2057 ) ;; cond
|
|
2058 ))
|
|
2059
|
|
2060 (defun verilog-forward-sexp ()
|
|
2061 (let ((reg)
|
|
2062 (md 2)
|
|
2063 (st (point)))
|
|
2064 (if (not (looking-at "\\<"))
|
|
2065 (forward-word -1))
|
|
2066 (cond
|
|
2067 ((verilog-skip-forward-comment-or-string)
|
|
2068 (verilog-forward-syntactic-ws)
|
|
2069 )
|
|
2070 ((looking-at verilog-beg-block-re-ordered);; begin|case|fork|class|table|specify|function|task|generate|covergroup|property|sequence|clocking
|
|
2071 (cond
|
|
2072 ((match-end 1) ; end
|
|
2073 ;; Search forward for matching begin
|
|
2074 (setq reg "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)" ))
|
|
2075 ((match-end 2) ; endcase
|
|
2076 ;; Search forward for matching case
|
|
2077 (setq reg "\\(\\<randcase\\>\\|\\(\\<unique\\>\\s-+\\|\\<priority\\>\\s-+\\)?\\<case[xz]?\\>[^:]\\)\\|\\(\\<endcase\\>\\)" )
|
|
2078 )
|
|
2079 ((match-end 3) ; join
|
|
2080 ;; Search forward for matching fork
|
|
2081 (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" ))
|
|
2082 ((match-end 4) ; endclass
|
|
2083 ;; Search forward for matching class
|
|
2084 (setq reg "\\(\\<class\\>\\)\\|\\(\\<endclass\\>\\)" ))
|
|
2085 ((match-end 5) ; endtable
|
|
2086 ;; Search forward for matching table
|
|
2087 (setq reg "\\(\\<table\\>\\)\\|\\(\\<endtable\\>\\)" ))
|
|
2088 ((match-end 6) ; endspecify
|
|
2089 ;; Search forward for matching specify
|
|
2090 (setq reg "\\(\\<specify\\>\\)\\|\\(\\<endspecify\\>\\)" ))
|
|
2091 ((match-end 7) ; endfunction
|
|
2092 ;; Search forward for matching function
|
|
2093 (setq reg "\\(\\<function\\>\\)\\|\\(\\<endfunction\\>\\)" ))
|
|
2094 ((match-end 8) ; endtask
|
|
2095 ;; Search forward for matching task
|
|
2096 (setq reg "\\(\\<task\\>\\)\\|\\(\\<endtask\\>\\)" ))
|
|
2097 ((match-end 9) ; endgenerate
|
|
2098 ;; Search forward for matching generate
|
|
2099 (setq reg "\\(\\<generate\\>\\)\\|\\(\\<endgenerate\\>\\)" ))
|
|
2100 ((match-end 10) ; endgroup
|
|
2101 ;; Search forward for matching covergroup
|
|
2102 (setq reg "\\(\\<covergroup\\>\\)\\|\\(\\<endgroup\\>\\)" ))
|
|
2103 ((match-end 11) ; endproperty
|
|
2104 ;; Search forward for matching property
|
|
2105 (setq reg "\\(\\<property\\>\\)\\|\\(\\<endproperty\\>\\)" ))
|
|
2106 ((match-end 12) ; endsequence
|
|
2107 ;; Search forward for matching sequence
|
|
2108 (setq reg "\\(\\<\\(rand\\)?sequence\\>\\)\\|\\(\\<endsequence\\>\\)" )
|
|
2109 (setq md 3) ; 3 to get to endsequence in the reg above
|
|
2110 )
|
|
2111 ((match-end 13) ; endclocking
|
|
2112 ;; Search forward for matching clocking
|
|
2113 (setq reg "\\(\\<clocking\\>\\)\\|\\(\\<endclocking\\>\\)" ))
|
|
2114 )
|
|
2115 (if (forward-word 1)
|
|
2116 (catch 'skip
|
|
2117 (let ((nest 1))
|
|
2118 (while (verilog-re-search-forward reg nil 'move)
|
|
2119 (cond
|
|
2120 ((match-end md) ; the closer in reg, so we are climbing out
|
|
2121 (setq nest (1- nest))
|
|
2122 (if (= 0 nest) ; we are out!
|
|
2123 (throw 'skip 1)))
|
|
2124 ((match-end 1) ; the opener in reg, so we are deeper now
|
|
2125 (setq nest (1+ nest)))))
|
|
2126 )))
|
|
2127 )
|
|
2128 ((looking-at (concat
|
|
2129 "\\(\\<\\(macro\\)?module\\>\\)\\|"
|
|
2130 "\\(\\<primitive\\>\\)\\|"
|
|
2131 "\\(\\<class\\>\\)\\|"
|
|
2132 "\\(\\<program\\>\\)\\|"
|
|
2133 "\\(\\<interface\\>\\)\\|"
|
|
2134 "\\(\\<package\\>\\)"))
|
|
2135 (cond
|
|
2136 ((match-end 1)
|
|
2137 (verilog-re-search-forward "\\<endmodule\\>" nil 'move))
|
|
2138 ((match-end 2)
|
|
2139 (verilog-re-search-forward "\\<endprimitive\\>" nil 'move))
|
|
2140 ((match-end 3)
|
|
2141 (verilog-re-search-forward "\\<endclass\\>" nil 'move))
|
|
2142 ((match-end 4)
|
|
2143 (verilog-re-search-forward "\\<endprogram\\>" nil 'move))
|
|
2144 ((match-end 5)
|
|
2145 (verilog-re-search-forward "\\<endinterface\\>" nil 'move))
|
|
2146 ((match-end 6)
|
|
2147 (verilog-re-search-forward "\\<endpackage\\>" nil 'move))
|
|
2148 (t
|
|
2149 (goto-char st)
|
|
2150 (if (= (following-char) ?\) )
|
|
2151 (forward-char 1)
|
|
2152 (forward-sexp 1)))))
|
|
2153 (t
|
|
2154 (goto-char st)
|
|
2155 (if (= (following-char) ?\) )
|
|
2156 (forward-char 1)
|
|
2157 (forward-sexp 1)))
|
|
2158 ) ;; cond
|
|
2159 ))
|
|
2160
|
|
2161 (defun verilog-declaration-beg ()
|
|
2162 (verilog-re-search-backward verilog-declaration-re (bobp) t))
|
|
2163
|
|
2164 ;;
|
|
2165 ;; Macros
|
|
2166 ;;
|
|
2167
|
|
2168 (defsubst verilog-string-replace-matches (from-string to-string fixedcase literal string)
|
|
2169 "Replace occurrences of FROM-STRING with TO-STRING.
|
|
2170 FIXEDCASE and LITERAL as in `replace-match`. STRING is what to replace.
|
|
2171 The case (verilog-string-replace-matches \"o\" \"oo\" nil nil \"foobar\")
|
|
2172 will break, as the o's continuously replace. xa -> x works ok though."
|
|
2173 ;; Hopefully soon to a emacs built-in
|
|
2174 (let ((start 0))
|
|
2175 (while (string-match from-string string start)
|
|
2176 (setq string (replace-match to-string fixedcase literal string)
|
|
2177 start (min (length string) (match-end 0))))
|
|
2178 string))
|
|
2179
|
|
2180 (defsubst verilog-string-remove-spaces (string)
|
|
2181 "Remove spaces surrounding STRING."
|
|
2182 (save-match-data
|
|
2183 (setq string (verilog-string-replace-matches "^\\s-+" "" nil nil string))
|
|
2184 (setq string (verilog-string-replace-matches "\\s-+$" "" nil nil string))
|
|
2185 string))
|
|
2186
|
|
2187 (defsubst verilog-re-search-forward (REGEXP BOUND NOERROR)
|
|
2188 ; checkdoc-params: (REGEXP BOUND NOERROR)
|
|
2189 "Like `re-search-forward', but skips over match in comments or strings."
|
|
2190 (store-match-data '(nil nil))
|
|
2191 (while (and
|
|
2192 (re-search-forward REGEXP BOUND NOERROR)
|
|
2193 (and (verilog-skip-forward-comment-or-string)
|
|
2194 (progn
|
|
2195 (store-match-data '(nil nil))
|
|
2196 (if BOUND
|
|
2197 (< (point) BOUND)
|
|
2198 t)
|
|
2199 ))))
|
|
2200 (match-end 0))
|
|
2201
|
|
2202 (defsubst verilog-re-search-backward (REGEXP BOUND NOERROR)
|
|
2203 ; checkdoc-params: (REGEXP BOUND NOERROR)
|
|
2204 "Like `re-search-backward', but skips over match in comments or strings."
|
|
2205 (store-match-data '(nil nil))
|
|
2206 (while (and
|
|
2207 (re-search-backward REGEXP BOUND NOERROR)
|
|
2208 (and (verilog-skip-backward-comment-or-string)
|
|
2209 (progn
|
|
2210 (store-match-data '(nil nil))
|
|
2211 (if BOUND
|
|
2212 (> (point) BOUND)
|
|
2213 t)
|
|
2214 ))))
|
|
2215 (match-end 0))
|
|
2216
|
|
2217 (defsubst verilog-re-search-forward-quick (regexp bound noerror)
|
|
2218 "Like `verilog-re-search-forward', including use of REGEXP BOUND and NOERROR,
|
|
2219 but trashes match data and is faster for REGEXP that doesn't match often.
|
|
2220 This may at some point use text properties to ignore comments,
|
|
2221 so there may be a large up front penalty for the first search."
|
|
2222 (let (pt)
|
|
2223 (while (and (not pt)
|
|
2224 (re-search-forward regexp bound noerror))
|
|
2225 (if (not (verilog-inside-comment-p))
|
|
2226 (setq pt (match-end 0))))
|
|
2227 pt))
|
|
2228
|
|
2229 (defsubst verilog-re-search-backward-quick (regexp bound noerror)
|
|
2230 ; checkdoc-params: (REGEXP BOUND NOERROR)
|
|
2231 "Like `verilog-re-search-backward', including use of REGEXP BOUND and NOERROR,
|
|
2232 but trashes match data and is faster for REGEXP that doesn't match often.
|
|
2233 This may at some point use text properties to ignore comments,
|
|
2234 so there may be a large up front penalty for the first search."
|
|
2235 (let (pt)
|
|
2236 (while (and (not pt)
|
|
2237 (re-search-backward regexp bound noerror))
|
|
2238 (if (not (verilog-inside-comment-p))
|
|
2239 (setq pt (match-end 0))))
|
|
2240 pt))
|
|
2241
|
|
2242 (defsubst verilog-get-beg-of-line (&optional arg)
|
|
2243 (save-excursion
|
|
2244 (beginning-of-line arg)
|
|
2245 (point)))
|
|
2246
|
|
2247 (defsubst verilog-get-end-of-line (&optional arg)
|
|
2248 (save-excursion
|
|
2249 (end-of-line arg)
|
|
2250 (point)))
|
|
2251
|
|
2252 (defsubst verilog-within-string ()
|
|
2253 (save-excursion
|
|
2254 (nth 3 (parse-partial-sexp (verilog-get-beg-of-line) (point)))))
|
|
2255
|
|
2256 (require 'font-lock)
|
|
2257 (defvar verilog-need-fld 1)
|
|
2258 (defvar font-lock-defaults-alist nil) ;In case we are XEmacs
|
|
2259
|
|
2260 (defun verilog-font-lock-init ()
|
|
2261 "Initialize fontification."
|
|
2262 ;; highlight keywords and standardized types, attributes, enumeration
|
|
2263 ;; values, and subprograms
|
|
2264 (setq verilog-font-lock-keywords-3
|
|
2265 (append verilog-font-lock-keywords-2
|
|
2266 (when verilog-highlight-translate-off
|
|
2267 (list
|
|
2268 ;; Fontify things in translate off regions
|
|
2269 '(verilog-match-translate-off (0 'verilog-font-lock-translate-off-face prepend))
|
|
2270 ))
|
|
2271 )
|
|
2272 )
|
|
2273 (put 'verilog-mode 'font-lock-defaults
|
|
2274 '((verilog-font-lock-keywords
|
|
2275 verilog-font-lock-keywords-1
|
|
2276 verilog-font-lock-keywords-2
|
|
2277 verilog-font-lock-keywords-3
|
|
2278 )
|
|
2279 nil ;; nil means highlight strings & comments as well as keywords
|
|
2280 nil ;; nil means keywords must match case
|
|
2281 nil ;; syntax table handled elsewhere
|
|
2282 verilog-beg-of-defun ;; function to move to beginning of reasonable region to highlight
|
|
2283 ))
|
|
2284 (if verilog-need-fld
|
|
2285 (let ((verilog-mode-defaults
|
|
2286 '((verilog-font-lock-keywords
|
|
2287 verilog-font-lock-keywords-1
|
|
2288 verilog-font-lock-keywords-2
|
|
2289 verilog-font-lock-keywords-3
|
|
2290 )
|
|
2291 nil ;; nil means highlight strings & comments as well as keywords
|
|
2292 nil ;; nil means keywords must match case
|
|
2293 nil ;; syntax table handled elsewhere
|
|
2294 verilog-beg-of-defun ;; function to move to beginning of reasonable region to highlight
|
|
2295 )))
|
|
2296 (setq font-lock-defaults-alist
|
|
2297 (append
|
|
2298 font-lock-defaults-alist
|
|
2299 (list (cons 'verilog-mode verilog-mode-defaults))))
|
|
2300 (setq verilog-need-fld 0))))
|
|
2301
|
|
2302 ;; initialize fontification for Verilog Mode
|
|
2303 (verilog-font-lock-init)
|
|
2304 ;; start up message
|
|
2305 (defconst verilog-startup-message-lines
|
|
2306 '("Please use \\[verilog-submit-bug-report] to report bugs."
|
|
2307 "Visit http://www.verilog.com to check for updates"
|
|
2308 ))
|
|
2309 (defconst verilog-startup-message-displayed t)
|
|
2310 (defun verilog-display-startup-message ()
|
|
2311 (if (not verilog-startup-message-displayed)
|
|
2312 (if (sit-for 5)
|
|
2313 (let ((lines verilog-startup-message-lines))
|
|
2314 (message "verilog-mode version %s, released %s; type \\[describe-mode] for help"
|
|
2315 verilog-mode-version verilog-mode-release-date)
|
|
2316 (setq verilog-startup-message-displayed t)
|
|
2317 (while (and (sit-for 4) lines)
|
|
2318 (message (substitute-command-keys (car lines)))
|
|
2319 (setq lines (cdr lines)))))
|
|
2320 (message "")))
|
|
2321 ;;
|
|
2322 ;;
|
|
2323 ;; Mode
|
|
2324 ;;
|
|
2325 (defvar verilog-which-tool 1)
|
|
2326 ;;###autoload
|
|
2327 (defun verilog-mode ()
|
|
2328 "Major mode for editing Verilog code.
|
|
2329 \\<verilog-mode-map>
|
|
2330 See \\[describe-function] verilog-auto (\\[verilog-auto]) for details on how
|
|
2331 AUTOs can improve coding efficiency.
|
|
2332
|
|
2333 Use \\[verilog-faq] for a pointer to frequently asked questions.
|
|
2334
|
|
2335 NEWLINE, TAB indents for Verilog code.
|
|
2336 Delete converts tabs to spaces as it moves back.
|
|
2337
|
|
2338 Supports highlighting.
|
|
2339
|
|
2340 Turning on Verilog mode calls the value of the variable `verilog-mode-hook'
|
|
2341 with no args, if that value is non-nil.
|
|
2342
|
|
2343 Variables controlling indentation/edit style:
|
|
2344
|
|
2345 variable `verilog-indent-level' (default 3)
|
|
2346 Indentation of Verilog statements with respect to containing block.
|
|
2347 `verilog-indent-level-module' (default 3)
|
|
2348 Absolute indentation of Module level Verilog statements.
|
|
2349 Set to 0 to get initial and always statements lined up
|
|
2350 on the left side of your screen.
|
|
2351 `verilog-indent-level-declaration' (default 3)
|
|
2352 Indentation of declarations with respect to containing block.
|
|
2353 Set to 0 to get them list right under containing block.
|
|
2354 `verilog-indent-level-behavioral' (default 3)
|
|
2355 Indentation of first begin in a task or function block
|
|
2356 Set to 0 to get such code to lined up underneath the task or function keyword
|
|
2357 `verilog-indent-level-directive' (default 1)
|
|
2358 Indentation of `ifdef/`endif blocks
|
|
2359 `verilog-cexp-indent' (default 1)
|
|
2360 Indentation of Verilog statements broken across lines i.e.:
|
|
2361 if (a)
|
|
2362 begin
|
|
2363 `verilog-case-indent' (default 2)
|
|
2364 Indentation for case statements.
|
|
2365 `verilog-auto-newline' (default nil)
|
|
2366 Non-nil means automatically newline after semicolons and the punctuation
|
|
2367 mark after an end.
|
|
2368 `verilog-auto-indent-on-newline' (default t)
|
|
2369 Non-nil means automatically indent line after newline
|
|
2370 `verilog-tab-always-indent' (default t)
|
|
2371 Non-nil means TAB in Verilog mode should always reindent the current line,
|
|
2372 regardless of where in the line point is when the TAB command is used.
|
|
2373 `verilog-indent-begin-after-if' (default t)
|
|
2374 Non-nil means to indent begin statements following a preceding
|
|
2375 if, else, while, for and repeat statements, if any. otherwise,
|
|
2376 the begin is lined up with the preceding token. If t, you get:
|
|
2377 if (a)
|
|
2378 begin // amount of indent based on `verilog-cexp-indent'
|
|
2379 otherwise you get:
|
|
2380 if (a)
|
|
2381 begin
|
|
2382 `verilog-auto-endcomments' (default t)
|
|
2383 Non-nil means a comment /* ... */ is set after the ends which ends
|
|
2384 cases, tasks, functions and modules.
|
|
2385 The type and name of the object will be set between the braces.
|
|
2386 `verilog-minimum-comment-distance' (default 10)
|
|
2387 Minimum distance (in lines) between begin and end required before a comment
|
|
2388 will be inserted. Setting this variable to zero results in every
|
|
2389 end acquiring a comment; the default avoids too many redundant
|
|
2390 comments in tight quarters.
|
|
2391 `verilog-auto-lineup' (default `(all))
|
|
2392 List of contexts where auto lineup of code should be done.
|
|
2393
|
|
2394 Variables controlling other actions:
|
|
2395
|
|
2396 `verilog-linter' (default surelint)
|
|
2397 Unix program to call to run the lint checker. This is the default
|
|
2398 command for \\[compile-command] and \\[verilog-auto-save-compile].
|
|
2399
|
|
2400 See \\[customize] for the complete list of variables.
|
|
2401
|
|
2402 AUTO expansion functions are, in part:
|
|
2403
|
|
2404 \\[verilog-auto] Expand AUTO statements.
|
|
2405 \\[verilog-delete-auto] Remove the AUTOs.
|
|
2406 \\[verilog-inject-auto] Insert AUTOs for the first time.
|
|
2407
|
|
2408 Some other functions are:
|
|
2409
|
|
2410 \\[verilog-complete-word] Complete word with appropriate possibilities.
|
|
2411 \\[verilog-mark-defun] Mark function.
|
|
2412 \\[verilog-beg-of-defun] Move to beginning of current function.
|
|
2413 \\[verilog-end-of-defun] Move to end of current function.
|
|
2414 \\[verilog-label-be] Label matching begin ... end, fork ... join, etc statements.
|
|
2415
|
|
2416 \\[verilog-comment-region] Put marked area in a comment.
|
|
2417 \\[verilog-uncomment-region] Uncomment an area commented with \\[verilog-comment-region].
|
|
2418 \\[verilog-insert-block] Insert begin ... end;.
|
|
2419 \\[verilog-star-comment] Insert /* ... */.
|
|
2420
|
|
2421 \\[verilog-sk-always] Insert a always @(AS) begin .. end block.
|
|
2422 \\[verilog-sk-begin] Insert a begin .. end block.
|
|
2423 \\[verilog-sk-case] Insert a case block, prompting for details.
|
|
2424 \\[verilog-sk-for] Insert a for (...) begin .. end block, prompting for details.
|
|
2425 \\[verilog-sk-generate] Insert a generate .. endgenerate block.
|
|
2426 \\[verilog-sk-header] Insert a nice header block at the top of file.
|
|
2427 \\[verilog-sk-initial] Insert an initial begin .. end block.
|
|
2428 \\[verilog-sk-fork] Insert a fork begin .. end .. join block.
|
|
2429 \\[verilog-sk-module] Insert a module .. (/*AUTOARG*/);.. endmodule block.
|
|
2430 \\[verilog-sk-primitive] Insert a primitive .. (.. );.. endprimitive block.
|
|
2431 \\[verilog-sk-repeat] Insert a repeat (..) begin .. end block.
|
|
2432 \\[verilog-sk-specify] Insert a specify .. endspecify block.
|
|
2433 \\[verilog-sk-task] Insert a task .. begin .. end endtask block.
|
|
2434 \\[verilog-sk-while] Insert a while (...) begin .. end block, prompting for details.
|
|
2435 \\[verilog-sk-casex] Insert a casex (...) item: begin.. end endcase block, prompting for details.
|
|
2436 \\[verilog-sk-casez] Insert a casez (...) item: begin.. end endcase block, prompting for details.
|
|
2437 \\[verilog-sk-if] Insert an if (..) begin .. end block.
|
|
2438 \\[verilog-sk-else-if] Insert an else if (..) begin .. end block.
|
|
2439 \\[verilog-sk-comment] Insert a comment block.
|
|
2440 \\[verilog-sk-assign] Insert an assign .. = ..; statement.
|
|
2441 \\[verilog-sk-function] Insert a function .. begin .. end endfunction block.
|
|
2442 \\[verilog-sk-input] Insert an input declaration, prompting for details.
|
|
2443 \\[verilog-sk-output] Insert an output declaration, prompting for details.
|
|
2444 \\[verilog-sk-state-machine] Insert a state machine definition, prompting for details.
|
|
2445 \\[verilog-sk-inout] Insert an inout declaration, prompting for details.
|
|
2446 \\[verilog-sk-wire] Insert a wire declaration, prompting for details.
|
|
2447 \\[verilog-sk-reg] Insert a register declaration, prompting for details.
|
|
2448 \\[verilog-sk-define-signal] Define signal under point as a register at the top of the module.
|
|
2449
|
|
2450 All key bindings can be seen in a Verilog-buffer with \\[describe-bindings].
|
|
2451 Key bindings specific to `verilog-mode-map' are:
|
|
2452
|
|
2453 \\{verilog-mode-map}"
|
|
2454 (interactive)
|
|
2455 (kill-all-local-variables)
|
|
2456 (use-local-map verilog-mode-map)
|
|
2457 (setq major-mode 'verilog-mode)
|
|
2458 (setq mode-name "Verilog")
|
|
2459 (setq local-abbrev-table verilog-mode-abbrev-table)
|
|
2460 (setq verilog-mode-syntax-table (make-syntax-table))
|
|
2461 (verilog-populate-syntax-table verilog-mode-syntax-table)
|
|
2462 ;; add extra comment syntax
|
|
2463 (verilog-setup-dual-comments verilog-mode-syntax-table)
|
|
2464 (set-syntax-table verilog-mode-syntax-table)
|
|
2465 (make-local-variable 'indent-line-function)
|
|
2466 (setq indent-line-function 'verilog-indent-line-relative)
|
|
2467 (setq comment-indent-function 'verilog-comment-indent)
|
|
2468 (make-local-variable 'parse-sexp-ignore-comments)
|
|
2469 (setq parse-sexp-ignore-comments nil)
|
|
2470 (make-local-variable 'comment-start)
|
|
2471 (make-local-variable 'comment-end)
|
|
2472 (make-local-variable 'comment-multi-line)
|
|
2473 (make-local-variable 'comment-start-skip)
|
|
2474 (setq comment-start "// "
|
|
2475 comment-end ""
|
|
2476 comment-start-skip "/\\*+ *\\|// *"
|
|
2477 comment-multi-line nil)
|
|
2478 ;; Set up for compilation
|
|
2479 (setq verilog-which-tool 1)
|
|
2480 (setq verilog-tool 'verilog-linter)
|
|
2481 (verilog-set-compile-command)
|
|
2482 (when (boundp 'hack-local-variables-hook) ;; Also modify any file-local-variables
|
|
2483 (add-hook 'hack-local-variables-hook 'verilog-modify-compile-command t))
|
|
2484
|
|
2485 ;; Setting up menus
|
|
2486 (if (featurep 'xemacs)
|
|
2487 (progn
|
|
2488 (if (and current-menubar
|
|
2489 (not (assoc "Verilog" current-menubar)))
|
|
2490 (progn
|
|
2491 ;; (set-buffer-menubar (copy-sequence current-menubar))
|
|
2492 (add-submenu nil verilog-xemacs-menu)
|
|
2493 (add-submenu nil verilog-stmt-menu)
|
|
2494 )
|
|
2495 )
|
|
2496 ))
|
|
2497 ;; Stuff for GNU emacs
|
|
2498 (make-local-variable 'font-lock-defaults)
|
|
2499 ;;------------------------------------------------------------
|
|
2500 ;; now hook in 'verilog-colorize-include-files (eldo-mode.el&spice-mode.el)
|
|
2501 ;; all buffer local:
|
|
2502 (make-local-hook 'font-lock-mode-hook)
|
|
2503 (make-local-hook 'font-lock-after-fontify-buffer-hook); doesn't exist in emacs 20
|
|
2504 (add-hook 'font-lock-mode-hook 'verilog-colorize-include-files-buffer t t)
|
|
2505 (add-hook 'font-lock-after-fontify-buffer-hook 'verilog-colorize-include-files-buffer t t) ; not in emacs 20
|
|
2506 (make-local-hook 'after-change-functions)
|
|
2507 (add-hook 'after-change-functions 'verilog-colorize-include-files t t)
|
|
2508
|
|
2509 ;; Tell imenu how to handle verilog.
|
|
2510 (make-local-variable 'imenu-generic-expression)
|
|
2511 (setq imenu-generic-expression verilog-imenu-generic-expression)
|
|
2512 ;; hideshow support
|
|
2513 (unless (assq 'verilog-mode hs-special-modes-alist)
|
|
2514 (setq hs-special-modes-alist
|
|
2515 (cons '(verilog-mode-mode "\\<begin\\>" "\\<end\\>" nil
|
|
2516 verilog-forward-sexp-function)
|
|
2517 hs-special-modes-alist)))
|
|
2518 ;; Display version splash information.
|
|
2519 (verilog-display-startup-message)
|
|
2520
|
|
2521 ;; Stuff for autos
|
|
2522 (add-hook 'write-contents-hooks 'verilog-auto-save-check) ; already local
|
|
2523 ;; (verilog-auto-reeval-locals t) ; Save locals in case user changes them
|
|
2524 ;; (verilog-getopt-flags)
|
|
2525 (run-hooks 'verilog-mode-hook))
|
|
2526
|
|
2527
|
|
2528 ;;
|
|
2529 ;; Electric functions
|
|
2530 ;;
|
|
2531 (defun electric-verilog-terminate-line (&optional arg)
|
|
2532 "Terminate line and indent next line.
|
|
2533 With optional ARG, remove existing end of line comments."
|
|
2534 (interactive)
|
|
2535 ;; before that see if we are in a comment
|
|
2536 (let ((state
|
|
2537 (save-excursion
|
|
2538 (parse-partial-sexp (point-min) (point)))))
|
|
2539 (cond
|
|
2540 ((nth 7 state) ; Inside // comment
|
|
2541 (if (eolp)
|
|
2542 (progn
|
|
2543 (delete-horizontal-space)
|
|
2544 (newline))
|
|
2545 (progn
|
|
2546 (newline)
|
|
2547 (insert-string "// ")
|
|
2548 (beginning-of-line)))
|
|
2549 (verilog-indent-line))
|
|
2550 ((nth 4 state) ; Inside any comment (hence /**/)
|
|
2551 (newline)
|
|
2552 (verilog-more-comment))
|
|
2553 ((eolp)
|
|
2554 ;; First, check if current line should be indented
|
|
2555 (if (save-excursion
|
|
2556 (delete-horizontal-space)
|
|
2557 (beginning-of-line)
|
|
2558 (skip-chars-forward " \t")
|
|
2559 (if (looking-at verilog-auto-end-comment-lines-re)
|
|
2560 (let ((indent-str (verilog-indent-line)))
|
|
2561 ;; Maybe we should set some endcomments
|
|
2562 (if verilog-auto-endcomments
|
|
2563 (verilog-set-auto-endcomments indent-str arg))
|
|
2564 (end-of-line)
|
|
2565 (delete-horizontal-space)
|
|
2566 (if arg
|
|
2567 ()
|
|
2568 (newline))
|
|
2569 nil)
|
|
2570 (progn
|
|
2571 (end-of-line)
|
|
2572 (delete-horizontal-space)
|
|
2573 't
|
|
2574 )
|
|
2575 )
|
|
2576 )
|
|
2577 ;; see if we should line up assignments
|
|
2578 (progn
|
|
2579 (if (or (memq 'all verilog-auto-lineup)
|
|
2580 (memq 'assignments verilog-auto-lineup))
|
|
2581 (verilog-pretty-expr)
|
|
2582 )
|
|
2583 (newline)
|
|
2584 )
|
|
2585 (forward-line 1)
|
|
2586 )
|
|
2587 ;; Indent next line
|
|
2588 (if verilog-auto-indent-on-newline
|
|
2589 (verilog-indent-line))
|
|
2590 )
|
|
2591 (t
|
|
2592 (newline))
|
|
2593 )))
|
|
2594
|
|
2595 (defun electric-verilog-terminate-and-indent ()
|
|
2596 "Insert a newline and indent for the next statement."
|
|
2597 (interactive)
|
|
2598 (electric-verilog-terminate-line 1))
|
|
2599
|
|
2600 (defun electric-verilog-semi ()
|
|
2601 "Insert `;' character and reindent the line."
|
|
2602 (interactive)
|
|
2603 (insert last-command-char)
|
|
2604
|
|
2605 (if (or (verilog-in-comment-or-string-p)
|
|
2606 (verilog-in-escaped-name-p))
|
|
2607 ()
|
|
2608 (save-excursion
|
|
2609 (beginning-of-line)
|
|
2610 (verilog-forward-ws&directives)
|
|
2611 (verilog-indent-line)
|
|
2612 )
|
|
2613 (if (and verilog-auto-newline
|
|
2614 (not (verilog-parenthesis-depth)))
|
|
2615 (electric-verilog-terminate-line))))
|
|
2616
|
|
2617 (defun electric-verilog-semi-with-comment ()
|
|
2618 "Insert `;' character, reindent the line and indent for comment."
|
|
2619 (interactive)
|
|
2620 (insert "\;")
|
|
2621 (save-excursion
|
|
2622 (beginning-of-line)
|
|
2623 (verilog-indent-line))
|
|
2624 (indent-for-comment))
|
|
2625
|
|
2626 (defun electric-verilog-colon ()
|
|
2627 "Insert `:' and do all indentations except line indent on this line."
|
|
2628 (interactive)
|
|
2629 (insert last-command-char)
|
|
2630 ;; Do nothing if within string.
|
|
2631 (if (or
|
|
2632 (verilog-within-string)
|
|
2633 (not (verilog-in-case-region-p)))
|
|
2634 ()
|
|
2635 (save-excursion
|
|
2636 (let ((p (point))
|
|
2637 (lim (progn (verilog-beg-of-statement) (point))))
|
|
2638 (goto-char p)
|
|
2639 (verilog-backward-case-item lim)
|
|
2640 (verilog-indent-line)))
|
|
2641 ;; (let ((verilog-tab-always-indent nil))
|
|
2642 ;; (verilog-indent-line))
|
|
2643 ))
|
|
2644
|
|
2645 ;;(defun electric-verilog-equal ()
|
|
2646 ;; "Insert `=', and do indentation if within block."
|
|
2647 ;; (interactive)
|
|
2648 ;; (insert last-command-char)
|
|
2649 ;; Could auto line up expressions, but not yet
|
|
2650 ;; (if (eq (car (verilog-calculate-indent)) 'block)
|
|
2651 ;; (let ((verilog-tab-always-indent nil))
|
|
2652 ;; (verilog-indent-command)))
|
|
2653 ;; )
|
|
2654
|
|
2655 (defun electric-verilog-tick ()
|
|
2656 "Insert back-tick, and indent to column 0 if this is a CPP directive."
|
|
2657 (interactive)
|
|
2658 (insert last-command-char)
|
|
2659 (save-excursion
|
|
2660 (if (progn
|
|
2661 (beginning-of-line)
|
|
2662 (looking-at verilog-directive-re-1))
|
|
2663 (verilog-indent-line))))
|
|
2664
|
|
2665 (defun electric-verilog-tab ()
|
|
2666 "Function called when TAB is pressed in Verilog mode."
|
|
2667 (interactive)
|
|
2668 ;; If verilog-tab-always-indent, indent the beginning of the line.
|
|
2669 (if (or verilog-tab-always-indent
|
|
2670 (save-excursion
|
|
2671 (skip-chars-backward " \t")
|
|
2672 (bolp)))
|
|
2673 (let* ((oldpnt (point))
|
|
2674 (boi-point
|
|
2675 (save-excursion
|
|
2676 (beginning-of-line)
|
|
2677 (skip-chars-forward " \t")
|
|
2678 (verilog-indent-line)
|
|
2679 (back-to-indentation)
|
|
2680 (point))))
|
|
2681 (if (< (point) boi-point)
|
|
2682 (back-to-indentation)
|
|
2683 (cond ((not verilog-tab-to-comment))
|
|
2684 ((not (eolp))
|
|
2685 (end-of-line))
|
|
2686 (t
|
|
2687 (indent-for-comment)
|
|
2688 (when (and (eolp) (= oldpnt (point)))
|
|
2689 ; kill existing comment
|
|
2690 (beginning-of-line)
|
|
2691 (re-search-forward comment-start-skip oldpnt 'move)
|
|
2692 (goto-char (match-beginning 0))
|
|
2693 (skip-chars-backward " \t")
|
|
2694 (kill-region (point) oldpnt)
|
|
2695 ))))
|
|
2696 )
|
|
2697 (progn (insert "\t"))))
|
|
2698
|
|
2699
|
|
2700
|
|
2701 ;;
|
|
2702 ;; Interactive functions
|
|
2703 ;;
|
|
2704
|
|
2705 (defun verilog-indent-buffer ()
|
|
2706 "Indent-region the entire buffer as Verilog code.
|
|
2707 To call this from the command line, see \\[verilog-batch-indent]."
|
|
2708 (interactive)
|
|
2709 (verilog-mode)
|
|
2710 (indent-region (point-min) (point-max) nil))
|
|
2711
|
|
2712 (defun verilog-insert-block ()
|
|
2713 "Insert Verilog begin ... end; block in the code with right indentation."
|
|
2714 (interactive)
|
|
2715 (verilog-indent-line)
|
|
2716 (insert "begin")
|
|
2717 (electric-verilog-terminate-line)
|
|
2718 (save-excursion
|
|
2719 (electric-verilog-terminate-line)
|
|
2720 (insert "end")
|
|
2721 (beginning-of-line)
|
|
2722 (verilog-indent-line)))
|
|
2723
|
|
2724 (defun verilog-star-comment ()
|
|
2725 "Insert Verilog star comment at point."
|
|
2726 (interactive)
|
|
2727 (verilog-indent-line)
|
|
2728 (insert "/*")
|
|
2729 (save-excursion
|
|
2730 (newline)
|
|
2731 (insert " */"))
|
|
2732 (newline)
|
|
2733 (insert " * "))
|
|
2734
|
|
2735 (defun verilog-insert-indices (MAX)
|
|
2736 "Insert a set of indices at into the rectangle.
|
|
2737 The upper left corner is defined by the current point. Indices always
|
|
2738 begin with 0 and extend to the MAX - 1. If no prefix arg is given, the
|
|
2739 user is prompted for a value. The indices are surrounded by square brackets
|
|
2740 []. For example, the following code with the point located after the first
|
|
2741 'a' gives:
|
|
2742
|
|
2743 a = b a[ 0] = b
|
|
2744 a = b a[ 1] = b
|
|
2745 a = b a[ 2] = b
|
|
2746 a = b a[ 3] = b
|
|
2747 a = b ==> insert-indices ==> a[ 4] = b
|
|
2748 a = b a[ 5] = b
|
|
2749 a = b a[ 6] = b
|
|
2750 a = b a[ 7] = b
|
|
2751 a = b a[ 8] = b"
|
|
2752
|
|
2753 (interactive "NMAX?")
|
|
2754 (save-excursion
|
|
2755 (let ((n 0))
|
|
2756 (while (< n MAX)
|
|
2757 (save-excursion
|
|
2758 (insert (format "[%3d]" n)))
|
|
2759 (next-line 1)
|
|
2760 (setq n (1+ n))))))
|
|
2761
|
|
2762
|
|
2763 (defun verilog-generate-numbers (MAX)
|
|
2764 "Insert a set of generated numbers into a rectangle.
|
|
2765 The upper left corner is defined by point. The numbers are padded to three
|
|
2766 digits, starting with 000 and extending to (MAX - 1). If no prefix argument
|
|
2767 is supplied, then the user is prompted for the MAX number. consider the
|
|
2768 following code fragment:
|
|
2769
|
|
2770 buf buf buf buf000
|
|
2771 buf buf buf buf001
|
|
2772 buf buf buf buf002
|
|
2773 buf buf buf buf003
|
|
2774 buf buf ==> insert-indices ==> buf buf004
|
|
2775 buf buf buf buf005
|
|
2776 buf buf buf buf006
|
|
2777 buf buf buf buf007
|
|
2778 buf buf buf buf008"
|
|
2779
|
|
2780 (interactive "NMAX?")
|
|
2781 (save-excursion
|
|
2782 (let ((n 0))
|
|
2783 (while (< n MAX)
|
|
2784 (save-excursion
|
|
2785 (insert (format "%3.3d" n)))
|
|
2786 (next-line 1)
|
|
2787 (setq n (1+ n))))))
|
|
2788
|
|
2789 (defun verilog-mark-defun ()
|
|
2790 "Mark the current verilog function (or procedure).
|
|
2791 This puts the mark at the end, and point at the beginning."
|
|
2792 (interactive)
|
|
2793 (push-mark (point))
|
|
2794 (verilog-end-of-defun)
|
|
2795 (push-mark (point))
|
|
2796 (verilog-beg-of-defun)
|
|
2797 (zmacs-activate-region))
|
|
2798
|
|
2799 (defun verilog-comment-region (start end)
|
|
2800 ; checkdoc-params: (start end)
|
|
2801 "Put the region into a Verilog comment.
|
|
2802 The comments that are in this area are \"deformed\":
|
|
2803 `*)' becomes `!(*' and `}' becomes `!{'.
|
|
2804 These deformed comments are returned to normal if you use
|
|
2805 \\[verilog-uncomment-region] to undo the commenting.
|
|
2806
|
|
2807 The commented area starts with `verilog-exclude-str-start', and ends with
|
|
2808 `verilog-exclude-str-end'. But if you change these variables,
|
|
2809 \\[verilog-uncomment-region] won't recognize the comments."
|
|
2810 (interactive "r")
|
|
2811 (save-excursion
|
|
2812 ;; Insert start and endcomments
|
|
2813 (goto-char end)
|
|
2814 (if (and (save-excursion (skip-chars-forward " \t") (eolp))
|
|
2815 (not (save-excursion (skip-chars-backward " \t") (bolp))))
|
|
2816 (forward-line 1)
|
|
2817 (beginning-of-line))
|
|
2818 (insert verilog-exclude-str-end)
|
|
2819 (setq end (point))
|
|
2820 (newline)
|
|
2821 (goto-char start)
|
|
2822 (beginning-of-line)
|
|
2823 (insert verilog-exclude-str-start)
|
|
2824 (newline)
|
|
2825 ;; Replace end-comments within commented area
|
|
2826 (goto-char end)
|
|
2827 (save-excursion
|
|
2828 (while (re-search-backward "\\*/" start t)
|
|
2829 (replace-match "*-/" t t)))
|
|
2830 (save-excursion
|
|
2831 (let ((s+1 (1+ start)))
|
|
2832 (while (re-search-backward "/\\*" s+1 t)
|
|
2833 (replace-match "/-*" t t))))
|
|
2834 ))
|
|
2835
|
|
2836 (defun verilog-uncomment-region ()
|
|
2837 "Uncomment a commented area; change deformed comments back to normal.
|
|
2838 This command does nothing if the pointer is not in a commented
|
|
2839 area. See also `verilog-comment-region'."
|
|
2840 (interactive)
|
|
2841 (save-excursion
|
|
2842 (let ((start (point))
|
|
2843 (end (point)))
|
|
2844 ;; Find the boundaries of the comment
|
|
2845 (save-excursion
|
|
2846 (setq start (progn (search-backward verilog-exclude-str-start nil t)
|
|
2847 (point)))
|
|
2848 (setq end (progn (search-forward verilog-exclude-str-end nil t)
|
|
2849 (point))))
|
|
2850 ;; Check if we're really inside a comment
|
|
2851 (if (or (equal start (point)) (<= end (point)))
|
|
2852 (message "Not standing within commented area.")
|
|
2853 (progn
|
|
2854 ;; Remove endcomment
|
|
2855 (goto-char end)
|
|
2856 (beginning-of-line)
|
|
2857 (let ((pos (point)))
|
|
2858 (end-of-line)
|
|
2859 (delete-region pos (1+ (point))))
|
|
2860 ;; Change comments back to normal
|
|
2861 (save-excursion
|
|
2862 (while (re-search-backward "\\*-/" start t)
|
|
2863 (replace-match "*/" t t)))
|
|
2864 (save-excursion
|
|
2865 (while (re-search-backward "/-\\*" start t)
|
|
2866 (replace-match "/*" t t)))
|
|
2867 ;; Remove start comment
|
|
2868 (goto-char start)
|
|
2869 (beginning-of-line)
|
|
2870 (let ((pos (point)))
|
|
2871 (end-of-line)
|
|
2872 (delete-region pos (1+ (point)))))))))
|
|
2873
|
|
2874 (defun verilog-beg-of-defun ()
|
|
2875 "Move backward to the beginning of the current function or procedure."
|
|
2876 (interactive)
|
|
2877 (verilog-re-search-backward verilog-defun-re nil 'move))
|
|
2878
|
|
2879 (defun verilog-end-of-defun ()
|
|
2880 "Move forward to the end of the current function or procedure."
|
|
2881 (interactive)
|
|
2882 (verilog-re-search-forward verilog-end-defun-re nil 'move))
|
|
2883
|
|
2884 (defun verilog-get-beg-of-defun (&optional warn)
|
|
2885 (save-excursion
|
|
2886 (cond ((verilog-re-search-forward-quick verilog-defun-re nil t)
|
|
2887 (point))
|
|
2888 (t
|
|
2889 (error "%s: Can't find module beginning" (verilog-point-text))
|
|
2890 (point-max)))))
|
|
2891 (defun verilog-get-end-of-defun (&optional warn)
|
|
2892 (save-excursion
|
|
2893 (cond ((verilog-re-search-forward-quick verilog-end-defun-re nil t)
|
|
2894 (point))
|
|
2895 (t
|
|
2896 (error "%s: Can't find endmodule" (verilog-point-text))
|
|
2897 (point-max)))))
|
|
2898
|
|
2899 (defun verilog-label-be (&optional arg)
|
|
2900 "Label matching begin ... end, fork ... join and case ... endcase statements.
|
|
2901 With ARG, first kill any existing labels."
|
|
2902 (interactive)
|
|
2903 (let ((cnt 0)
|
|
2904 (oldpos (point))
|
|
2905 (b (progn
|
|
2906 (verilog-beg-of-defun)
|
|
2907 (point-marker)))
|
|
2908 (e (progn
|
|
2909 (verilog-end-of-defun)
|
|
2910 (point-marker)))
|
|
2911 )
|
|
2912 (goto-char (marker-position b))
|
|
2913 (if (> (- e b) 200)
|
|
2914 (message "Relabeling module..."))
|
|
2915 (while (and
|
|
2916 (> (marker-position e) (point))
|
|
2917 (verilog-re-search-forward
|
|
2918 (concat
|
|
2919 "\\<end\\(\\(function\\)\\|\\(task\\)\\|\\(module\\)\\|\\(primitive\\)\\|\\(interface\\)\\|\\(package\\)\\|\\(case\\)\\)?\\>"
|
|
2920 "\\|\\(`endif\\)\\|\\(`else\\)")
|
|
2921 nil 'move))
|
|
2922 (goto-char (match-beginning 0))
|
|
2923 (let ((indent-str (verilog-indent-line)))
|
|
2924 (verilog-set-auto-endcomments indent-str 't)
|
|
2925 (end-of-line)
|
|
2926 (delete-horizontal-space)
|
|
2927 )
|
|
2928 (setq cnt (1+ cnt))
|
|
2929 (if (= 9 (% cnt 10))
|
|
2930 (message "%d..." cnt))
|
|
2931 )
|
|
2932 (goto-char oldpos)
|
|
2933 (if (or
|
|
2934 (> (- e b) 200)
|
|
2935 (> cnt 20))
|
|
2936 (message "%d lines auto commented" cnt))
|
|
2937 ))
|
|
2938
|
|
2939 (defun verilog-beg-of-statement ()
|
|
2940 "Move backward to beginning of statement."
|
|
2941 (interactive)
|
|
2942 ;; Move back token by token until we see the end
|
|
2943 ;; of some ealier line.
|
|
2944 (while
|
|
2945 ;; If the current point does not begin a new
|
|
2946 ;; statement, as in the character ahead of us is a ';', or SOF
|
|
2947 ;; or the string after us unambiguosly starts a statement,
|
|
2948 ;; or the token before us unambiguously ends a statement,
|
|
2949 ;; then move back a token and test again.
|
|
2950 (not (or
|
|
2951 (bolp)
|
|
2952 (= (preceding-char) ?\;)
|
|
2953 (not (or
|
|
2954 (looking-at "\\<")
|
|
2955 (forward-word -1)))
|
|
2956 (and
|
|
2957 (looking-at verilog-extended-complete-re)
|
|
2958 (not (save-excursion
|
|
2959 (verilog-backward-token)
|
|
2960 (looking-at verilog-extended-complete-re)))
|
|
2961 )
|
|
2962 (looking-at verilog-basic-complete-re)
|
|
2963 (save-excursion
|
|
2964 (verilog-backward-token)
|
|
2965 (or
|
|
2966 (looking-at verilog-end-block-re)
|
|
2967 (looking-at verilog-preprocessor-re)))
|
|
2968 ))
|
|
2969 (verilog-backward-syntactic-ws)
|
|
2970 (verilog-backward-token))
|
|
2971 ;; Now point is where the previous line ended.
|
|
2972 (verilog-forward-syntactic-ws))
|
|
2973
|
|
2974 (defun verilog-beg-of-statement-1 ()
|
|
2975 "Move backward to beginning of statement."
|
|
2976 (interactive)
|
|
2977 (let ((pt (point)))
|
|
2978
|
|
2979 (while (and (not (looking-at verilog-complete-reg))
|
|
2980 (setq pt (point))
|
|
2981 (verilog-backward-token)
|
|
2982 (not (looking-at verilog-complete-reg))
|
|
2983 (verilog-backward-syntactic-ws)
|
|
2984 (setq pt (point))
|
|
2985 (not (bolp))
|
|
2986 (not (= (preceding-char) ?\;))))
|
|
2987 (goto-char pt)
|
|
2988 (verilog-forward-ws&directives)))
|
|
2989
|
|
2990 (defun verilog-end-of-statement ()
|
|
2991 "Move forward to end of current statement."
|
|
2992 (interactive)
|
|
2993 (let ((nest 0) pos)
|
|
2994 (or (looking-at verilog-beg-block-re)
|
|
2995 ;; Skip to end of statement
|
|
2996 (setq pos (catch 'found
|
|
2997 (while t
|
|
2998 (forward-sexp 1)
|
|
2999 (verilog-skip-forward-comment-or-string)
|
|
3000 (cond ((looking-at "[ \t]*;")
|
|
3001 (skip-chars-forward "^;")
|
|
3002 (forward-char 1)
|
|
3003 (throw 'found (point)))
|
|
3004 ((save-excursion
|
|
3005 (forward-sexp -1)
|
|
3006 (looking-at verilog-beg-block-re))
|
|
3007 (goto-char (match-beginning 0))
|
|
3008 (throw 'found nil))
|
|
3009 ((looking-at "[ \t]*)")
|
|
3010 (throw 'found (point)))
|
|
3011 ((eobp)
|
|
3012 (throw 'found (point))))))))
|
|
3013 (if (not pos)
|
|
3014 ;; Skip a whole block
|
|
3015 (catch 'found
|
|
3016 (while t
|
|
3017 (verilog-re-search-forward verilog-end-statement-re nil 'move)
|
|
3018 (setq nest (if (match-end 1)
|
|
3019 (1+ nest)
|
|
3020 (1- nest)))
|
|
3021 (cond ((eobp)
|
|
3022 (throw 'found (point)))
|
|
3023 ((= 0 nest)
|
|
3024 (throw 'found (verilog-end-of-statement))))))
|
|
3025 pos)))
|
|
3026
|
|
3027 (defun verilog-in-case-region-p ()
|
|
3028 "Return TRUE if in a case region;
|
|
3029 more specifically, point @ in the line foo : @ begin"
|
|
3030 (interactive)
|
|
3031 (save-excursion
|
|
3032 (if (and
|
|
3033 (progn (verilog-forward-syntactic-ws)
|
|
3034 (looking-at "\\<begin\\>"))
|
|
3035 (progn (verilog-backward-syntactic-ws)
|
|
3036 (= (preceding-char) ?\:)))
|
|
3037 (catch 'found
|
|
3038 (let ((nest 1))
|
|
3039 (while t
|
|
3040 (verilog-re-search-backward
|
|
3041 (concat "\\(\\<module\\>\\)\\|\\(\\<randcase\\>\\|\\<case[xz]?\\>[^:]\\)\\|"
|
|
3042 "\\(\\<endcase\\>\\)\\>")
|
|
3043 nil 'move)
|
|
3044 (cond
|
|
3045 ((match-end 3)
|
|
3046 (setq nest (1+ nest)))
|
|
3047 ((match-end 2)
|
|
3048 (if (= nest 1)
|
|
3049 (throw 'found 1))
|
|
3050 (setq nest (1- nest)))
|
|
3051 (t
|
|
3052 (throw 'found (= nest 0)))
|
|
3053 ))))
|
|
3054 nil)))
|
|
3055 (defun verilog-in-struct-region-p ()
|
|
3056 "Return TRUE if in a struct region;
|
|
3057 more specifically, in a list after a struct|union keyword"
|
|
3058 (interactive)
|
|
3059 (save-excursion
|
|
3060 (let* ((state (parse-partial-sexp (point-min) (point)))
|
|
3061 (depth (nth 0 state)))
|
|
3062 (if depth
|
|
3063 (progn (backward-up-list depth)
|
|
3064 (verilog-beg-of-statement)
|
|
3065 (looking-at "\\<typedef\\>?\\s-*\\<struct\\|union\\>")
|
|
3066 )
|
|
3067 )
|
|
3068 )
|
|
3069 )
|
|
3070 )
|
|
3071
|
|
3072 (defun verilog-in-generate-region-p ()
|
|
3073 "Return TRUE if in a generate region;
|
|
3074 more specifically, after a generate and before an endgenerate"
|
|
3075 (interactive)
|
|
3076 (let ((lim (save-excursion (verilog-beg-of-defun) (point)))
|
|
3077 (nest 1)
|
|
3078 )
|
|
3079 (save-excursion
|
|
3080 (while (and
|
|
3081 (/= nest 0)
|
|
3082 (verilog-re-search-backward "\\<\\(generate\\)\\|\\(endgenerate\\)\\>" lim 'move)
|
|
3083 (cond
|
|
3084 ((match-end 1) ; generate
|
|
3085 (setq nest (1- nest)))
|
|
3086 ((match-end 2) ; endgenerate
|
|
3087 (setq nest (1+ nest)))
|
|
3088 ))
|
|
3089 ))
|
|
3090 (= nest 0) )) ; return nest
|
|
3091
|
|
3092 (defun verilog-in-fork-region-p ()
|
|
3093 "Return true if between a fork and join."
|
|
3094 (interactive)
|
|
3095 (let ((lim (save-excursion (verilog-beg-of-defun) (point)))
|
|
3096 (nest 1)
|
|
3097 )
|
|
3098 (save-excursion
|
|
3099 (while (and
|
|
3100 (/= nest 0)
|
|
3101 (verilog-re-search-backward "\\<\\(fork\\)\\|\\(join\\(_any\\|_none\\)?\\)\\>" lim 'move)
|
|
3102 (cond
|
|
3103 ((match-end 1) ; fork
|
|
3104 (setq nest (1- nest)))
|
|
3105 ((match-end 2) ; join
|
|
3106 (setq nest (1+ nest)))
|
|
3107 ))
|
|
3108 ))
|
|
3109 (= nest 0) )) ; return nest
|
|
3110
|
|
3111 (defun verilog-backward-case-item (lim)
|
|
3112 "Skip backward to nearest enclosing case item.
|
|
3113 Limit search to point LIM."
|
|
3114 (interactive)
|
|
3115 (let ((str 'nil)
|
|
3116 (lim1
|
|
3117 (progn
|
|
3118 (save-excursion
|
|
3119 (verilog-re-search-backward verilog-endcomment-reason-re
|
|
3120 lim 'move)
|
|
3121 (point)))))
|
|
3122 ;; Try to find the real :
|
|
3123 (if (save-excursion (search-backward ":" lim1 t))
|
|
3124 (let ((colon 0)
|
|
3125 b e )
|
|
3126 (while
|
|
3127 (and
|
|
3128 (< colon 1)
|
|
3129 (verilog-re-search-backward "\\(\\[\\)\\|\\(\\]\\)\\|\\(:\\)"
|
|
3130 lim1 'move))
|
|
3131 (cond
|
|
3132 ((match-end 1) ;; [
|
|
3133 (setq colon (1+ colon))
|
|
3134 (if (>= colon 0)
|
|
3135 (error "%s: unbalanced [" (verilog-point-text))))
|
|
3136 ((match-end 2) ;; ]
|
|
3137 (setq colon (1- colon)))
|
|
3138
|
|
3139 ((match-end 3) ;; :
|
|
3140 (setq colon (1+ colon)))
|
|
3141 ))
|
|
3142 ;; Skip back to beginning of case item
|
|
3143 (skip-chars-backward "\t ")
|
|
3144 (verilog-skip-backward-comment-or-string)
|
|
3145 (setq e (point))
|
|
3146 (setq b
|
|
3147 (progn
|
|
3148 (if
|
|
3149 (verilog-re-search-backward
|
|
3150 "\\<\\(case[zx]?\\)\\>\\|;\\|\\<end\\>" nil 'move)
|
|
3151 (progn
|
|
3152 (cond
|
|
3153 ((match-end 1)
|
|
3154 (goto-char (match-end 1))
|
|
3155 (verilog-forward-ws&directives)
|
|
3156 (if (looking-at "(")
|
|
3157 (progn
|
|
3158 (forward-sexp)
|
|
3159 (verilog-forward-ws&directives)))
|
|
3160 (point))
|
|
3161 (t
|
|
3162 (goto-char (match-end 0))
|
|
3163 (verilog-forward-ws&directives)
|
|
3164 (point))
|
|
3165 ))
|
|
3166 (error "Malformed case item")
|
|
3167 )))
|
|
3168 (setq str (buffer-substring b e))
|
|
3169 (if
|
|
3170 (setq e
|
|
3171 (string-match
|
|
3172 "[ \t]*\\(\\(\n\\)\\|\\(//\\)\\|\\(/\\*\\)\\)" str))
|
|
3173 (setq str (concat (substring str 0 e) "...")))
|
|
3174 str)
|
|
3175 'nil)))
|
|
3176
|
|
3177
|
|
3178 ;;
|
|
3179 ;; Other functions
|
|
3180 ;;
|
|
3181
|
|
3182 (defun kill-existing-comment ()
|
|
3183 "Kill auto comment on this line."
|
|
3184 (save-excursion
|
|
3185 (let* (
|
|
3186 (e (progn
|
|
3187 (end-of-line)
|
|
3188 (point)))
|
|
3189 (b (progn
|
|
3190 (beginning-of-line)
|
|
3191 (search-forward "//" e t))))
|
|
3192 (if b
|
|
3193 (delete-region (- b 2) e)))))
|
|
3194
|
|
3195 (defconst verilog-directive-nest-re
|
|
3196 (concat "\\(`else\\>\\)\\|"
|
|
3197 "\\(`endif\\>\\)\\|"
|
|
3198 "\\(`if\\>\\)\\|"
|
|
3199 "\\(`ifdef\\>\\)\\|"
|
|
3200 "\\(`ifndef\\>\\)"))
|
|
3201 (defun verilog-set-auto-endcomments (indent-str kill-existing-comment)
|
|
3202 "Add ending comment with given INDENT-STR.
|
|
3203 With KILL-EXISTING-COMMENT, remove what was there before.
|
|
3204 Insert `// case: 7 ' or `// NAME ' on this line if appropriate.
|
|
3205 Insert `// case expr ' if this line ends a case block.
|
|
3206 Insert `// ifdef FOO ' if this line ends code conditional on FOO.
|
|
3207 Insert `// NAME ' if this line ends a function, task, module, primitive or interface named NAME."
|
|
3208 (save-excursion
|
|
3209 (cond
|
|
3210 (; Comment close preprocessor directives
|
|
3211 (and
|
|
3212 (looking-at "\\(`endif\\)\\|\\(`else\\)")
|
|
3213 (or kill-existing-comment
|
|
3214 (not (save-excursion
|
|
3215 (end-of-line)
|
|
3216 (search-backward "//" (verilog-get-beg-of-line) t)))))
|
|
3217 (let ((nest 1) b e
|
|
3218 m
|
|
3219 (else (if (match-end 2) "!" " "))
|
|
3220 )
|
|
3221 (end-of-line)
|
|
3222 (if kill-existing-comment
|
|
3223 (kill-existing-comment))
|
|
3224 (delete-horizontal-space)
|
|
3225 (save-excursion
|
|
3226 (backward-sexp 1)
|
|
3227 (while (and (/= nest 0)
|
|
3228 (verilog-re-search-backward verilog-directive-nest-re nil 'move))
|
|
3229 (cond
|
|
3230 ((match-end 1) ; `else
|
|
3231 (if (= nest 1)
|
|
3232 (setq else "!")))
|
|
3233 ((match-end 2) ; `endif
|
|
3234 (setq nest (1+ nest)))
|
|
3235 ((match-end 3) ; `if
|
|
3236 (setq nest (1- nest)))
|
|
3237 ((match-end 4) ; `ifdef
|
|
3238 (setq nest (1- nest)))
|
|
3239 ((match-end 5) ; `ifndef
|
|
3240 (setq nest (1- nest)))
|
|
3241 ))
|
|
3242 (if (match-end 0)
|
|
3243 (setq
|
|
3244 m (buffer-substring
|
|
3245 (match-beginning 0)
|
|
3246 (match-end 0))
|
|
3247 b (progn
|
|
3248 (skip-chars-forward "^ \t")
|
|
3249 (verilog-forward-syntactic-ws)
|
|
3250 (point))
|
|
3251 e (progn
|
|
3252 (skip-chars-forward "a-zA-Z0-9_")
|
|
3253 (point)
|
|
3254 ))))
|
|
3255 (if b
|
|
3256 (if (> (count-lines (point) b) verilog-minimum-comment-distance)
|
|
3257 (insert (concat " // " else m " " (buffer-substring b e))))
|
|
3258 (progn
|
|
3259 (insert " // unmatched `else or `endif")
|
|
3260 (ding 't))
|
|
3261 )))
|
|
3262
|
|
3263 (; Comment close case/class/function/task/module and named block
|
|
3264 (and (looking-at "\\<end")
|
|
3265 (or kill-existing-comment
|
|
3266 (not (save-excursion
|
|
3267 (end-of-line)
|
|
3268 (search-backward "//" (verilog-get-beg-of-line) t)))))
|
|
3269 (let ((type (car indent-str)))
|
|
3270 (unless (eq type 'declaration)
|
|
3271 (unless (looking-at (concat "\\(" verilog-end-block-ordered-re "\\)[ \t]*:")) ;; ignore named ends
|
|
3272 (if (looking-at verilog-end-block-ordered-re)
|
|
3273 (cond
|
|
3274 (;- This is a case block; search back for the start of this case
|
|
3275 (match-end 1) ;; of verilog-end-block-ordered-re
|
|
3276
|
|
3277 (let ((err 't)
|
|
3278 (str "UNMATCHED!!"))
|
|
3279 (save-excursion
|
|
3280 (verilog-leap-to-head)
|
|
3281 (cond
|
|
3282 ((looking-at "\\<randcase\\>")
|
|
3283 (setq str "randcase")
|
|
3284 (setq err nil)
|
|
3285 )
|
|
3286 ((match-end 0)
|
|
3287 (goto-char (match-end 1))
|
|
3288 (if nil
|
|
3289 (let (s f)
|
|
3290 (setq s (match-beginning 1))
|
|
3291 (setq f (progn (end-of-line)
|
|
3292 (point)))
|
|
3293 (setq str (buffer-substring s f)))
|
|
3294 (setq err nil))
|
|
3295 (setq str (concat (buffer-substring (match-beginning 1) (match-end 1))
|
|
3296 " "
|
|
3297 (verilog-get-expr))))))
|
|
3298 (end-of-line)
|
|
3299 (if kill-existing-comment
|
|
3300 (kill-existing-comment))
|
|
3301 (delete-horizontal-space)
|
|
3302 (insert (concat " // " str ))
|
|
3303 (if err (ding 't))
|
|
3304 ))
|
|
3305
|
|
3306 (;- This is a begin..end block
|
|
3307 (match-end 2) ;; of verilog-end-block-ordered-re
|
|
3308 (let ((str " // UNMATCHED !!")
|
|
3309 (err 't)
|
|
3310 (here (point))
|
|
3311 there
|
|
3312 cntx
|
|
3313 )
|
|
3314 (save-excursion
|
|
3315 (verilog-leap-to-head)
|
|
3316 (setq there (point))
|
|
3317 (if (not (match-end 0))
|
|
3318 (progn
|
|
3319 (goto-char here)
|
|
3320 (end-of-line)
|
|
3321 (if kill-existing-comment
|
|
3322 (kill-existing-comment))
|
|
3323 (delete-horizontal-space)
|
|
3324 (insert str)
|
|
3325 (ding 't)
|
|
3326 )
|
|
3327 (let ((lim
|
|
3328 (save-excursion (verilog-beg-of-defun) (point)))
|
|
3329 (here (point))
|
|
3330 )
|
|
3331 (cond
|
|
3332 (;-- handle named block differently
|
|
3333 (looking-at verilog-named-block-re)
|
|
3334 (search-forward ":")
|
|
3335 (setq there (point))
|
|
3336 (setq str (verilog-get-expr))
|
|
3337 (setq err nil)
|
|
3338 (setq str (concat " // block: " str )))
|
|
3339
|
|
3340 ((verilog-in-case-region-p) ;-- handle case item differently
|
|
3341 (goto-char here)
|
|
3342 (setq str (verilog-backward-case-item lim))
|
|
3343 (setq there (point))
|
|
3344 (setq err nil)
|
|
3345 (setq str (concat " // case: " str )))
|
|
3346
|
|
3347 (;- try to find "reason" for this begin
|
|
3348 (cond
|
|
3349 (;
|
|
3350 (eq here (progn
|
|
3351 (verilog-backward-token)
|
|
3352 (verilog-beg-of-statement-1)
|
|
3353 (point)))
|
|
3354 (setq err nil)
|
|
3355 (setq str ""))
|
|
3356 ((looking-at verilog-endcomment-reason-re)
|
|
3357 (setq there (match-end 0))
|
|
3358 (setq cntx (concat
|
|
3359 (buffer-substring (match-beginning 0) (match-end 0)) " "))
|
|
3360 (cond
|
|
3361 (;- begin
|
|
3362 (match-end 2)
|
|
3363 (setq err nil)
|
|
3364 (save-excursion
|
|
3365 (if (and (verilog-continued-line)
|
|
3366 (looking-at "\\<repeat\\>\\|\\<wait\\>\\|\\<always\\>"))
|
|
3367 (progn
|
|
3368 (goto-char (match-end 0))
|
|
3369 (setq there (point))
|
|
3370 (setq str
|
|
3371 (concat " // "
|
|
3372 (buffer-substring (match-beginning 0) (match-end 0)) " "
|
|
3373 (verilog-get-expr))))
|
|
3374 (setq str ""))))
|
|
3375
|
|
3376 (;- else
|
|
3377 (match-end 4)
|
|
3378 (let ((nest 0)
|
|
3379 ( reg "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)\\|\\(\\<if\\>\\)")
|
|
3380 )
|
|
3381 (catch 'skip
|
|
3382 (while (verilog-re-search-backward reg nil 'move)
|
|
3383 (cond
|
|
3384 ((match-end 1) ; begin
|
|
3385 (setq nest (1- nest)))
|
|
3386 ((match-end 2) ; end
|
|
3387 (setq nest (1+ nest)))
|
|
3388 ((match-end 3)
|
|
3389 (if (= 0 nest)
|
|
3390 (progn
|
|
3391 (goto-char (match-end 0))
|
|
3392 (setq there (point))
|
|
3393 (setq err nil)
|
|
3394 (setq str (verilog-get-expr))
|
|
3395 (setq str (concat " // else: !if" str ))
|
|
3396 (throw 'skip 1))
|
|
3397 )))
|
|
3398 ))))
|
|
3399
|
|
3400 (;- end else
|
|
3401 (match-end 5)
|
|
3402 (goto-char there)
|
|
3403 (let ((nest 0)
|
|
3404 ( reg "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)\\|\\(\\<if\\>\\)")
|
|
3405 )
|
|
3406 (catch 'skip
|
|
3407 (while (verilog-re-search-backward reg nil 'move)
|
|
3408 (cond
|
|
3409 ((match-end 1) ; begin
|
|
3410 (setq nest (1- nest)))
|
|
3411 ((match-end 2) ; end
|
|
3412 (setq nest (1+ nest)))
|
|
3413 ((match-end 3)
|
|
3414 (if (= 0 nest)
|
|
3415 (progn
|
|
3416 (goto-char (match-end 0))
|
|
3417 (setq there (point))
|
|
3418 (setq err nil)
|
|
3419 (setq str (verilog-get-expr))
|
|
3420 (setq str (concat " // else: !if" str ))
|
|
3421 (throw 'skip 1))
|
|
3422 )))
|
|
3423 ))))
|
|
3424
|
|
3425 (;- task/function/initial et cetera
|
|
3426 t
|
|
3427 (match-end 0)
|
|
3428 (goto-char (match-end 0))
|
|
3429 (setq there (point))
|
|
3430 (setq err nil)
|
|
3431 (setq str (verilog-get-expr))
|
|
3432 (setq str (concat " // " cntx str )))
|
|
3433
|
|
3434 (;-- otherwise...
|
|
3435 (setq str " // auto-endcomment confused "))
|
|
3436 ))
|
|
3437
|
|
3438 ((and
|
|
3439 (verilog-in-case-region-p) ;-- handle case item differently
|
|
3440 (progn
|
|
3441 (setq there (point))
|
|
3442 (goto-char here)
|
|
3443 (setq str (verilog-backward-case-item lim))))
|
|
3444 (setq err nil)
|
|
3445 (setq str (concat " // case: " str )))
|
|
3446
|
|
3447 ((verilog-in-fork-region-p)
|
|
3448 (setq err nil)
|
|
3449 (setq str " // fork branch" ))
|
|
3450
|
|
3451 ((looking-at "\\<end\\>")
|
|
3452 ;; HERE
|
|
3453 (forward-word 1)
|
|
3454 (verilog-forward-syntactic-ws)
|
|
3455 (setq err nil)
|
|
3456 (setq str (verilog-get-expr))
|
|
3457 (setq str (concat " // " cntx str )))
|
|
3458
|
|
3459 ))))
|
|
3460 (goto-char here)
|
|
3461 (end-of-line)
|
|
3462 (if kill-existing-comment
|
|
3463 (kill-existing-comment))
|
|
3464 (delete-horizontal-space)
|
|
3465 (if (or err
|
|
3466 (> (count-lines here there) verilog-minimum-comment-distance))
|
|
3467 (insert str))
|
|
3468 (if err (ding 't))
|
|
3469 ))))
|
|
3470 (;- this is endclass, which can be nested
|
|
3471 (match-end 11) ;; of verilog-end-block-ordered-re
|
|
3472 ;;(goto-char there)
|
|
3473 (let ((nest 0)
|
|
3474 ( reg "\\<\\(class\\)\\|\\(endclass\\)\\|\\(package\\|primitive\\|\\(macro\\)?module\\)\\>")
|
|
3475 string
|
|
3476 )
|
|
3477 (save-excursion
|
|
3478 (catch 'skip
|
|
3479 (while (verilog-re-search-backward reg nil 'move)
|
|
3480 (cond
|
|
3481 ((match-end 3) ; endclass
|
|
3482 (ding 't)
|
|
3483 (setq string "unmatched endclass")
|
|
3484 (throw 'skip 1))
|
|
3485
|
|
3486 ((match-end 2) ; endclass
|
|
3487 (setq nest (1+ nest)))
|
|
3488
|
|
3489 ((match-end 1) ; class
|
|
3490 (setq nest (1- nest))
|
|
3491 (if (< nest 0)
|
|
3492 (progn
|
|
3493 (goto-char (match-end 0))
|
|
3494 (let (b e)
|
|
3495 (setq b (progn
|
|
3496 (skip-chars-forward "^ \t")
|
|
3497 (verilog-forward-ws&directives)
|
|
3498 (point))
|
|
3499 e (progn
|
|
3500 (skip-chars-forward "a-zA-Z0-9_")
|
|
3501 (point)))
|
|
3502 (setq string (buffer-substring b e)))
|
|
3503 (throw 'skip 1))))
|
|
3504 ))))
|
|
3505 (end-of-line)
|
|
3506 (insert (concat " // " string )))
|
|
3507 )
|
|
3508
|
|
3509 (;- this is end{function,generate,task,module,primitive,table,generate}
|
|
3510 ;- which can not be nested.
|
|
3511 t
|
|
3512 (let (string reg (width nil))
|
|
3513 (end-of-line)
|
|
3514 (if kill-existing-comment
|
|
3515 (save-match-data
|
|
3516 (kill-existing-comment)))
|
|
3517 (delete-horizontal-space)
|
|
3518 (backward-sexp)
|
|
3519 (cond
|
|
3520 ((match-end 5) ;; of verilog-end-block-ordered-re
|
|
3521 (setq reg "\\(\\<function\\>\\)\\|\\(\\<\\(endfunction\\|task\\|\\(macro\\)?module\\|primitive\\)\\>\\)")
|
|
3522 (setq width "\\(\\s-*\\(\\[[^]]*\\]\\)\\|\\(real\\(time\\)?\\)\\|\\(integer\\)\\|\\(time\\)\\)?")
|
|
3523 )
|
|
3524 ((match-end 6) ;; of verilog-end-block-ordered-re
|
|
3525 (setq reg "\\(\\<task\\>\\)\\|\\(\\<\\(endtask\\|function\\|\\(macro\\)?module\\|primitive\\)\\>\\)"))
|
|
3526 ((match-end 7) ;; of verilog-end-block-ordered-re
|
|
3527 (setq reg "\\(\\<\\(macro\\)?module\\>\\)\\|\\<endmodule\\>"))
|
|
3528 ((match-end 8) ;; of verilog-end-block-ordered-re
|
|
3529 (setq reg "\\(\\<primitive\\>\\)\\|\\(\\<\\(endprimitive\\|package\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
|
|
3530 ((match-end 9) ;; of verilog-end-block-ordered-re
|
|
3531 (setq reg "\\(\\<interface\\>\\)\\|\\(\\<\\(endinterface\\|package\\|primitive\\|\\(macro\\)?module\\)\\>\\)"))
|
|
3532 ((match-end 10) ;; of verilog-end-block-ordered-re
|
|
3533 (setq reg "\\(\\<package\\>\\)\\|\\(\\<\\(endpackage\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
|
|
3534 ((match-end 11) ;; of verilog-end-block-ordered-re
|
|
3535 (setq reg "\\(\\<class\\>\\)\\|\\(\\<\\(endclass\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
|
|
3536 ((match-end 12) ;; of verilog-end-block-ordered-re
|
|
3537 (setq reg "\\(\\<covergroup\\>\\)\\|\\(\\<\\(endcovergroup\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
|
|
3538 ((match-end 13) ;; of verilog-end-block-ordered-re
|
|
3539 (setq reg "\\(\\<program\\>\\)\\|\\(\\<\\(endprogram\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
|
|
3540 ((match-end 14) ;; of verilog-end-block-ordered-re
|
|
3541 (setq reg "\\(\\<\\(rand\\)?sequence\\>\\)\\|\\(\\<\\(endsequence\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
|
|
3542 ((match-end 15) ;; of verilog-end-block-ordered-re
|
|
3543 (setq reg "\\(\\<clocking\\>\\)\\|\\<endclocking\\>"))
|
|
3544
|
|
3545 (t (error "Problem in verilog-set-auto-endcomments"))
|
|
3546 )
|
|
3547 (let (b e)
|
|
3548 (save-excursion
|
|
3549 (verilog-re-search-backward reg nil 'move)
|
|
3550 (cond
|
|
3551 ((match-end 1)
|
|
3552 (setq b (progn
|
|
3553 (skip-chars-forward "^ \t")
|
|
3554 (verilog-forward-ws&directives)
|
|
3555 (if (and width (looking-at width))
|
|
3556 (progn
|
|
3557 (goto-char (match-end 0))
|
|
3558 (verilog-forward-ws&directives)
|
|
3559 ))
|
|
3560 (point))
|
|
3561 e (progn
|
|
3562 (skip-chars-forward "a-zA-Z0-9_")
|
|
3563 (point)))
|
|
3564 (setq string (buffer-substring b e)))
|
|
3565 (t
|
|
3566 (ding 't)
|
|
3567 (setq string "unmatched end(function|task|module|primitive|interface|package|class|clocking)")))))
|
|
3568 (end-of-line)
|
|
3569 (insert (concat " // " string )))
|
|
3570 ))))))))))
|
|
3571
|
|
3572 (defun verilog-get-expr()
|
|
3573 "Grab expression at point, e.g, case ( a | b & (c ^d))"
|
|
3574 (let* ((b (progn
|
|
3575 (verilog-forward-syntactic-ws)
|
|
3576 (skip-chars-forward " \t")
|
|
3577 (point)))
|
|
3578 (e (let ((par 1))
|
|
3579 (cond
|
|
3580 ((looking-at "@")
|
|
3581 (forward-char 1)
|
|
3582 (verilog-forward-syntactic-ws)
|
|
3583 (if (looking-at "(")
|
|
3584 (progn
|
|
3585 (forward-char 1)
|
|
3586 (while (and (/= par 0)
|
|
3587 (verilog-re-search-forward "\\((\\)\\|\\()\\)" nil 'move))
|
|
3588 (cond
|
|
3589 ((match-end 1)
|
|
3590 (setq par (1+ par)))
|
|
3591 ((match-end 2)
|
|
3592 (setq par (1- par)))))))
|
|
3593 (point))
|
|
3594 ((looking-at "(")
|
|
3595 (forward-char 1)
|
|
3596 (while (and (/= par 0)
|
|
3597 (verilog-re-search-forward "\\((\\)\\|\\()\\)" nil 'move))
|
|
3598 (cond
|
|
3599 ((match-end 1)
|
|
3600 (setq par (1+ par)))
|
|
3601 ((match-end 2)
|
|
3602 (setq par (1- par)))))
|
|
3603 (point))
|
|
3604 ((looking-at "\\[")
|
|
3605 (forward-char 1)
|
|
3606 (while (and (/= par 0)
|
|
3607 (verilog-re-search-forward "\\(\\[\\)\\|\\(\\]\\)" nil 'move))
|
|
3608 (cond
|
|
3609 ((match-end 1)
|
|
3610 (setq par (1+ par)))
|
|
3611 ((match-end 2)
|
|
3612 (setq par (1- par)))))
|
|
3613 (verilog-forward-syntactic-ws)
|
|
3614 (skip-chars-forward "^ \t\n\f")
|
|
3615 (point))
|
|
3616 ((looking-at "/[/\\*]")
|
|
3617 b)
|
|
3618 ('t
|
|
3619 (skip-chars-forward "^: \t\n\f")
|
|
3620 (point)
|
|
3621 ))))
|
|
3622 (str (buffer-substring b e)))
|
|
3623 (if (setq e (string-match "[ \t]*\\(\\(\n\\)\\|\\(//\\)\\|\\(/\\*\\)\\)" str))
|
|
3624 (setq str (concat (substring str 0 e) "...")))
|
|
3625 str))
|
|
3626
|
|
3627 (defun verilog-expand-vector ()
|
|
3628 "Take a signal vector on the current line and expand it to multiple lines.
|
|
3629 Useful for creating tri's and other expanded fields."
|
|
3630 (interactive)
|
|
3631 (verilog-expand-vector-internal "[" "]"))
|
|
3632
|
|
3633 (defun verilog-expand-vector-internal (bra ket)
|
|
3634 "Given BRA, the start brace and KET, the end brace, expand one line into many lines."
|
|
3635 (save-excursion
|
|
3636 (forward-line 0)
|
|
3637 (let ((signal-string (buffer-substring (point)
|
|
3638 (progn
|
|
3639 (end-of-line) (point)))))
|
|
3640 (if (string-match (concat "\\(.*\\)"
|
|
3641 (regexp-quote bra)
|
|
3642 "\\([0-9]*\\)\\(:[0-9]*\\|\\)\\(::[0-9---]*\\|\\)"
|
|
3643 (regexp-quote ket)
|
|
3644 "\\(.*\\)$") signal-string)
|
|
3645 (let* ((sig-head (match-string 1 signal-string))
|
|
3646 (vec-start (string-to-int (match-string 2 signal-string)))
|
|
3647 (vec-end (if (= (match-beginning 3) (match-end 3))
|
|
3648 vec-start
|
|
3649 (string-to-int (substring signal-string (1+ (match-beginning 3)) (match-end 3)))))
|
|
3650 (vec-range (if (= (match-beginning 4) (match-end 4))
|
|
3651 1
|
|
3652 (string-to-int (substring signal-string (+ 2 (match-beginning 4)) (match-end 4)))))
|
|
3653 (sig-tail (match-string 5 signal-string))
|
|
3654 vec)
|
|
3655 ;; Decode vectors
|
|
3656 (setq vec nil)
|
|
3657 (if (< vec-range 0)
|
|
3658 (let ((tmp vec-start))
|
|
3659 (setq vec-start vec-end
|
|
3660 vec-end tmp
|
|
3661 vec-range (- vec-range))))
|
|
3662 (if (< vec-end vec-start)
|
|
3663 (while (<= vec-end vec-start)
|
|
3664 (setq vec (append vec (list vec-start)))
|
|
3665 (setq vec-start (- vec-start vec-range)))
|
|
3666 (while (<= vec-start vec-end)
|
|
3667 (setq vec (append vec (list vec-start)))
|
|
3668 (setq vec-start (+ vec-start vec-range))))
|
|
3669 ;;
|
|
3670 ;; Delete current line
|
|
3671 (delete-region (point) (progn (forward-line 0) (point)))
|
|
3672 ;;
|
|
3673 ;; Expand vector
|
|
3674 (while vec
|
|
3675 (insert (concat sig-head bra (int-to-string (car vec)) ket sig-tail "\n"))
|
|
3676 (setq vec (cdr vec)))
|
|
3677 (delete-char -1)
|
|
3678 ;;
|
|
3679 )))))
|
|
3680
|
|
3681 (defun verilog-strip-comments ()
|
|
3682 "Strip all comments from the verilog code."
|
|
3683 (interactive)
|
|
3684 (goto-char (point-min))
|
|
3685 (while (re-search-forward "//" nil t)
|
|
3686 (if (verilog-within-string)
|
|
3687 (re-search-forward "\"" nil t)
|
|
3688 (if (verilog-in-star-comment-p)
|
|
3689 (re-search-forward "\*/" nil t)
|
|
3690 (let ((bpt (- (point) 2)))
|
|
3691 (end-of-line)
|
|
3692 (delete-region bpt (point))))))
|
|
3693 ;;
|
|
3694 (goto-char (point-min))
|
|
3695 (while (re-search-forward "/\\*" nil t)
|
|
3696 (if (verilog-within-string)
|
|
3697 (re-search-forward "\"" nil t)
|
|
3698 (let ((bpt (- (point) 2)))
|
|
3699 (re-search-forward "\\*/")
|
|
3700 (delete-region bpt (point))))))
|
|
3701
|
|
3702 (defun verilog-one-line ()
|
|
3703 "Convert structural verilog instances to occupy one line."
|
|
3704 (interactive)
|
|
3705 (goto-char (point-min))
|
|
3706 (while (re-search-forward "\\([^;]\\)[ \t]*\n[ \t]*" nil t)
|
|
3707 (replace-match "\\1 " nil nil)))
|
|
3708
|
|
3709 (defun verilog-linter-name ()
|
|
3710 "Return name of linter, either surelint or verilint."
|
|
3711 (let ((compile-word1 (verilog-string-replace-matches "\\s .*$" "" nil nil
|
|
3712 compile-command))
|
|
3713 (lint-word1 (verilog-string-replace-matches "\\s .*$" "" nil nil
|
|
3714 verilog-linter)))
|
|
3715 (cond ((equal compile-word1 "surelint") `surelint)
|
|
3716 ((equal compile-word1 "verilint") `verilint)
|
|
3717 ((equal lint-word1 "surelint") `surelint)
|
|
3718 ((equal lint-word1 "verilint") `verilint)
|
|
3719 (t `surelint)))) ;; back compatibility
|
|
3720
|
|
3721 (defun verilog-lint-off ()
|
|
3722 "Convert a Verilog linter warning line into a disable statement.
|
|
3723 For example:
|
|
3724 pci_bfm_null.v, line 46: Unused input: pci_rst_
|
|
3725 becomes a comment for the appropriate tool.
|
|
3726
|
|
3727 The first word of the `compile-command' or `verilog-linter'
|
|
3728 variables are used to determine which product is being used.
|
|
3729
|
|
3730 See \\[verilog-surelint-off] and \\[verilog-verilint-off]."
|
|
3731 (interactive)
|
|
3732 (let ((linter (verilog-linter-name)))
|
|
3733 (cond ((equal linter `surelint)
|
|
3734 (verilog-surelint-off))
|
|
3735 ((equal linter `verilint)
|
|
3736 (verilog-verilint-off))
|
|
3737 (t (error "Linter name not set")))))
|
|
3738
|
|
3739 (defun verilog-surelint-off ()
|
|
3740 "Convert a SureLint warning line into a disable statement.
|
|
3741 Run from Verilog source window; assumes there is a *compile* buffer
|
|
3742 with point set appropriately.
|
|
3743
|
|
3744 For example:
|
|
3745 WARNING [STD-UDDONX]: xx.v, line 8: output out is never assigned.
|
|
3746 becomes:
|
|
3747 // surefire lint_line_off UDDONX"
|
|
3748 (interactive)
|
|
3749 (save-excursion
|
|
3750 (switch-to-buffer compilation-last-buffer)
|
|
3751 (beginning-of-line)
|
|
3752 (when
|
|
3753 (looking-at "\\(INFO\\|WARNING\\|ERROR\\) \\[[^-]+-\\([^]]+\\)\\]: \\([^,]+\\), line \\([0-9]+\\): \\(.*\\)$")
|
|
3754 (let* ((code (match-string 2))
|
|
3755 (file (match-string 3))
|
|
3756 (line (match-string 4))
|
|
3757 (buffer (get-file-buffer file))
|
|
3758 dir filename)
|
|
3759 (unless buffer
|
|
3760 (progn
|
|
3761 (setq buffer
|
|
3762 (and (file-exists-p file)
|
|
3763 (find-file-noselect file)))
|
|
3764 (or buffer
|
|
3765 (let* ((pop-up-windows t))
|
|
3766 (let ((name (expand-file-name
|
|
3767 (read-file-name
|
|
3768 (format "Find this error in: (default %s) "
|
|
3769 file)
|
|
3770 dir file t))))
|
|
3771 (if (file-directory-p name)
|
|
3772 (setq name (expand-file-name filename name)))
|
|
3773 (setq buffer
|
|
3774 (and (file-exists-p name)
|
|
3775 (find-file-noselect name))))))))
|
|
3776 (switch-to-buffer buffer)
|
|
3777 (goto-line (string-to-number line))
|
|
3778 (end-of-line)
|
|
3779 (catch 'already
|
|
3780 (cond
|
|
3781 ((verilog-in-slash-comment-p)
|
|
3782 (re-search-backward "//")
|
|
3783 (cond
|
|
3784 ((looking-at "// surefire lint_off_line ")
|
|
3785 (goto-char (match-end 0))
|
|
3786 (let ((lim (save-excursion (end-of-line) (point))))
|
|
3787 (if (re-search-forward code lim 'move)
|
|
3788 (throw 'already t)
|
|
3789 (insert-string (concat " " code)))))
|
|
3790 (t
|
|
3791 )))
|
|
3792 ((verilog-in-star-comment-p)
|
|
3793 (re-search-backward "/\*")
|
|
3794 (insert-string (format " // surefire lint_off_line %6s" code ))
|
|
3795 )
|
|
3796 (t
|
|
3797 (insert-string (format " // surefire lint_off_line %6s" code ))
|
|
3798 )))))))
|
|
3799
|
|
3800 (defun verilog-verilint-off ()
|
|
3801 "Convert a Verilint warning line into a disable statement.
|
|
3802
|
|
3803 For example:
|
|
3804 (W240) pci_bfm_null.v, line 46: Unused input: pci_rst_
|
|
3805 becomes:
|
|
3806 //Verilint 240 off // WARNING: Unused input"
|
|
3807 (interactive)
|
|
3808 (save-excursion
|
|
3809 (beginning-of-line)
|
|
3810 (when (looking-at "\\(.*\\)([WE]\\([0-9A-Z]+\\)).*,\\s +line\\s +[0-9]+:\\s +\\([^:\n]+\\):?.*$")
|
|
3811 (replace-match (format
|
|
3812 ;; %3s makes numbers 1-999 line up nicely
|
|
3813 "\\1//Verilint %3s off // WARNING: \\3"
|
|
3814 (match-string 2)))
|
|
3815 (beginning-of-line)
|
|
3816 (verilog-indent-line))))
|
|
3817
|
|
3818 (defun verilog-auto-save-compile ()
|
|
3819 "Update automatics with \\[verilog-auto], save the buffer, and compile."
|
|
3820 (interactive)
|
|
3821 (verilog-auto) ; Always do it for safety
|
|
3822 (save-buffer)
|
|
3823 (compile compile-command))
|
|
3824
|
|
3825
|
|
3826
|
|
3827 ;;
|
|
3828 ;; Batch
|
|
3829 ;;
|
|
3830
|
|
3831 (defmacro verilog-batch-error-wrapper (&rest body)
|
|
3832 "Execute BODY and add error prefix to any errors found.
|
|
3833 This lets programs calling batch mode to easily extract error messages."
|
|
3834 (` (condition-case err
|
|
3835 (progn (,@ body))
|
|
3836 (error
|
|
3837 (error "%%Error: %s%s" (error-message-string err)
|
|
3838 (if (featurep 'xemacs) "\n" "")))))) ;; xemacs forgets to add a newline
|
|
3839
|
|
3840 (defun verilog-batch-execute-func (funref)
|
|
3841 "Internal processing of a batch command, running FUNREF on all command arguments."
|
|
3842 (verilog-batch-error-wrapper
|
|
3843 ;; General globals needed
|
|
3844 (setq make-backup-files nil)
|
|
3845 (setq-default make-backup-files nil)
|
|
3846 (setq enable-local-variables t)
|
|
3847 (setq enable-local-eval t)
|
|
3848 ;; Make sure any sub-files we read get proper mode
|
|
3849 (setq default-major-mode `verilog-mode)
|
|
3850 ;; Ditto files already read in
|
|
3851 (mapcar '(lambda (buf)
|
|
3852 (when (buffer-file-name buf)
|
|
3853 (save-excursion
|
|
3854 (set-buffer buf)
|
|
3855 (verilog-mode))))
|
|
3856 (buffer-list))
|
|
3857 ;; Process the files
|
|
3858 (mapcar '(lambda (buf)
|
|
3859 (when (buffer-file-name buf)
|
|
3860 (save-excursion
|
|
3861 (if (not (file-exists-p (buffer-file-name buf)))
|
|
3862 (error (concat "File not found: " (buffer-file-name buf))))
|
|
3863 (message (concat "Processing " (buffer-file-name buf)))
|
|
3864 (set-buffer buf)
|
|
3865 (funcall funref)
|
|
3866 (save-buffer))))
|
|
3867 (buffer-list))))
|
|
3868
|
|
3869 (defun verilog-batch-auto ()
|
|
3870 "For use with --batch, perform automatic expansions as a stand-alone tool.
|
|
3871 This sets up the appropriate Verilog-Mode environment, updates automatics
|
|
3872 with \\[verilog-auto] on all command-line files, and saves the buffers.
|
|
3873 For proper results, multiple filenames need to be passed on the command
|
|
3874 line in bottom-up order."
|
|
3875 (unless noninteractive
|
|
3876 (error "Use verilog-batch-auto only with --batch")) ;; Otherwise we'd mess up buffer modes
|
|
3877 (verilog-batch-execute-func `verilog-auto))
|
|
3878
|
|
3879 (defun verilog-batch-delete-auto ()
|
|
3880 "For use with --batch, perform automatic deletion as a stand-alone tool.
|
|
3881 This sets up the appropriate Verilog-Mode environment, deletes automatics
|
|
3882 with \\[verilog-delete-auto] on all command-line files, and saves the buffers."
|
|
3883 (unless noninteractive
|
|
3884 (error "Use verilog-batch-delete-auto only with --batch")) ;; Otherwise we'd mess up buffer modes
|
|
3885 (verilog-batch-execute-func `verilog-delete-auto))
|
|
3886
|
|
3887 (defun verilog-batch-inject-auto ()
|
|
3888 "For use with --batch, perform automatic injection as a stand-alone tool.
|
|
3889 This sets up the appropriate Verilog-Mode environment, injects new automatics
|
|
3890 with \\[verilog-inject-auto] on all command-line files, and saves the buffers.
|
|
3891 For proper results, multiple filenames need to be passed on the command
|
|
3892 line in bottom-up order."
|
|
3893 (unless noninteractive
|
|
3894 (error "Use verilog-batch-inject-auto only with --batch")) ;; Otherwise we'd mess up buffer modes
|
|
3895 (verilog-batch-execute-func `verilog-inject-auto))
|
|
3896
|
|
3897 (defun verilog-batch-indent ()
|
|
3898 "For use with --batch, reindent an a entire file as a stand-alone tool.
|
|
3899 This sets up the appropriate Verilog-Mode environment, calls
|
|
3900 \\[verilog-indent-buffer] on all command-line files, and saves the buffers."
|
|
3901 (unless noninteractive
|
|
3902 (error "Use verilog-batch-indent only with --batch")) ;; Otherwise we'd mess up buffer modes
|
|
3903 (verilog-batch-execute-func `verilog-indent-buffer))
|
|
3904
|
|
3905
|
|
3906 ;;
|
|
3907 ;; Indentation
|
|
3908 ;;
|
|
3909 (defconst verilog-indent-alist
|
|
3910 '((block . (+ ind verilog-indent-level))
|
|
3911 (case . (+ ind verilog-case-indent))
|
|
3912 (cparenexp . (+ ind verilog-indent-level))
|
|
3913 (cexp . (+ ind verilog-cexp-indent))
|
|
3914 (defun . verilog-indent-level-module)
|
|
3915 (declaration . verilog-indent-level-declaration)
|
|
3916 (directive . (verilog-calculate-indent-directive))
|
|
3917 (tf . verilog-indent-level)
|
|
3918 (behavioral . (+ verilog-indent-level-behavioral verilog-indent-level-module))
|
|
3919 (statement . ind)
|
|
3920 (cpp . 0)
|
|
3921 (comment . (verilog-comment-indent))
|
|
3922 (unknown . 3)
|
|
3923 (string . 0)))
|
|
3924
|
|
3925 (defun verilog-continued-line-1 (lim)
|
|
3926 "Return true if this is a continued line.
|
|
3927 Set point to where line starts. Limit search to point LIM."
|
|
3928 (let ((continued 't))
|
|
3929 (if (eq 0 (forward-line -1))
|
|
3930 (progn
|
|
3931 (end-of-line)
|
|
3932 (verilog-backward-ws&directives lim)
|
|
3933 (if (bobp)
|
|
3934 (setq continued nil)
|
|
3935 (setq continued (verilog-backward-token))))
|
|
3936 (setq continued nil))
|
|
3937 continued))
|
|
3938
|
|
3939 (defun verilog-calculate-indent ()
|
|
3940 "Calculate the indent of the current Verilog line.
|
|
3941 Examine previous lines. Once a line is found that is definitive as to the
|
|
3942 type of the current line, return that lines' indent level and its
|
|
3943 type. Return a list of two elements: (INDENT-TYPE INDENT-LEVEL)."
|
|
3944 (save-excursion
|
|
3945 (let* ((starting_position (point))
|
|
3946 (par 0)
|
|
3947 (begin (looking-at "[ \t]*begin\\>"))
|
|
3948 (lim (save-excursion (verilog-re-search-backward "\\(\\<begin\\>\\)\\|\\(\\<module\\>\\)" nil t)))
|
|
3949 (type (catch 'nesting
|
|
3950 ;; Keep working backwards until we can figure out
|
|
3951 ;; what type of statement this is.
|
|
3952 ;; Basically we need to figure out
|
|
3953 ;; 1) if this is a continuation of the previous line;
|
|
3954 ;; 2) are we in a block scope (begin..end)
|
|
3955
|
|
3956 ;; if we are in a comment, done.
|
|
3957 (if (verilog-in-star-comment-p)
|
|
3958 (throw 'nesting 'comment))
|
|
3959
|
|
3960 ;; if we have a directive, done.
|
|
3961 (if (save-excursion (beginning-of-line) (looking-at verilog-directive-re-1))
|
|
3962 (throw 'nesting 'directive))
|
|
3963
|
|
3964 ;; unless we are in the newfangled coverpoint or constraint blocks
|
|
3965 ;; if we are in a parenthesized list, and the user likes to indent these, return.
|
|
3966 (if (and
|
|
3967 verilog-indent-lists
|
|
3968 (not (verilog-in-coverage))
|
|
3969 (verilog-in-paren))
|
|
3970 (progn (setq par 1)
|
|
3971 (throw 'nesting 'block))
|
|
3972 )
|
|
3973
|
|
3974 ;; See if we are continuing a previous line
|
|
3975 (while t
|
|
3976 ;; trap out if we crawl off the top of the buffer
|
|
3977 (if (bobp) (throw 'nesting 'cpp))
|
|
3978
|
|
3979 (if (verilog-continued-line-1 lim)
|
|
3980 (let ((sp (point)))
|
|
3981 (if (and
|
|
3982 (not (looking-at verilog-complete-reg))
|
|
3983 (verilog-continued-line-1 lim))
|
|
3984 (progn (goto-char sp)
|
|
3985 (throw 'nesting 'cexp))
|
|
3986
|
|
3987 (goto-char sp))
|
|
3988
|
|
3989 (if (and begin
|
|
3990 (not verilog-indent-begin-after-if)
|
|
3991 (looking-at verilog-no-indent-begin-re))
|
|
3992 (progn
|
|
3993 (beginning-of-line)
|
|
3994 (skip-chars-forward " \t")
|
|
3995 (throw 'nesting 'statement))
|
|
3996 (progn
|
|
3997 (throw 'nesting 'cexp))))
|
|
3998 ;; not a continued line
|
|
3999 (goto-char starting_position))
|
|
4000
|
|
4001 (if (looking-at "\\<else\\>")
|
|
4002 ;; search back for governing if, striding across begin..end pairs
|
|
4003 ;; appropriately
|
|
4004 (let ((elsec 1))
|
|
4005 (while (verilog-re-search-backward verilog-ends-re nil 'move)
|
|
4006 (cond
|
|
4007 ((match-end 1) ; else, we're in deep
|
|
4008 (setq elsec (1+ elsec)))
|
|
4009 ((match-end 2) ; if
|
|
4010 (setq elsec (1- elsec))
|
|
4011 (if (= 0 elsec)
|
|
4012 (if verilog-align-ifelse
|
|
4013 (throw 'nesting 'statement)
|
|
4014 (progn ;; back up to first word on this line
|
|
4015 (beginning-of-line)
|
|
4016 (verilog-forward-syntactic-ws)
|
|
4017 (throw 'nesting 'statement)))))
|
|
4018 (t ; endblock
|
|
4019 ; try to leap back to matching outward block by striding across
|
|
4020 ; indent level changing tokens then immediately
|
|
4021 ; previous line governs indentation.
|
|
4022 (let (( reg) (nest 1))
|
|
4023 ;; verilog-ends => else|if|end|join(_any|_none|)|endcase|endclass|endtable|endspecify|endfunction|endtask|endgenerate|endgroup
|
|
4024 (cond
|
|
4025 ((match-end 3) ; end
|
|
4026 ;; Search back for matching begin
|
|
4027 (setq reg "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)" ))
|
|
4028 ((match-end 4) ; endcase
|
|
4029 ;; Search back for matching case
|
|
4030 (setq reg "\\(\\<randcase\\>\\|\\<case[xz]?\\>[^:]\\)\\|\\(\\<endcase\\>\\)" ))
|
|
4031 ((match-end 5) ; endfunction
|
|
4032 ;; Search back for matching function
|
|
4033 (setq reg "\\(\\<function\\>\\)\\|\\(\\<endfunction\\>\\)" ))
|
|
4034 ((match-end 6) ; endtask
|
|
4035 ;; Search back for matching task
|
|
4036 (setq reg "\\(\\<task\\>\\)\\|\\(\\<endtask\\>\\)" ))
|
|
4037 ((match-end 7) ; endspecify
|
|
4038 ;; Search back for matching specify
|
|
4039 (setq reg "\\(\\<specify\\>\\)\\|\\(\\<endspecify\\>\\)" ))
|
|
4040 ((match-end 8) ; endtable
|
|
4041 ;; Search back for matching table
|
|
4042 (setq reg "\\(\\<table\\>\\)\\|\\(\\<endtable\\>\\)" ))
|
|
4043 ((match-end 9) ; endgenerate
|
|
4044 ;; Search back for matching generate
|
|
4045 (setq reg "\\(\\<generate\\>\\)\\|\\(\\<endgenerate\\>\\)" ))
|
|
4046 ((match-end 10) ; joins
|
|
4047 ;; Search back for matching fork
|
|
4048 (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|none\\)?\\>\\)" ))
|
|
4049 ((match-end 11) ; class
|
|
4050 ;; Search back for matching class
|
|
4051 (setq reg "\\(\\<class\\>\\)\\|\\(\\<endclass\\>\\)" ))
|
|
4052 ((match-end 12) ; covergroup
|
|
4053 ;; Search back for matching covergroup
|
|
4054 (setq reg "\\(\\<covergroup\\>\\)\\|\\(\\<endgroup\\>\\)" ))
|
|
4055 )
|
|
4056 (catch 'skip
|
|
4057 (while (verilog-re-search-backward reg nil 'move)
|
|
4058 (cond
|
|
4059 ((match-end 1) ; begin
|
|
4060 (setq nest (1- nest))
|
|
4061 (if (= 0 nest)
|
|
4062 (throw 'skip 1)))
|
|
4063 ((match-end 2) ; end
|
|
4064 (setq nest (1+ nest)))))
|
|
4065 )
|
|
4066 ))
|
|
4067 ))))
|
|
4068 (throw 'nesting (verilog-calc-1))
|
|
4069 )
|
|
4070 );; catch nesting
|
|
4071 );; type
|
|
4072 )
|
|
4073 ;; Return type of block and indent level.
|
|
4074 (if (not type)
|
|
4075 (setq type 'cpp))
|
|
4076 (if (> par 0) ; Unclosed Parenthesis
|
|
4077 (list 'cparenexp par)
|
|
4078 (cond
|
|
4079 ((eq type 'case)
|
|
4080 (list type (verilog-case-indent-level)))
|
|
4081 ((eq type 'statement)
|
|
4082 (list type (current-column)))
|
|
4083 ((eq type 'defun)
|
|
4084 (list type 0))
|
|
4085 (t
|
|
4086 (list type (verilog-current-indent-level)))))
|
|
4087 )))
|
|
4088 (defun verilog-wai ()
|
|
4089 "Show matching nesting block for debugging."
|
|
4090 (interactive)
|
|
4091 (save-excursion
|
|
4092 (let ((nesting (verilog-calc-1)))
|
|
4093 (message "You are at nesting %s" nesting))))
|
|
4094
|
|
4095 (defun verilog-calc-1 ()
|
|
4096 (catch 'nesting
|
|
4097 (while (verilog-re-search-backward (concat "\\({\\|}\\|" verilog-indent-re "\\)") nil 'move)
|
|
4098 (cond
|
|
4099 ((equal (char-after) ?\{)
|
|
4100 (if (verilog-at-constraint-p)
|
|
4101 (throw 'nesting 'block)
|
|
4102 ))
|
|
4103 ((equal (char-after) ?\})
|
|
4104
|
|
4105 (let ((there (verilog-at-close-constraint-p)))
|
|
4106 (if there (goto-char there))))
|
|
4107
|
|
4108 ((looking-at verilog-beg-block-re-ordered)
|
|
4109 (cond
|
|
4110 ((match-end 2) ; *sigh* could be "unique case" or "priority casex"
|
|
4111 (let ((here (point)))
|
|
4112 (verilog-beg-of-statement)
|
|
4113 (if (looking-at verilog-extended-case-re)
|
|
4114 (throw 'nesting 'case)
|
|
4115 (goto-char here)))
|
|
4116 (throw 'nesting 'case))
|
|
4117
|
|
4118 ;; need to consider typedef struct here...
|
|
4119 ((looking-at "\\<class\\|struct\\|function\\|task\\|property\\>")
|
|
4120 ; *sigh* These words have an optional prefix:
|
|
4121 ; extern {virtual|protected}? function a();
|
|
4122 ; assert property (p_1);
|
|
4123 ; typedef class foo;
|
|
4124 ; and we don't want to confuse this with
|
|
4125 ; function a();
|
|
4126 ; property
|
|
4127 ; ...
|
|
4128 ; endfunction
|
|
4129 (let ((here (point)))
|
|
4130 (save-excursion
|
|
4131 (verilog-beg-of-statement)
|
|
4132 (if (= (point) here)
|
|
4133 (throw 'nesting 'block))
|
|
4134 )))
|
|
4135 (t (throw 'nesting 'block))))
|
|
4136
|
|
4137 ((looking-at verilog-end-block-re)
|
|
4138 (verilog-leap-to-head)
|
|
4139 (if (verilog-in-case-region-p)
|
|
4140 (progn
|
|
4141 (verilog-leap-to-case-head)
|
|
4142 (if (looking-at verilog-case-re)
|
|
4143 (throw 'nesting 'case)))))
|
|
4144
|
|
4145 ((looking-at (if (verilog-in-generate-region-p)
|
|
4146 verilog-defun-level-not-generate-re
|
|
4147 verilog-defun-level-re))
|
|
4148 (throw 'nesting 'defun))
|
|
4149
|
|
4150 ((looking-at verilog-cpp-level-re)
|
|
4151 (throw 'nesting 'cpp))
|
|
4152
|
|
4153 ((bobp)
|
|
4154 (throw 'nesting 'cpp))
|
|
4155 ))
|
|
4156 (throw 'nesting 'cpp)
|
|
4157 )
|
|
4158 )
|
|
4159
|
|
4160 (defun verilog-calculate-indent-directive ()
|
|
4161 "Return indentation level for directive.
|
|
4162 For speed, the searcher looks at the last directive, not the indent
|
|
4163 of the appropriate enclosing block."
|
|
4164 (let ((base -1) ;; Indent of the line that determines our indentation
|
|
4165 (ind 0) ;; Relative offset caused by other directives (like `endif on same line as `else)
|
|
4166 )
|
|
4167 ;; Start at current location, scan back for another directive
|
|
4168
|
|
4169 (save-excursion
|
|
4170 (beginning-of-line)
|
|
4171 (while (and (< base 0)
|
|
4172 (verilog-re-search-backward verilog-directive-re nil t))
|
|
4173 (cond ((save-excursion (skip-chars-backward " \t") (bolp))
|
|
4174 (setq base (current-indentation))
|
|
4175 ))
|
|
4176 (cond ((and (looking-at verilog-directive-end) (< base 0)) ;; Only matters when not at BOL
|
|
4177 (setq ind (- ind verilog-indent-level-directive)))
|
|
4178 ((and (looking-at verilog-directive-middle) (>= base 0)) ;; Only matters when at BOL
|
|
4179 (setq ind (+ ind verilog-indent-level-directive)))
|
|
4180 ((looking-at verilog-directive-begin)
|
|
4181 (setq ind (+ ind verilog-indent-level-directive)))))
|
|
4182 ;; Adjust indent to starting indent of critical line
|
|
4183 (setq ind (max 0 (+ ind base))))
|
|
4184
|
|
4185 (save-excursion
|
|
4186 (beginning-of-line)
|
|
4187 (skip-chars-forward " \t")
|
|
4188 (cond ((or (looking-at verilog-directive-middle)
|
|
4189 (looking-at verilog-directive-end))
|
|
4190 (setq ind (max 0 (- ind verilog-indent-level-directive))))))
|
|
4191 ind))
|
|
4192
|
|
4193 (defun verilog-leap-to-case-head ()
|
|
4194 (let ((nest 1))
|
|
4195 (while (/= 0 nest)
|
|
4196 (verilog-re-search-backward "\\(\\<randcase\\>\\|\\<case[xz]?\\>[^:]\\)\\|\\(\\<endcase\\>\\)" nil 'move)
|
|
4197 (cond
|
|
4198 ((match-end 1)
|
|
4199 (setq nest (1- nest)))
|
|
4200 ((match-end 2)
|
|
4201 (setq nest (1+ nest)))
|
|
4202 ((bobp)
|
|
4203 (ding 't)
|
|
4204 (setq nest 0))))))
|
|
4205
|
|
4206 (defun verilog-leap-to-head ()
|
|
4207 "Move point to the head of this block; jump from end to matching begin,
|
|
4208 from endcase to matching case, and so on."
|
|
4209 (let ((reg nil)
|
|
4210 snest
|
|
4211 (nest 1))
|
|
4212 (cond
|
|
4213 ((looking-at "\\<end\\>")
|
|
4214 ;; 1: Search back for matching begin
|
|
4215 (setq reg (concat "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)\\|"
|
|
4216 "\\(\\<endcase\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" )))
|
|
4217 ((looking-at "\\<endcase\\>")
|
|
4218 ;; 2: Search back for matching case
|
|
4219 (setq reg "\\(\\<randcase\\>\\|\\<case[xz]?\\>\\)\\|\\(\\<endcase\\>\\)" ))
|
|
4220 ((looking-at "\\<join\\(_any\\|_none\\)?\\>")
|
|
4221 ;; 3: Search back for matching fork
|
|
4222 (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" ))
|
|
4223 ((looking-at "\\<endclass\\>")
|
|
4224 ;; 4: Search back for matching class
|
|
4225 (setq reg "\\(\\<class\\>\\)\\|\\(\\<endclass\\>\\)" ))
|
|
4226 ((looking-at "\\<endtable\\>")
|
|
4227 ;; 5: Search back for matching table
|
|
4228 (setq reg "\\(\\<table\\>\\)\\|\\(\\<endtable\\>\\)" ))
|
|
4229 ((looking-at "\\<endspecify\\>")
|
|
4230 ;; 6: Search back for matching specify
|
|
4231 (setq reg "\\(\\<specify\\>\\)\\|\\(\\<endspecify\\>\\)" ))
|
|
4232 ((looking-at "\\<endfunction\\>")
|
|
4233 ;; 7: Search back for matching function
|
|
4234 (setq reg "\\(\\<function\\>\\)\\|\\(\\<endfunction\\>\\)" ))
|
|
4235 ((looking-at "\\<endgenerate\\>")
|
|
4236 ;; 8: Search back for matching generate
|
|
4237 (setq reg "\\(\\<generate\\>\\)\\|\\(\\<endgenerate\\>\\)" ))
|
|
4238 ((looking-at "\\<endtask\\>")
|
|
4239 ;; 9: Search back for matching task
|
|
4240 (setq reg "\\(\\<task\\>\\)\\|\\(\\<endtask\\>\\)" ))
|
|
4241 ((looking-at "\\<endgroup\\>")
|
|
4242 ;; 10: Search back for matching covergroup
|
|
4243 (setq reg "\\(\\<covergroup\\>\\)\\|\\(\\<endgroup\\>\\)" ))
|
|
4244 ((looking-at "\\<endproperty\\>")
|
|
4245 ;; 11: Search back for matching property
|
|
4246 (setq reg "\\(\\<property\\>\\)\\|\\(\\<endproperty\\>\\)" ))
|
|
4247 ((looking-at "\\<endinterface\\>")
|
|
4248 ;; 12: Search back for matching interface
|
|
4249 (setq reg "\\(\\<interface\\>\\)\\|\\(\\<endinterface\\>\\)" ))
|
|
4250 ((looking-at "\\<endsequence\\>")
|
|
4251 ;; 12: Search back for matching sequence
|
|
4252 (setq reg "\\(\\<\\(rand\\)?sequence\\>\\)\\|\\(\\<endsequence\\>\\)" ))
|
|
4253 ((looking-at "\\<endclocking\\>")
|
|
4254 ;; 12: Search back for matching clocking
|
|
4255 (setq reg "\\(\\<clocking\\)\\|\\(\\<endclocking\\>\\)" ))
|
|
4256 )
|
|
4257 (if reg
|
|
4258 (catch 'skip
|
|
4259 (let (sreg)
|
|
4260 (while (verilog-re-search-backward reg nil 'move)
|
|
4261 (cond
|
|
4262 ((match-end 1) ; begin
|
|
4263 (setq nest (1- nest))
|
|
4264 (if (= 0 nest)
|
|
4265 ;; Now previous line describes syntax
|
|
4266 (throw 'skip 1))
|
|
4267 (if (and snest
|
|
4268 (= snest nest))
|
|
4269 (setq reg sreg)))
|
|
4270 ((match-end 2) ; end
|
|
4271 (setq nest (1+ nest)))
|
|
4272 ((match-end 3)
|
|
4273 ;; endcase, jump to case
|
|
4274 (setq snest nest)
|
|
4275 (setq nest (1+ nest))
|
|
4276 (setq sreg reg)
|
|
4277 (setq reg "\\(\\<randcase\\>\\|\\<case[xz]?\\>[^:]\\)\\|\\(\\<endcase\\>\\)" ))
|
|
4278 ((match-end 4)
|
|
4279 ;; join, jump to fork
|
|
4280 (setq snest nest)
|
|
4281 (setq nest (1+ nest))
|
|
4282 (setq sreg reg)
|
|
4283 (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" ))
|
|
4284 )))))))
|
|
4285
|
|
4286 (defun verilog-continued-line ()
|
|
4287 "Return true if this is a continued line.
|
|
4288 Set point to where line starts"
|
|
4289 (let ((continued 't))
|
|
4290 (if (eq 0 (forward-line -1))
|
|
4291 (progn
|
|
4292 (end-of-line)
|
|
4293 (verilog-backward-ws&directives)
|
|
4294 (if (bobp)
|
|
4295 (setq continued nil)
|
|
4296 (while (and continued
|
|
4297 (save-excursion
|
|
4298 (skip-chars-backward " \t")
|
|
4299 (not (bolp))))
|
|
4300 (setq continued (verilog-backward-token))
|
|
4301 ) ;; while
|
|
4302 ))
|
|
4303 (setq continued nil))
|
|
4304 continued))
|
|
4305
|
|
4306 (defun verilog-backward-token ()
|
|
4307 "Step backward token, returning true if we are now at an end of line token."
|
|
4308 (interactive)
|
|
4309 (verilog-backward-syntactic-ws)
|
|
4310 (cond
|
|
4311 ((bolp)
|
|
4312 nil)
|
|
4313 (;-- Anything ending in a ; is complete
|
|
4314 (= (preceding-char) ?\;)
|
|
4315 nil)
|
|
4316 (; If a "}" is prefixed by a ";", then this is a complete statement
|
|
4317 ; i.e.: constraint foo { a = b; }
|
|
4318 (= (preceding-char) ?\})
|
|
4319 (progn
|
|
4320 (backward-char)
|
|
4321 (verilog-at-close-constraint-p))
|
|
4322 )
|
|
4323 (;-- constraint foo { a = b }
|
|
4324 ; is a complete statement. *sigh*
|
|
4325 (= (preceding-char) ?\{)
|
|
4326 (progn
|
|
4327 (backward-char)
|
|
4328 (not (verilog-at-constraint-p)))
|
|
4329 )
|
|
4330 (;-- Could be 'case (foo)' or 'always @(bar)' which is complete
|
|
4331 ; also could be simply '@(foo)'
|
|
4332 ; or foo u1 #(a=8)
|
|
4333 ; (b, ... which ISN'T complete
|
|
4334 ;;;; Do we need this???
|
|
4335 (= (preceding-char) ?\))
|
|
4336 (progn
|
|
4337 (backward-char)
|
|
4338 (backward-up-list 1)
|
|
4339 (verilog-backward-syntactic-ws)
|
|
4340 (let ((back (point)))
|
|
4341 (forward-word -1)
|
|
4342 (cond
|
|
4343 ((looking-at "\\<\\(always\\(_latch\\|_ff\\|_comb\\)?\\|case\\(\\|[xz]\\)\\|for\\(\\|each\\|ever\\)\\|i\\(f\\|nitial\\)\\|repeat\\|while\\)\\>")
|
|
4344 (not (looking-at "\\<randcase\\>\\|\\<case[xz]?\\>[^:]")))
|
|
4345 (t
|
|
4346 (goto-char back)
|
|
4347 (cond
|
|
4348 ((= (preceding-char) ?\@)
|
|
4349 (backward-char)
|
|
4350 (save-excursion
|
|
4351 (verilog-backward-token)
|
|
4352 (not (looking-at "\\<\\(always\\(_latch\\|_ff\\|_comb\\)?\\|initial\\|while\\)\\>"))))
|
|
4353 ((= (preceding-char) ?\#)
|
|
4354 (backward-char)
|
|
4355 )
|
|
4356 (t t))
|
|
4357 )))))
|
|
4358
|
|
4359 (;-- any of begin|initial|while are complete statements; 'begin : foo' is also complete
|
|
4360 t
|
|
4361 (forward-word -1)
|
|
4362 (cond
|
|
4363 ((looking-at "\\<else\\>")
|
|
4364 t)
|
|
4365 ((looking-at verilog-indent-re)
|
|
4366 nil)
|
|
4367 (t
|
|
4368 (let
|
|
4369 ((back (point)))
|
|
4370 (verilog-backward-syntactic-ws)
|
|
4371 (cond
|
|
4372 ((= (preceding-char) ?\:)
|
|
4373 (backward-char)
|
|
4374 (verilog-backward-syntactic-ws)
|
|
4375 (backward-sexp)
|
|
4376 (if (looking-at verilog-nameable-item-re )
|
|
4377 nil
|
|
4378 t)
|
|
4379 )
|
|
4380 ((= (preceding-char) ?\#)
|
|
4381 (backward-char)
|
|
4382 t)
|
|
4383 ((= (preceding-char) ?\`)
|
|
4384 (backward-char)
|
|
4385 t)
|
|
4386
|
|
4387 (t
|
|
4388 (goto-char back)
|
|
4389 t)
|
|
4390 )))))))
|
|
4391
|
|
4392 (defun verilog-backward-syntactic-ws (&optional bound)
|
|
4393 "Backward skip over syntactic whitespace for Emacs 19.
|
|
4394 Optional BOUND limits search."
|
|
4395 (save-restriction
|
|
4396 (let* ((bound (or bound (point-min))) (here bound) )
|
|
4397 (if (< bound (point))
|
|
4398 (progn
|
|
4399 (narrow-to-region bound (point))
|
|
4400 (while (/= here (point))
|
|
4401 (setq here (point))
|
|
4402 (verilog-skip-backward-comments)
|
|
4403 )))
|
|
4404 ))
|
|
4405 t)
|
|
4406
|
|
4407 (defun verilog-forward-syntactic-ws (&optional bound)
|
|
4408 "Forward skip over syntactic whitespace for Emacs 19.
|
|
4409 Optional BOUND limits search."
|
|
4410 (save-restriction
|
|
4411 (let* ((bound (or bound (point-max)))
|
|
4412 (here bound)
|
|
4413 )
|
|
4414 (if (> bound (point))
|
|
4415 (progn
|
|
4416 (narrow-to-region (point) bound)
|
|
4417 (while (/= here (point))
|
|
4418 (setq here (point))
|
|
4419 (forward-comment (buffer-size))
|
|
4420 )))
|
|
4421 )))
|
|
4422
|
|
4423 (defun verilog-backward-ws&directives (&optional bound)
|
|
4424 "Backward skip over syntactic whitespace and compiler directives for Emacs 19.
|
|
4425 Optional BOUND limits search."
|
|
4426 (save-restriction
|
|
4427 (let* ((bound (or bound (point-min)))
|
|
4428 (here bound)
|
|
4429 (p nil) )
|
|
4430 (if (< bound (point))
|
|
4431 (progn
|
|
4432 (let ((state
|
|
4433 (save-excursion
|
|
4434 (parse-partial-sexp (point-min) (point)))))
|
|
4435 (cond
|
|
4436 ((nth 7 state) ;; in // comment
|
|
4437 (verilog-re-search-backward "//" nil 'move)
|
|
4438 (skip-chars-backward "/"))
|
|
4439 ((nth 4 state) ;; in /* */ comment
|
|
4440 (verilog-re-search-backward "/\*" nil 'move))))
|
|
4441 (narrow-to-region bound (point))
|
|
4442 (while (/= here (point))
|
|
4443 (setq here (point))
|
|
4444 (verilog-skip-backward-comments)
|
|
4445 (setq p
|
|
4446 (save-excursion
|
|
4447 (beginning-of-line)
|
|
4448 (cond
|
|
4449 ((verilog-within-translate-off)
|
|
4450 (verilog-back-to-start-translate-off (point-min)))
|
|
4451 ((looking-at verilog-directive-re-1)
|
|
4452 (point))
|
|
4453 (t
|
|
4454 nil))))
|
|
4455 (if p (goto-char p))
|
|
4456 )))
|
|
4457 )))
|
|
4458
|
|
4459 (defun verilog-forward-ws&directives (&optional bound)
|
|
4460 "Forward skip over syntactic whitespace and compiler directives for Emacs 19.
|
|
4461 Optional BOUND limits search."
|
|
4462 (save-restriction
|
|
4463 (let* ((bound (or bound (point-max)))
|
|
4464 (here bound)
|
|
4465 jump
|
|
4466 )
|
|
4467 (if (> bound (point))
|
|
4468 (progn
|
|
4469 (let ((state
|
|
4470 (save-excursion
|
|
4471 (parse-partial-sexp (point-min) (point)))))
|
|
4472 (cond
|
|
4473 ((nth 7 state) ;; in // comment
|
|
4474 (verilog-re-search-forward "//" nil 'move))
|
|
4475 ((nth 4 state) ;; in /* */ comment
|
|
4476 (verilog-re-search-forward "/\*" nil 'move))))
|
|
4477 (narrow-to-region (point) bound)
|
|
4478 (while (/= here (point))
|
|
4479 (setq here (point)
|
|
4480 jump nil)
|
|
4481 (forward-comment (buffer-size))
|
|
4482 (save-excursion
|
|
4483 (beginning-of-line)
|
|
4484 (if (looking-at verilog-directive-re-1)
|
|
4485 (setq jump t)))
|
|
4486 (if jump
|
|
4487 (beginning-of-line 2))
|
|
4488 )))
|
|
4489 )))
|
|
4490
|
|
4491 (defun verilog-in-comment-p ()
|
|
4492 "Return true if in a star or // comment."
|
|
4493 (let ((state
|
|
4494 (save-excursion
|
|
4495 (parse-partial-sexp (point-min) (point)))))
|
|
4496 (or (nth 4 state) (nth 7 state))))
|
|
4497
|
|
4498 (defun verilog-in-star-comment-p ()
|
|
4499 "Return true if in a star comment."
|
|
4500 (let ((state
|
|
4501 (save-excursion
|
|
4502 (parse-partial-sexp (point-min) (point)))))
|
|
4503 (and
|
|
4504 (nth 4 state) ; t if in a comment of style a // or b /**/
|
|
4505 (not
|
|
4506 (nth 7 state) ; t if in a comment of style b /**/
|
|
4507 ))))
|
|
4508
|
|
4509 (defun verilog-in-slash-comment-p ()
|
|
4510 "Return true if in a slash comment."
|
|
4511 (let ((state
|
|
4512 (save-excursion
|
|
4513 (parse-partial-sexp (point-min) (point)))))
|
|
4514 (nth 7 state)))
|
|
4515
|
|
4516 (defun verilog-in-comment-or-string-p ()
|
|
4517 "Return true if in a string or comment."
|
|
4518 (let ((state
|
|
4519 (save-excursion
|
|
4520 (parse-partial-sexp (point-min) (point)))))
|
|
4521 (or (nth 3 state) (nth 4 state) (nth 7 state)))) ; Inside string or comment)
|
|
4522
|
|
4523 (defun verilog-in-escaped-name-p ()
|
|
4524 "Return true if in an escaped name."
|
|
4525 (save-excursion
|
|
4526 (backward-char)
|
|
4527 (skip-chars-backward "^ \t\n\f")
|
|
4528 (if (equal (char-after (point) ) ?\\ )
|
|
4529 t
|
|
4530 nil)))
|
|
4531
|
|
4532 (defun verilog-in-paren ()
|
|
4533 "Return true if in a parenthetical expression."
|
|
4534 (let ((state
|
|
4535 (save-excursion
|
|
4536 (parse-partial-sexp (point-min) (point)))))
|
|
4537 (> (nth 0 state) 0 )))
|
|
4538
|
|
4539 (defun verilog-in-coverage ()
|
|
4540 "Return true if in a constraint or coverpoint expression."
|
|
4541 (interactive)
|
|
4542 (save-excursion
|
|
4543 (if (verilog-in-paren)
|
|
4544 (progn
|
|
4545 (backward-up-list 1)
|
|
4546 (verilog-at-constraint-p)
|
|
4547 )
|
|
4548 nil)))
|
|
4549 (defun verilog-at-close-constraint-p ()
|
|
4550 "If at the } that closes a constraint or covergroup, return true."
|
|
4551 (if (and
|
|
4552 (equal (char-after) ?\})
|
|
4553 (verilog-in-paren))
|
|
4554
|
|
4555 (save-excursion
|
|
4556 (verilog-backward-ws&directives)
|
|
4557 (if (equal (char-before) ?\;)
|
|
4558 (point)
|
|
4559 nil))))
|
|
4560
|
|
4561 (defun verilog-at-constraint-p ()
|
|
4562 "If at the { of a constraint or coverpoint definition, return true, moving point to constraint."
|
|
4563 (if (save-excursion
|
|
4564 (and
|
|
4565 (equal (char-after) ?\{)
|
|
4566 (forward-list)
|
|
4567 (progn (backward-char 1)
|
|
4568 (verilog-backward-ws&directives)
|
|
4569 (equal (char-before) ?\;))
|
|
4570 ))
|
|
4571 ;; maybe
|
|
4572 (verilog-re-search-backward "\\<constraint\\|coverpoint\\|cross\\>" nil 'move)
|
|
4573 ;; not
|
|
4574 nil
|
|
4575 )
|
|
4576 )
|
|
4577
|
|
4578 (defun verilog-parenthesis-depth ()
|
|
4579 "Return non zero if in parenthetical-expression."
|
|
4580 (save-excursion
|
|
4581 (nth 1 (parse-partial-sexp (point-min) (point)))))
|
|
4582
|
|
4583
|
|
4584 (defun verilog-skip-forward-comment-or-string ()
|
|
4585 "Return true if in a string or comment."
|
|
4586 (let ((state
|
|
4587 (save-excursion
|
|
4588 (parse-partial-sexp (point-min) (point)))))
|
|
4589 (cond
|
|
4590 ((nth 3 state) ;Inside string
|
|
4591 (goto-char (nth 3 state))
|
|
4592 t)
|
|
4593 ((nth 7 state) ;Inside // comment
|
|
4594 (forward-line 1)
|
|
4595 t)
|
|
4596 ((nth 4 state) ;Inside any comment (hence /**/)
|
|
4597 (search-forward "*/"))
|
|
4598 (t
|
|
4599 nil))))
|
|
4600
|
|
4601 (defun verilog-skip-backward-comment-or-string ()
|
|
4602 "Return true if in a string or comment."
|
|
4603 (let ((state
|
|
4604 (save-excursion
|
|
4605 (parse-partial-sexp (point-min) (point)))))
|
|
4606 (cond
|
|
4607 ((nth 3 state) ;Inside string
|
|
4608 (search-backward "\"")
|
|
4609 t)
|
|
4610 ((nth 7 state) ;Inside // comment
|
|
4611 (search-backward "//")
|
|
4612 (skip-chars-backward "/")
|
|
4613 t)
|
|
4614 ((nth 4 state) ;Inside /* */ comment
|
|
4615 (search-backward "/*")
|
|
4616 t)
|
|
4617 (t
|
|
4618 nil))))
|
|
4619
|
|
4620 (defun verilog-skip-backward-comments ()
|
|
4621 "Return true if a comment was skipped."
|
|
4622 (let ((more t))
|
|
4623 (while more
|
|
4624 (setq more
|
|
4625 (let ((state
|
|
4626 (save-excursion
|
|
4627 (parse-partial-sexp (point-min) (point)))))
|
|
4628 (cond
|
|
4629 ((nth 7 state) ;Inside // comment
|
|
4630 (search-backward "//")
|
|
4631 (skip-chars-backward "/")
|
|
4632 (skip-chars-backward " \t\n\f")
|
|
4633 t)
|
|
4634 ((nth 4 state) ;Inside /* */ comment
|
|
4635 (search-backward "/*")
|
|
4636 (skip-chars-backward " \t\n\f")
|
|
4637 t)
|
|
4638 ((and (not (bobp))
|
|
4639 (= (char-before) ?\/)
|
|
4640 (= (char-before (1- (point))) ?\*)
|
|
4641 )
|
|
4642 (goto-char (- (point) 2))
|
|
4643 t)
|
|
4644 (t
|
|
4645 (skip-chars-backward " \t\n\f")
|
|
4646 nil)))))))
|
|
4647
|
|
4648 (defun verilog-skip-forward-comment-p ()
|
|
4649 "If in comment, move to end and return true."
|
|
4650 (let (state)
|
|
4651 (progn
|
|
4652 (setq state
|
|
4653 (save-excursion
|
|
4654 (parse-partial-sexp (point-min) (point))))
|
|
4655 (cond
|
|
4656 ((nth 3 state)
|
|
4657 t)
|
|
4658 ((nth 7 state) ;Inside // comment
|
|
4659 (end-of-line)
|
|
4660 (forward-char 1)
|
|
4661 t)
|
|
4662 ((nth 4 state) ;Inside any comment
|
|
4663 t)
|
|
4664 (t
|
|
4665 nil)))))
|
|
4666
|
|
4667 (defun verilog-indent-line-relative ()
|
|
4668 "Cheap version of indent line.
|
|
4669 Only look at a few lines to determine indent level."
|
|
4670 (interactive)
|
|
4671 (let ((indent-str)
|
|
4672 (sp (point)))
|
|
4673 (if (looking-at "^[ \t]*$")
|
|
4674 (cond ;- A blank line; No need to be too smart.
|
|
4675 ((bobp)
|
|
4676 (setq indent-str (list 'cpp 0)))
|
|
4677 ((verilog-continued-line)
|
|
4678 (let ((sp1 (point)))
|
|
4679 (if (verilog-continued-line)
|
|
4680 (progn (goto-char sp)
|
|
4681 (setq indent-str (list 'statement (verilog-current-indent-level))))
|
|
4682 (goto-char sp1)
|
|
4683 (setq indent-str (list 'block (verilog-current-indent-level)))))
|
|
4684 (goto-char sp))
|
|
4685 ((goto-char sp)
|
|
4686 (setq indent-str (verilog-calculate-indent))))
|
|
4687 (progn (skip-chars-forward " \t")
|
|
4688 (setq indent-str (verilog-calculate-indent))))
|
|
4689 (verilog-do-indent indent-str)))
|
|
4690
|
|
4691 (defun verilog-indent-line ()
|
|
4692 "Indent for special part of code."
|
|
4693 (verilog-do-indent (verilog-calculate-indent)))
|
|
4694
|
|
4695 (defun verilog-do-indent (indent-str)
|
|
4696 (let ((type (car indent-str))
|
|
4697 (ind (car (cdr indent-str))))
|
|
4698 (cond
|
|
4699 (; handle continued exp
|
|
4700 (eq type 'cexp)
|
|
4701 (let ((here (point)))
|
|
4702 (verilog-backward-syntactic-ws)
|
|
4703 (cond
|
|
4704 ((or
|
|
4705 (= (preceding-char) ?\,)
|
|
4706 (= (preceding-char) ?\])
|
|
4707 (save-excursion
|
|
4708 (verilog-beg-of-statement-1)
|
|
4709 (looking-at verilog-declaration-re)))
|
|
4710 (let* ( fst
|
|
4711 (val
|
|
4712 (save-excursion
|
|
4713 (backward-char 1)
|
|
4714 (verilog-beg-of-statement-1)
|
|
4715 (setq fst (point))
|
|
4716 (if (looking-at verilog-declaration-re)
|
|
4717 (progn ;; we have multiple words
|
|
4718 (goto-char (match-end 0))
|
|
4719 (skip-chars-forward " \t")
|
|
4720 (cond
|
|
4721 ((and verilog-indent-declaration-macros
|
|
4722 (= (following-char) ?\`))
|
|
4723 (progn
|
|
4724 (forward-char 1)
|
|
4725 (forward-word 1)
|
|
4726 (skip-chars-forward " \t")))
|
|
4727 ((= (following-char) ?\[)
|
|
4728 (progn
|
|
4729 (forward-char 1)
|
|
4730 (backward-up-list -1)
|
|
4731 (skip-chars-forward " \t")))
|
|
4732 )
|
|
4733 (current-column))
|
|
4734 (progn
|
|
4735 (goto-char fst)
|
|
4736 (+ (current-column) verilog-cexp-indent))
|
|
4737 ))))
|
|
4738 (goto-char here)
|
|
4739 (indent-line-to val))
|
|
4740 )
|
|
4741 ((= (preceding-char) ?\) )
|
|
4742 (goto-char here)
|
|
4743 (let ((val (eval (cdr (assoc type verilog-indent-alist)))))
|
|
4744 (indent-line-to val)))
|
|
4745 (t
|
|
4746 (goto-char here)
|
|
4747 (let ((val))
|
|
4748 (verilog-beg-of-statement-1)
|
|
4749 (if (and (< (point) here)
|
|
4750 (verilog-re-search-forward "=[ \\t]*" here 'move))
|
|
4751 (setq val (current-column))
|
|
4752 (setq val (eval (cdr (assoc type verilog-indent-alist)))))
|
|
4753 (goto-char here)
|
|
4754 (indent-line-to val)))
|
|
4755 )))
|
|
4756
|
|
4757 (; handle inside parenthetical expressions
|
|
4758 (eq type 'cparenexp)
|
|
4759 (let ((val (save-excursion
|
|
4760 (backward-up-list 1)
|
|
4761 (forward-char 1)
|
|
4762 (skip-chars-forward " \t")
|
|
4763 (current-column))))
|
|
4764 (indent-line-to val)
|
|
4765 (if (and (not (verilog-in-struct-region-p))
|
|
4766 (looking-at verilog-declaration-re))
|
|
4767 (verilog-indent-declaration ind))
|
|
4768 ))
|
|
4769
|
|
4770 (;-- Handle the ends
|
|
4771 (or
|
|
4772 (looking-at verilog-end-block-re )
|
|
4773 (verilog-at-close-constraint-p))
|
|
4774 (let ((val (if (eq type 'statement)
|
|
4775 (- ind verilog-indent-level)
|
|
4776 ind)))
|
|
4777 (indent-line-to val)))
|
|
4778
|
|
4779 (;-- Case -- maybe line 'em up
|
|
4780 (and (eq type 'case) (not (looking-at "^[ \t]*$")))
|
|
4781 (progn
|
|
4782 (cond
|
|
4783 ((looking-at "\\<endcase\\>")
|
|
4784 (indent-line-to ind))
|
|
4785 (t
|
|
4786 (let ((val (eval (cdr (assoc type verilog-indent-alist)))))
|
|
4787 (indent-line-to val))))))
|
|
4788
|
|
4789 (;-- defun
|
|
4790 (and (eq type 'defun)
|
|
4791 (looking-at verilog-zero-indent-re))
|
|
4792 (indent-line-to 0))
|
|
4793
|
|
4794 (;-- declaration
|
|
4795 (and (or
|
|
4796 (eq type 'defun)
|
|
4797 (eq type 'block))
|
|
4798 (looking-at verilog-declaration-re))
|
|
4799 (verilog-indent-declaration ind))
|
|
4800
|
|
4801 (;-- Everything else
|
|
4802 t
|
|
4803 (let ((val (eval (cdr (assoc type verilog-indent-alist)))))
|
|
4804 (indent-line-to val)))
|
|
4805 )
|
|
4806 (if (looking-at "[ \t]+$")
|
|
4807 (skip-chars-forward " \t"))
|
|
4808 indent-str ; Return indent data
|
|
4809 ))
|
|
4810
|
|
4811 (defun verilog-current-indent-level ()
|
|
4812 "Return the indent-level the current statement has."
|
|
4813 (save-excursion
|
|
4814 (let (par-pos)
|
|
4815 (beginning-of-line)
|
|
4816 (setq par-pos (verilog-parenthesis-depth))
|
|
4817 (while par-pos
|
|
4818 (goto-char par-pos)
|
|
4819 (beginning-of-line)
|
|
4820 (setq par-pos (verilog-parenthesis-depth)))
|
|
4821 (skip-chars-forward " \t")
|
|
4822 (current-column))))
|
|
4823
|
|
4824 (defun verilog-case-indent-level ()
|
|
4825 "Return the indent-level the current statement has.
|
|
4826 Do not count named blocks or case-statements."
|
|
4827 (save-excursion
|
|
4828 (skip-chars-forward " \t")
|
|
4829 (cond
|
|
4830 ((looking-at verilog-named-block-re)
|
|
4831 (current-column))
|
|
4832 ((and (not (looking-at verilog-case-re))
|
|
4833 (looking-at "^[^:;]+[ \t]*:"))
|
|
4834 (verilog-re-search-forward ":" nil t)
|
|
4835 (skip-chars-forward " \t")
|
|
4836 (current-column))
|
|
4837 (t
|
|
4838 (current-column)))))
|
|
4839
|
|
4840 (defun verilog-indent-comment ()
|
|
4841 "Indent current line as comment."
|
|
4842 (let* ((stcol
|
|
4843 (cond
|
|
4844 ((verilog-in-star-comment-p)
|
|
4845 (save-excursion
|
|
4846 (re-search-backward "/\\*" nil t)
|
|
4847 (1+(current-column))))
|
|
4848 (comment-column
|
|
4849 comment-column )
|
|
4850 (t
|
|
4851 (save-excursion
|
|
4852 (re-search-backward "//" nil t)
|
|
4853 (current-column)))
|
|
4854 )))
|
|
4855 (indent-line-to stcol)
|
|
4856 stcol))
|
|
4857
|
|
4858 (defun verilog-more-comment ()
|
|
4859 "Make more comment lines like the previous."
|
|
4860 (let* ((star 0)
|
|
4861 (stcol
|
|
4862 (cond
|
|
4863 ((verilog-in-star-comment-p)
|
|
4864 (save-excursion
|
|
4865 (setq star 1)
|
|
4866 (re-search-backward "/\\*" nil t)
|
|
4867 (1+(current-column))))
|
|
4868 (comment-column
|
|
4869 comment-column )
|
|
4870 (t
|
|
4871 (save-excursion
|
|
4872 (re-search-backward "//" nil t)
|
|
4873 (current-column)))
|
|
4874 )))
|
|
4875 (progn
|
|
4876 (indent-to stcol)
|
|
4877 (if (and star
|
|
4878 (save-excursion
|
|
4879 (forward-line -1)
|
|
4880 (skip-chars-forward " \t")
|
|
4881 (looking-at "\*")))
|
|
4882 (insert "* ")))))
|
|
4883
|
|
4884 (defun verilog-comment-indent (&optional arg)
|
|
4885 "Return the column number the line should be indented to.
|
|
4886 ARG is ignored, for `comment-indent-function' compatibility."
|
|
4887 (cond
|
|
4888 ((verilog-in-star-comment-p)
|
|
4889 (save-excursion
|
|
4890 (re-search-backward "/\\*" nil t)
|
|
4891 (1+(current-column))))
|
|
4892 ( comment-column
|
|
4893 comment-column )
|
|
4894 (t
|
|
4895 (save-excursion
|
|
4896 (re-search-backward "//" nil t)
|
|
4897 (current-column)))))
|
|
4898
|
|
4899 ;;
|
|
4900
|
|
4901 (defun verilog-pretty-declarations ()
|
|
4902 "Line up declarations around point."
|
|
4903 (interactive)
|
|
4904 (save-excursion
|
|
4905 (if (progn
|
|
4906 (verilog-beg-of-statement-1)
|
|
4907 (looking-at verilog-declaration-re))
|
|
4908 (let* ((m1 (make-marker))
|
|
4909 (e) (r)
|
|
4910 (here (point))
|
|
4911 ;; Start of declaration range
|
|
4912 (start
|
|
4913 (progn
|
|
4914 (verilog-beg-of-statement-1)
|
|
4915 (while (looking-at verilog-declaration-re)
|
|
4916 (beginning-of-line)
|
|
4917 (setq e (point))
|
|
4918 (verilog-backward-syntactic-ws)
|
|
4919 (backward-char)
|
|
4920 (verilog-beg-of-statement-1)) ;Ack, need to grok `define
|
|
4921 e))
|
|
4922 ;; End of declaration range
|
|
4923 (end
|
|
4924 (progn
|
|
4925 (goto-char here)
|
|
4926 (verilog-end-of-statement)
|
|
4927 (setq e (point)) ;Might be on last line
|
|
4928 (verilog-forward-syntactic-ws)
|
|
4929 (while (looking-at verilog-declaration-re)
|
|
4930 (beginning-of-line)
|
|
4931 (verilog-end-of-statement)
|
|
4932 (setq e (point))
|
|
4933 (verilog-forward-syntactic-ws))
|
|
4934 e))
|
|
4935 (edpos (set-marker (make-marker) end))
|
|
4936 (ind)
|
|
4937 (base-ind
|
|
4938 (progn
|
|
4939 (goto-char start)
|
|
4940 (verilog-do-indent (verilog-calculate-indent))
|
|
4941 (verilog-forward-ws&directives)
|
|
4942 (current-column)))
|
|
4943 )
|
|
4944 (goto-char end)
|
|
4945 (goto-char start)
|
|
4946 (if (> (- end start) 100)
|
|
4947 (message "Lining up declarations..(please stand by)"))
|
|
4948 ;; Get the beginning of line indent first
|
|
4949 (while (progn (setq e (marker-position edpos))
|
|
4950 (< (point) e))
|
|
4951 (cond
|
|
4952 ( (save-excursion (skip-chars-backward " \t")
|
|
4953 (bolp))
|
|
4954 (verilog-forward-ws&directives)
|
|
4955 (indent-line-to base-ind)
|
|
4956 (verilog-forward-ws&directives)
|
|
4957 (verilog-re-search-forward "[ \t\n\f]" e 'move)
|
|
4958 )
|
|
4959 (t
|
|
4960 (just-one-space)
|
|
4961 (verilog-re-search-forward "[ \t\n\f]" e 'move)
|
|
4962 )
|
|
4963 )
|
|
4964 )
|
|
4965 ;;(forward-line))
|
|
4966 ;; Now find biggest prefix
|
|
4967 (setq ind (verilog-get-lineup-indent start edpos))
|
|
4968 ;; Now indent each line.
|
|
4969 (goto-char start)
|
|
4970 (while (progn (setq e (marker-position edpos))
|
|
4971 (setq r (- e (point)))
|
|
4972 (> r 0))
|
|
4973 (setq e (point))
|
|
4974 (message "%d" r)
|
|
4975 (cond
|
|
4976 ((or (and verilog-indent-declaration-macros
|
|
4977 (looking-at verilog-declaration-re-1-macro))
|
|
4978 (looking-at verilog-declaration-re-1-no-macro))
|
|
4979 (let ((p (match-end 0)))
|
|
4980 (set-marker m1 p)
|
|
4981 (if (verilog-re-search-forward "[[#`]" p 'move)
|
|
4982 (progn
|
|
4983 (forward-char -1)
|
|
4984 (just-one-space)
|
|
4985 (goto-char (marker-position m1))
|
|
4986 (just-one-space)
|
|
4987 (indent-to ind))
|
|
4988 (progn
|
|
4989 (just-one-space)
|
|
4990 (indent-to ind))
|
|
4991 )))
|
|
4992 ((verilog-continued-line-1 start)
|
|
4993 (goto-char e)
|
|
4994 (indent-line-to ind))
|
|
4995 (t ; Must be comment or white space
|
|
4996 (goto-char e)
|
|
4997 (verilog-forward-ws&directives)
|
|
4998 (forward-line -1))
|
|
4999 )
|
|
5000 (forward-line 1))
|
|
5001 (message "")))))
|
|
5002
|
|
5003 (defun verilog-pretty-expr (&optional myre)
|
|
5004 "Line up expressions around point."
|
|
5005 (interactive "sRegular Expression: ((<|:)?=) ")
|
|
5006 (save-excursion
|
|
5007 (if (or (eq myre nil)
|
|
5008 (string-equal myre ""))
|
|
5009 (setq myre "\\(<\\|:\\)?="))
|
|
5010 ; (setq myre (concat "\\(^[^;" myre "]*\\)\\([" myre "]\\)"))
|
|
5011 (setq myre (concat "\\(^[^;#:?=]*\\)\\([" myre "]\\)"))
|
|
5012 (beginning-of-line)
|
|
5013 (if (and (not (looking-at (concat "^\\s-*" verilog-complete-reg)))
|
|
5014 (looking-at myre))
|
|
5015 (let* ((here (point))
|
|
5016 (e) (r)
|
|
5017 (start
|
|
5018 (progn
|
|
5019 (beginning-of-line)
|
|
5020 (setq e (point))
|
|
5021 (verilog-backward-syntactic-ws)
|
|
5022 (beginning-of-line)
|
|
5023 (while (and (not (looking-at (concat "^\\s-*" verilog-complete-reg)))
|
|
5024 (looking-at myre)
|
|
5025 (not (bobp))
|
|
5026 )
|
|
5027 (setq e (point))
|
|
5028 (verilog-backward-syntactic-ws)
|
|
5029 (beginning-of-line)
|
|
5030 ) ;Ack, need to grok `define
|
|
5031 e))
|
|
5032 (end
|
|
5033 (progn
|
|
5034 (goto-char here)
|
|
5035 (end-of-line)
|
|
5036 (setq e (point)) ;Might be on last line
|
|
5037 (verilog-forward-syntactic-ws)
|
|
5038 (beginning-of-line)
|
|
5039 (while (and (not(looking-at (concat "^\\s-*" verilog-complete-reg)))
|
|
5040 (looking-at myre))
|
|
5041 (end-of-line)
|
|
5042 (setq e (point))
|
|
5043 (verilog-forward-syntactic-ws)
|
|
5044 (beginning-of-line)
|
|
5045 )
|
|
5046 e))
|
|
5047 (edpos (set-marker (make-marker) end))
|
|
5048 (ind)
|
|
5049 )
|
|
5050 (goto-char start)
|
|
5051 (verilog-do-indent (verilog-calculate-indent))
|
|
5052 (if (> (- end start) 100)
|
|
5053 (message "Lining up expressions..(please stand by)"))
|
|
5054
|
|
5055 ;; Set indent to minimum throughout region
|
|
5056 (while (< (point) (marker-position edpos))
|
|
5057 (beginning-of-line)
|
|
5058 (verilog-just-one-space myre)
|
|
5059 (end-of-line)
|
|
5060 (verilog-forward-syntactic-ws)
|
|
5061 )
|
|
5062
|
|
5063 ;; Now find biggest prefix
|
|
5064 (setq ind (verilog-get-lineup-indent-2 myre start edpos))
|
|
5065
|
|
5066 ;; Now indent each line.
|
|
5067 (goto-char start)
|
|
5068 (while (progn (setq e (marker-position edpos))
|
|
5069 (setq r (- e (point)))
|
|
5070 (> r 0))
|
|
5071 (setq e (point))
|
|
5072 (message "%d" r)
|
|
5073 (cond
|
|
5074 ((looking-at myre)
|
|
5075 (goto-char (match-end 1))
|
|
5076 (if (eq (char-after) ?=)
|
|
5077 (indent-to (1+ ind)) ; line up the = of the <= with surrounding =
|
|
5078 (indent-to ind)
|
|
5079 )
|
|
5080 )
|
|
5081 ((verilog-continued-line-1 start)
|
|
5082 (goto-char e)
|
|
5083 (indent-line-to ind))
|
|
5084 (t ; Must be comment or white space
|
|
5085 (goto-char e)
|
|
5086 (verilog-forward-ws&directives)
|
|
5087 (forward-line -1))
|
|
5088 )
|
|
5089 (forward-line 1))
|
|
5090 (message "")
|
|
5091 ))))
|
|
5092
|
|
5093 (defun verilog-just-one-space (myre)
|
|
5094 "Remove extra spaces around regular expression MYRE."
|
|
5095 (interactive)
|
|
5096 (if (and (not(looking-at verilog-complete-reg))
|
|
5097 (looking-at myre))
|
|
5098 (let ((p1 (match-end 1))
|
|
5099 (p2 (match-end 2)))
|
|
5100 (progn
|
|
5101 (goto-char p2)
|
|
5102 (if (looking-at "\\s-") (just-one-space) )
|
|
5103 (goto-char p1)
|
|
5104 (forward-char -1)
|
|
5105 (if (looking-at "\\s-") (just-one-space))
|
|
5106 )
|
|
5107 ))
|
|
5108 (message ""))
|
|
5109
|
|
5110 (defun verilog-indent-declaration (baseind)
|
|
5111 "Indent current lines as declaration.
|
|
5112 Line up the variable names based on previous declaration's indentation.
|
|
5113 BASEIND is the base indent to offset everything."
|
|
5114 (interactive)
|
|
5115 (let ((pos (point-marker))
|
|
5116 (lim (save-excursion
|
|
5117 ;; (verilog-re-search-backward verilog-declaration-opener nil 'move)
|
|
5118 (verilog-re-search-backward "\\(\\<begin\\>\\)\\|\\(\\<module\\>\\)\\|\\(\\<task\\>\\)" nil 'move)
|
|
5119 (point)))
|
|
5120 (ind)
|
|
5121 (val)
|
|
5122 (m1 (make-marker))
|
|
5123 )
|
|
5124 (setq val (+ baseind (eval (cdr (assoc 'declaration verilog-indent-alist)))))
|
|
5125 (indent-line-to val)
|
|
5126
|
|
5127 ;; Use previous declaration (in this module) as template.
|
|
5128 (if (or (memq 'all verilog-auto-lineup)
|
|
5129 (memq 'declaration verilog-auto-lineup))
|
|
5130 (if (verilog-re-search-backward
|
|
5131 (or (and verilog-indent-declaration-macros
|
|
5132 verilog-declaration-re-1-macro)
|
|
5133 verilog-declaration-re-1-no-macro) lim t)
|
|
5134 (progn
|
|
5135 (goto-char (match-end 0))
|
|
5136 (skip-chars-forward " \t")
|
|
5137 (setq ind (current-column))
|
|
5138 (goto-char pos)
|
|
5139 (setq val (+ baseind (eval (cdr (assoc 'declaration verilog-indent-alist)))))
|
|
5140 (indent-line-to val)
|
|
5141 (if (and verilog-indent-declaration-macros
|
|
5142 (looking-at verilog-declaration-re-2-macro))
|
|
5143 (let ((p (match-end 0)))
|
|
5144 (set-marker m1 p)
|
|
5145 (if (verilog-re-search-forward "[[#`]" p 'move)
|
|
5146 (progn
|
|
5147 (forward-char -1)
|
|
5148 (just-one-space)
|
|
5149 (goto-char (marker-position m1))
|
|
5150 (just-one-space)
|
|
5151 (indent-to ind)
|
|
5152 )
|
|
5153 (if (/= (current-column) ind)
|
|
5154 (progn
|
|
5155 (just-one-space)
|
|
5156 (indent-to ind))
|
|
5157 )))
|
|
5158 (if (looking-at verilog-declaration-re-2-no-macro)
|
|
5159 (let ((p (match-end 0)))
|
|
5160 (set-marker m1 p)
|
|
5161 (if (verilog-re-search-forward "[[`#]" p 'move)
|
|
5162 (progn
|
|
5163 (forward-char -1)
|
|
5164 (just-one-space)
|
|
5165 (goto-char (marker-position m1))
|
|
5166 (just-one-space)
|
|
5167 (indent-to ind))
|
|
5168 (if (/= (current-column) ind)
|
|
5169 (progn
|
|
5170 (just-one-space)
|
|
5171 (indent-to ind))
|
|
5172 )))
|
|
5173 )))
|
|
5174 )
|
|
5175 )
|
|
5176 (goto-char pos)
|
|
5177 )
|
|
5178 )
|
|
5179
|
|
5180 (defun verilog-get-lineup-indent (b edpos)
|
|
5181 "Return the indent level that will line up several lines within the region.
|
|
5182 Region is defined by B and EDPOS."
|
|
5183 (save-excursion
|
|
5184 (let ((ind 0) e)
|
|
5185 (goto-char b)
|
|
5186 ;; Get rightmost position
|
|
5187 (while (progn (setq e (marker-position edpos))
|
|
5188 (< (point) e))
|
|
5189 (if (verilog-re-search-forward
|
|
5190 (or (and verilog-indent-declaration-macros
|
|
5191 verilog-declaration-re-1-macro)
|
|
5192 verilog-declaration-re-1-no-macro) e 'move)
|
|
5193 (progn
|
|
5194 (goto-char (match-end 0))
|
|
5195 (verilog-backward-syntactic-ws)
|
|
5196 (if (> (current-column) ind)
|
|
5197 (setq ind (current-column)))
|
|
5198 (goto-char (match-end 0)))))
|
|
5199 (if (> ind 0)
|
|
5200 (1+ ind)
|
|
5201 ;; No lineup-string found
|
|
5202 (goto-char b)
|
|
5203 (end-of-line)
|
|
5204 (skip-chars-backward " \t")
|
|
5205 (1+ (current-column))))))
|
|
5206
|
|
5207 (defun verilog-get-lineup-indent-2 (myre b edpos)
|
|
5208 "Return the indent level that will line up several lines within the region."
|
|
5209 (save-excursion
|
|
5210 (let ((ind 0) e)
|
|
5211 (goto-char b)
|
|
5212 ;; Get rightmost position
|
|
5213 (while (progn (setq e (marker-position edpos))
|
|
5214 (< (point) e))
|
|
5215 (if (verilog-re-search-forward myre e 'move)
|
|
5216 (progn
|
|
5217 (goto-char (match-end 0))
|
|
5218 (verilog-backward-syntactic-ws)
|
|
5219 (if (> (current-column) ind)
|
|
5220 (setq ind (current-column)))
|
|
5221 (goto-char (match-end 0)))))
|
|
5222 (if (> ind 0)
|
|
5223 (1+ ind)
|
|
5224 ;; No lineup-string found
|
|
5225 (goto-char b)
|
|
5226 (end-of-line)
|
|
5227 (skip-chars-backward " \t")
|
|
5228 (1+ (current-column))))))
|
|
5229
|
|
5230 (defun verilog-comment-depth (type val)
|
|
5231 "A useful mode debugging aide. TYPE and VAL are comments for insertion."
|
|
5232 (save-excursion
|
|
5233 (let
|
|
5234 ((b (prog2
|
|
5235 (beginning-of-line)
|
|
5236 (point-marker)
|
|
5237 (end-of-line)))
|
|
5238 (e (point-marker)))
|
|
5239 (if (re-search-backward " /\\* \[#-\]# \[a-zA-Z\]+ \[0-9\]+ ## \\*/" b t)
|
|
5240 (progn
|
|
5241 (replace-match " /* -# ## */")
|
|
5242 (end-of-line))
|
|
5243 (progn
|
|
5244 (end-of-line)
|
|
5245 (insert " /* ## ## */"))))
|
|
5246 (backward-char 6)
|
|
5247 (insert
|
|
5248 (format "%s %d" type val))))
|
|
5249
|
|
5250 ;;
|
|
5251 ;;
|
|
5252 ;; Completion
|
|
5253 ;;
|
|
5254 (defvar verilog-str nil)
|
|
5255 (defvar verilog-all nil)
|
|
5256 (defvar verilog-pred nil)
|
|
5257 (defvar verilog-buffer-to-use nil)
|
|
5258 (defvar verilog-flag nil)
|
|
5259 (defvar verilog-toggle-completions nil
|
|
5260 "*True means \\<verilog-mode-map>\\[verilog-complete-word] should try all possible completions one by one.
|
|
5261 Repeated use of \\[verilog-complete-word] will show you all of them.
|
|
5262 Normally, when there is more than one possible completion,
|
|
5263 it displays a list of all possible completions.")
|
|
5264
|
|
5265
|
|
5266 (defvar verilog-type-keywords
|
|
5267 '(
|
|
5268 "and" "buf" "bufif0" "bufif1" "cmos" "defparam" "inout" "input"
|
|
5269 "integer" "localparam" "logic" "mailbox" "nand" "nmos" "nor" "not" "notif0"
|
|
5270 "notif1" "or" "output" "parameter" "pmos" "pull0" "pull1" "pullup"
|
|
5271 "rcmos" "real" "realtime" "reg" "rnmos" "rpmos" "rtran" "rtranif0"
|
|
5272 "rtranif1" "semaphore" "time" "tran" "tranif0" "tranif1" "tri" "tri0" "tri1"
|
|
5273 "triand" "trior" "trireg" "wand" "wire" "wor" "xnor" "xor"
|
|
5274 )
|
|
5275 "*Keywords for types used when completing a word in a declaration or parmlist.
|
|
5276 \(eg. integer, real, reg...)")
|
|
5277
|
|
5278 (defvar verilog-cpp-keywords
|
|
5279 '("module" "macromodule" "primitive" "timescale" "define" "ifdef" "ifndef" "else"
|
|
5280 "endif")
|
|
5281 "*Keywords to complete when at first word of a line in declarative scope.
|
|
5282 \(eg. initial, always, begin, assign.)
|
|
5283 The procedures and variables defined within the Verilog program
|
|
5284 will be completed runtime and should not be added to this list.")
|
|
5285
|
|
5286 (defvar verilog-defun-keywords
|
|
5287 (append
|
|
5288 '(
|
|
5289 "always" "always_comb" "always_ff" "always_latch" "assign"
|
|
5290 "begin" "end" "generate" "endgenerate" "module" "endmodule"
|
|
5291 "specify" "endspecify" "function" "endfunction" "initial" "final"
|
|
5292 "task" "endtask" "primitive" "endprimitive"
|
|
5293 )
|
|
5294 verilog-type-keywords)
|
|
5295 "*Keywords to complete when at first word of a line in declarative scope.
|
|
5296 \(eg. initial, always, begin, assign.)
|
|
5297 The procedures and variables defined within the Verilog program
|
|
5298 will be completed runtime and should not be added to this list.")
|
|
5299
|
|
5300 (defvar verilog-block-keywords
|
|
5301 '(
|
|
5302 "begin" "break" "case" "continue" "else" "end" "endfunction"
|
|
5303 "endgenerate" "endinterface" "endpackage" "endspecify" "endtask"
|
|
5304 "for" "fork" "if" "join" "join_any" "join_none" "repeat" "return"
|
|
5305 "while")
|
|
5306 "*Keywords to complete when at first word of a line in behavioral scope.
|
|
5307 \(eg. begin, if, then, else, for, fork.)
|
|
5308 The procedures and variables defined within the Verilog program
|
|
5309 will be completed runtime and should not be added to this list.")
|
|
5310
|
|
5311 (defvar verilog-tf-keywords
|
|
5312 '("begin" "break" "fork" "join" "join_any" "join_none" "case" "end" "endtask" "endfunction" "if" "else" "for" "while" "repeat")
|
|
5313 "*Keywords to complete when at first word of a line in a task or function.
|
|
5314 \(eg. begin, if, then, else, for, fork.)
|
|
5315 The procedures and variables defined within the Verilog program
|
|
5316 will be completed runtime and should not be added to this list.")
|
|
5317
|
|
5318 (defvar verilog-case-keywords
|
|
5319 '("begin" "fork" "join" "join_any" "join_none" "case" "end" "endcase" "if" "else" "for" "repeat")
|
|
5320 "*Keywords to complete when at first word of a line in case scope.
|
|
5321 \(eg. begin, if, then, else, for, fork.)
|
|
5322 The procedures and variables defined within the Verilog program
|
|
5323 will be completed runtime and should not be added to this list.")
|
|
5324
|
|
5325 (defvar verilog-separator-keywords
|
|
5326 '("else" "then" "begin")
|
|
5327 "*Keywords to complete when NOT standing at the first word of a statement.
|
|
5328 \(eg. else, then.)
|
|
5329 Variables and function names defined within the
|
|
5330 Verilog program are completed runtime and should not be added to this list.")
|
|
5331
|
|
5332 (defun verilog-string-diff (str1 str2)
|
|
5333 "Return index of first letter where STR1 and STR2 differs."
|
|
5334 (catch 'done
|
|
5335 (let ((diff 0))
|
|
5336 (while t
|
|
5337 (if (or (> (1+ diff) (length str1))
|
|
5338 (> (1+ diff) (length str2)))
|
|
5339 (throw 'done diff))
|
|
5340 (or (equal (aref str1 diff) (aref str2 diff))
|
|
5341 (throw 'done diff))
|
|
5342 (setq diff (1+ diff))))))
|
|
5343
|
|
5344 ;; Calculate all possible completions for functions if argument is `function',
|
|
5345 ;; completions for procedures if argument is `procedure' or both functions and
|
|
5346 ;; procedures otherwise.
|
|
5347
|
|
5348 (defun verilog-func-completion (type)
|
|
5349 "Build regular expression for module/task/function names.
|
|
5350 TYPE is 'module, 'tf for task or function, or t if unknown."
|
|
5351 (if (string= verilog-str "")
|
|
5352 (setq verilog-str "[a-zA-Z_]"))
|
|
5353 (let ((verilog-str (concat (cond
|
|
5354 ((eq type 'module) "\\<\\(module\\)\\s +")
|
|
5355 ((eq type 'tf) "\\<\\(task\\|function\\)\\s +")
|
|
5356 (t "\\<\\(task\\|function\\|module\\)\\s +"))
|
|
5357 "\\<\\(" verilog-str "[a-zA-Z0-9_.]*\\)\\>"))
|
|
5358 match)
|
|
5359
|
|
5360 (if (not (looking-at verilog-defun-re))
|
|
5361 (verilog-re-search-backward verilog-defun-re nil t))
|
|
5362 (forward-char 1)
|
|
5363
|
|
5364 ;; Search through all reachable functions
|
|
5365 (goto-char (point-min))
|
|
5366 (while (verilog-re-search-forward verilog-str (point-max) t)
|
|
5367 (progn (setq match (buffer-substring (match-beginning 2)
|
|
5368 (match-end 2)))
|
|
5369 (if (or (null verilog-pred)
|
|
5370 (funcall verilog-pred match))
|
|
5371 (setq verilog-all (cons match verilog-all)))))
|
|
5372 (if (match-beginning 0)
|
|
5373 (goto-char (match-beginning 0)))))
|
|
5374
|
|
5375 (defun verilog-get-completion-decl (end)
|
|
5376 "Macro for searching through current declaration (var, type or const)
|
|
5377 for matches of `str' and adding the occurrence tp `all' through point END."
|
|
5378 (let ((re (or (and verilog-indent-declaration-macros
|
|
5379 verilog-declaration-re-2-macro)
|
|
5380 verilog-declaration-re-2-no-macro))
|
|
5381 decl-end match)
|
|
5382 ;; Traverse lines
|
|
5383 (while (and (< (point) end)
|
|
5384 (verilog-re-search-forward re end t))
|
|
5385 ;; Traverse current line
|
|
5386 (setq decl-end (save-excursion (verilog-declaration-end)))
|
|
5387 (while (and (verilog-re-search-forward verilog-symbol-re decl-end t)
|
|
5388 (not (match-end 1)))
|
|
5389 (setq match (buffer-substring (match-beginning 0) (match-end 0)))
|
|
5390 (if (string-match (concat "\\<" verilog-str) match)
|
|
5391 (if (or (null verilog-pred)
|
|
5392 (funcall verilog-pred match))
|
|
5393 (setq verilog-all (cons match verilog-all)))))
|
|
5394 (forward-line 1)
|
|
5395 )
|
|
5396 )
|
|
5397 verilog-all
|
|
5398 )
|
|
5399
|
|
5400 (defun verilog-type-completion ()
|
|
5401 "Calculate all possible completions for types."
|
|
5402 (let ((start (point))
|
|
5403 goon)
|
|
5404 ;; Search for all reachable type declarations
|
|
5405 (while (or (verilog-beg-of-defun)
|
|
5406 (setq goon (not goon)))
|
|
5407 (save-excursion
|
|
5408 (if (and (< start (prog1 (save-excursion (verilog-end-of-defun)
|
|
5409 (point))
|
|
5410 (forward-char 1)))
|
|
5411 (verilog-re-search-forward
|
|
5412 "\\<type\\>\\|\\<\\(begin\\|function\\|procedure\\)\\>"
|
|
5413 start t)
|
|
5414 (not (match-end 1)))
|
|
5415 ;; Check current type declaration
|
|
5416 (verilog-get-completion-decl start))))))
|
|
5417
|
|
5418 (defun verilog-var-completion ()
|
|
5419 "Calculate all possible completions for variables (or constants)."
|
|
5420 (let ((start (point)))
|
|
5421 ;; Search for all reachable var declarations
|
|
5422 (verilog-beg-of-defun)
|
|
5423 (save-excursion
|
|
5424 ;; Check var declarations
|
|
5425 (verilog-get-completion-decl start))))
|
|
5426
|
|
5427 (defun verilog-keyword-completion (keyword-list)
|
|
5428 "Give list of all possible completions of keywords in KEYWORD-LIST."
|
|
5429 (mapcar '(lambda (s)
|
|
5430 (if (string-match (concat "\\<" verilog-str) s)
|
|
5431 (if (or (null verilog-pred)
|
|
5432 (funcall verilog-pred s))
|
|
5433 (setq verilog-all (cons s verilog-all)))))
|
|
5434 keyword-list))
|
|
5435
|
|
5436
|
|
5437 (defun verilog-completion (verilog-str verilog-pred verilog-flag)
|
|
5438 "Function passed to `completing-read', `try-completion' or `all-completions'.
|
|
5439 Called to get completion on VERILOG-STR. If VERILOG-PRED is non-nil, it
|
|
5440 must be a function to be called for every match to check if this should
|
|
5441 really be a match. If VERILOG-FLAG is t, the function returns a list of all
|
|
5442 possible completions. If VERILOG-FLAG is nil it returns a string, the
|
|
5443 longest possible completion, or t if STR is an exact match. If VERILOG-FLAG
|
|
5444 is 'lambda, the function returns t if STR is an exact match, nil
|
|
5445 otherwise."
|
|
5446 (save-excursion
|
|
5447 (let ((verilog-all nil))
|
|
5448 ;; Set buffer to use for searching labels. This should be set
|
|
5449 ;; within functions which use verilog-completions
|
|
5450 (set-buffer verilog-buffer-to-use)
|
|
5451
|
|
5452 ;; Determine what should be completed
|
|
5453 (let ((state (car (verilog-calculate-indent))))
|
|
5454 (cond ((eq state 'defun)
|
|
5455 (save-excursion (verilog-var-completion))
|
|
5456 (verilog-func-completion 'module)
|
|
5457 (verilog-keyword-completion verilog-defun-keywords))
|
|
5458
|
|
5459 ((eq state 'behavioral)
|
|
5460 (save-excursion (verilog-var-completion))
|
|
5461 (verilog-func-completion 'module)
|
|
5462 (verilog-keyword-completion verilog-defun-keywords))
|
|
5463
|
|
5464 ((eq state 'block)
|
|
5465 (save-excursion (verilog-var-completion))
|
|
5466 (verilog-func-completion 'tf)
|
|
5467 (verilog-keyword-completion verilog-block-keywords))
|
|
5468
|
|
5469 ((eq state 'case)
|
|
5470 (save-excursion (verilog-var-completion))
|
|
5471 (verilog-func-completion 'tf)
|
|
5472 (verilog-keyword-completion verilog-case-keywords))
|
|
5473
|
|
5474 ((eq state 'tf)
|
|
5475 (save-excursion (verilog-var-completion))
|
|
5476 (verilog-func-completion 'tf)
|
|
5477 (verilog-keyword-completion verilog-tf-keywords))
|
|
5478
|
|
5479 ((eq state 'cpp)
|
|
5480 (save-excursion (verilog-var-completion))
|
|
5481 (verilog-keyword-completion verilog-cpp-keywords))
|
|
5482
|
|
5483 ((eq state 'cparenexp)
|
|
5484 (save-excursion (verilog-var-completion)))
|
|
5485
|
|
5486 (t;--Anywhere else
|
|
5487 (save-excursion (verilog-var-completion))
|
|
5488 (verilog-func-completion 'both)
|
|
5489 (verilog-keyword-completion verilog-separator-keywords))))
|
|
5490
|
|
5491 ;; Now we have built a list of all matches. Give response to caller
|
|
5492 (verilog-completion-response))))
|
|
5493
|
|
5494 (defun verilog-completion-response ()
|
|
5495 (cond ((or (equal verilog-flag 'lambda) (null verilog-flag))
|
|
5496 ;; This was not called by all-completions
|
|
5497 (if (null verilog-all)
|
|
5498 ;; Return nil if there was no matching label
|
|
5499 nil
|
|
5500 ;; Get longest string common in the labels
|
|
5501 (let* ((elm (cdr verilog-all))
|
|
5502 (match (car verilog-all))
|
|
5503 (min (length match))
|
|
5504 tmp)
|
|
5505 (if (string= match verilog-str)
|
|
5506 ;; Return t if first match was an exact match
|
|
5507 (setq match t)
|
|
5508 (while (not (null elm))
|
|
5509 ;; Find longest common string
|
|
5510 (if (< (setq tmp (verilog-string-diff match (car elm))) min)
|
|
5511 (progn
|
|
5512 (setq min tmp)
|
|
5513 (setq match (substring match 0 min))))
|
|
5514 ;; Terminate with match=t if this is an exact match
|
|
5515 (if (string= (car elm) verilog-str)
|
|
5516 (progn
|
|
5517 (setq match t)
|
|
5518 (setq elm nil))
|
|
5519 (setq elm (cdr elm)))))
|
|
5520 ;; If this is a test just for exact match, return nil ot t
|
|
5521 (if (and (equal verilog-flag 'lambda) (not (equal match 't)))
|
|
5522 nil
|
|
5523 match))))
|
|
5524 ;; If flag is t, this was called by all-completions. Return
|
|
5525 ;; list of all possible completions
|
|
5526 (verilog-flag
|
|
5527 verilog-all)))
|
|
5528
|
|
5529 (defvar verilog-last-word-numb 0)
|
|
5530 (defvar verilog-last-word-shown nil)
|
|
5531 (defvar verilog-last-completions nil)
|
|
5532
|
|
5533 (defun verilog-complete-word ()
|
|
5534 "Complete word at current point.
|
|
5535 \(See also `verilog-toggle-completions', `verilog-type-keywords',
|
|
5536 and `verilog-separator-keywords'.)"
|
|
5537 (interactive)
|
|
5538 (let* ((b (save-excursion (skip-chars-backward "a-zA-Z0-9_") (point)))
|
|
5539 (e (save-excursion (skip-chars-forward "a-zA-Z0-9_") (point)))
|
|
5540 (verilog-str (buffer-substring b e))
|
|
5541 ;; The following variable is used in verilog-completion
|
|
5542 (verilog-buffer-to-use (current-buffer))
|
|
5543 (allcomp (if (and verilog-toggle-completions
|
|
5544 (string= verilog-last-word-shown verilog-str))
|
|
5545 verilog-last-completions
|
|
5546 (all-completions verilog-str 'verilog-completion)))
|
|
5547 (match (if verilog-toggle-completions
|
|
5548 "" (try-completion
|
|
5549 verilog-str (mapcar '(lambda (elm)
|
|
5550 (cons elm 0)) allcomp)))))
|
|
5551 ;; Delete old string
|
|
5552 (delete-region b e)
|
|
5553
|
|
5554 ;; Toggle-completions inserts whole labels
|
|
5555 (if verilog-toggle-completions
|
|
5556 (progn
|
|
5557 ;; Update entry number in list
|
|
5558 (setq verilog-last-completions allcomp
|
|
5559 verilog-last-word-numb
|
|
5560 (if (>= verilog-last-word-numb (1- (length allcomp)))
|
|
5561 0
|
|
5562 (1+ verilog-last-word-numb)))
|
|
5563 (setq verilog-last-word-shown (elt allcomp verilog-last-word-numb))
|
|
5564 ;; Display next match or same string if no match was found
|
|
5565 (if (not (null allcomp))
|
|
5566 (insert "" verilog-last-word-shown)
|
|
5567 (insert "" verilog-str)
|
|
5568 (message "(No match)")))
|
|
5569 ;; The other form of completion does not necessarily do that.
|
|
5570
|
|
5571 ;; Insert match if found, or the original string if no match
|
|
5572 (if (or (null match) (equal match 't))
|
|
5573 (progn (insert "" verilog-str)
|
|
5574 (message "(No match)"))
|
|
5575 (insert "" match))
|
|
5576 ;; Give message about current status of completion
|
|
5577 (cond ((equal match 't)
|
|
5578 (if (not (null (cdr allcomp)))
|
|
5579 (message "(Complete but not unique)")
|
|
5580 (message "(Sole completion)")))
|
|
5581 ;; Display buffer if the current completion didn't help
|
|
5582 ;; on completing the label.
|
|
5583 ((and (not (null (cdr allcomp))) (= (length verilog-str)
|
|
5584 (length match)))
|
|
5585 (with-output-to-temp-buffer "*Completions*"
|
|
5586 (display-completion-list allcomp))
|
|
5587 ;; Wait for a key press. Then delete *Completion* window
|
|
5588 (momentary-string-display "" (point))
|
|
5589 (delete-window (get-buffer-window (get-buffer "*Completions*")))
|
|
5590 )))))
|
|
5591
|
|
5592 (defun verilog-show-completions ()
|
|
5593 "Show all possible completions at current point."
|
|
5594 (interactive)
|
|
5595 (let* ((b (save-excursion (skip-chars-backward "a-zA-Z0-9_") (point)))
|
|
5596 (e (save-excursion (skip-chars-forward "a-zA-Z0-9_") (point)))
|
|
5597 (verilog-str (buffer-substring b e))
|
|
5598 ;; The following variable is used in verilog-completion
|
|
5599 (verilog-buffer-to-use (current-buffer))
|
|
5600 (allcomp (if (and verilog-toggle-completions
|
|
5601 (string= verilog-last-word-shown verilog-str))
|
|
5602 verilog-last-completions
|
|
5603 (all-completions verilog-str 'verilog-completion))))
|
|
5604 ;; Show possible completions in a temporary buffer.
|
|
5605 (with-output-to-temp-buffer "*Completions*"
|
|
5606 (display-completion-list allcomp))
|
|
5607 ;; Wait for a key press. Then delete *Completion* window
|
|
5608 (momentary-string-display "" (point))
|
|
5609 (delete-window (get-buffer-window (get-buffer "*Completions*")))))
|
|
5610
|
|
5611
|
|
5612 (defun verilog-get-default-symbol ()
|
|
5613 "Return symbol around current point as a string."
|
|
5614 (save-excursion
|
|
5615 (buffer-substring (progn
|
|
5616 (skip-chars-backward " \t")
|
|
5617 (skip-chars-backward "a-zA-Z0-9_")
|
|
5618 (point))
|
|
5619 (progn
|
|
5620 (skip-chars-forward "a-zA-Z0-9_")
|
|
5621 (point)))))
|
|
5622
|
|
5623 (defun verilog-build-defun-re (str &optional arg)
|
|
5624 "Return function/task/module starting with STR as regular expression.
|
|
5625 With optional second ARG non-nil, STR is the complete name of the instruction."
|
|
5626 (if arg
|
|
5627 (concat "^\\(function\\|task\\|module\\)[ \t]+\\(" str "\\)\\>")
|
|
5628 (concat "^\\(function\\|task\\|module\\)[ \t]+\\(" str "[a-zA-Z0-9_]*\\)\\>")))
|
|
5629
|
|
5630 (defun verilog-comp-defun (verilog-str verilog-pred verilog-flag)
|
|
5631 "Function passed to `completing-read', `try-completion' or `all-completions'.
|
|
5632 Returns a completion on any function name based on VERILOG-STR prefix. If
|
|
5633 VERILOG-PRED is non-nil, it must be a function to be called for every match
|
|
5634 to check if this should really be a match. If VERILOG-FLAG is t, the
|
|
5635 function returns a list of all possible completions. If it is nil it
|
|
5636 returns a string, the longest possible completion, or t if VERILOG-STR is
|
|
5637 an exact match. If VERILOG-FLAG is 'lambda, the function returns t if
|
|
5638 VERILOG-STR is an exact match, nil otherwise."
|
|
5639 (save-excursion
|
|
5640 (let ((verilog-all nil)
|
|
5641 match)
|
|
5642
|
|
5643 ;; Set buffer to use for searching labels. This should be set
|
|
5644 ;; within functions which use verilog-completions
|
|
5645 (set-buffer verilog-buffer-to-use)
|
|
5646
|
|
5647 (let ((verilog-str verilog-str))
|
|
5648 ;; Build regular expression for functions
|
|
5649 (if (string= verilog-str "")
|
|
5650 (setq verilog-str (verilog-build-defun-re "[a-zA-Z_]"))
|
|
5651 (setq verilog-str (verilog-build-defun-re verilog-str)))
|
|
5652 (goto-char (point-min))
|
|
5653
|
|
5654 ;; Build a list of all possible completions
|
|
5655 (while (verilog-re-search-forward verilog-str nil t)
|
|
5656 (setq match (buffer-substring (match-beginning 2) (match-end 2)))
|
|
5657 (if (or (null verilog-pred)
|
|
5658 (funcall verilog-pred match))
|
|
5659 (setq verilog-all (cons match verilog-all)))))
|
|
5660
|
|
5661 ;; Now we have built a list of all matches. Give response to caller
|
|
5662 (verilog-completion-response))))
|
|
5663
|
|
5664 (defun verilog-goto-defun ()
|
|
5665 "Move to specified Verilog module/task/function.
|
|
5666 The default is a name found in the buffer around point.
|
|
5667 If search fails, other files are checked based on
|
|
5668 `verilog-library-flags'."
|
|
5669 (interactive)
|
|
5670 (let* ((default (verilog-get-default-symbol))
|
|
5671 ;; The following variable is used in verilog-comp-function
|
|
5672 (verilog-buffer-to-use (current-buffer))
|
|
5673 (label (if (not (string= default ""))
|
|
5674 ;; Do completion with default
|
|
5675 (completing-read (concat "Label: (default " default ") ")
|
|
5676 'verilog-comp-defun nil nil "")
|
|
5677 ;; There is no default value. Complete without it
|
|
5678 (completing-read "Label: "
|
|
5679 'verilog-comp-defun nil nil "")))
|
|
5680 pt)
|
|
5681 ;; If there was no response on prompt, use default value
|
|
5682 (if (string= label "")
|
|
5683 (setq label default))
|
|
5684 ;; Goto right place in buffer if label is not an empty string
|
|
5685 (or (string= label "")
|
|
5686 (progn
|
|
5687 (save-excursion
|
|
5688 (goto-char (point-min))
|
|
5689 (setq pt (re-search-forward (verilog-build-defun-re label t) nil t)))
|
|
5690 (when pt
|
|
5691 (goto-char pt)
|
|
5692 (beginning-of-line))
|
|
5693 pt)
|
|
5694 (verilog-goto-defun-file label)
|
|
5695 )))
|
|
5696
|
|
5697 ;; Eliminate compile warning
|
|
5698 (eval-when-compile
|
|
5699 (if (not (boundp 'occur-pos-list))
|
|
5700 (defvar occur-pos-list nil "Backward compatibility occur positions.")))
|
|
5701
|
|
5702 (defun verilog-showscopes ()
|
|
5703 "List all scopes in this module."
|
|
5704 (interactive)
|
|
5705 (let ((buffer (current-buffer))
|
|
5706 (linenum 1)
|
|
5707 (nlines 0)
|
|
5708 (first 1)
|
|
5709 (prevpos (point-min))
|
|
5710 (final-context-start (make-marker))
|
|
5711 (regexp "\\(module\\s-+\\w+\\s-*(\\)\\|\\(\\w+\\s-+\\w+\\s-*(\\)")
|
|
5712 )
|
|
5713 (with-output-to-temp-buffer "*Occur*"
|
|
5714 (save-excursion
|
|
5715 (message (format "Searching for %s ..." regexp))
|
|
5716 ;; Find next match, but give up if prev match was at end of buffer.
|
|
5717 (while (and (not (= prevpos (point-max)))
|
|
5718 (verilog-re-search-forward regexp nil t))
|
|
5719 (goto-char (match-beginning 0))
|
|
5720 (beginning-of-line)
|
|
5721 (save-match-data
|
|
5722 (setq linenum (+ linenum (count-lines prevpos (point)))))
|
|
5723 (setq prevpos (point))
|
|
5724 (goto-char (match-end 0))
|
|
5725 (let* ((start (save-excursion
|
|
5726 (goto-char (match-beginning 0))
|
|
5727 (forward-line (if (< nlines 0) nlines (- nlines)))
|
|
5728 (point)))
|
|
5729 (end (save-excursion
|
|
5730 (goto-char (match-end 0))
|
|
5731 (if (> nlines 0)
|
|
5732 (forward-line (1+ nlines))
|
|
5733 (forward-line 1))
|
|
5734 (point)))
|
|
5735 (tag (format "%3d" linenum))
|
|
5736 (empty (make-string (length tag) ?\ ))
|
|
5737 tem)
|
|
5738 (save-excursion
|
|
5739 (setq tem (make-marker))
|
|
5740 (set-marker tem (point))
|
|
5741 (set-buffer standard-output)
|
|
5742 (setq occur-pos-list (cons tem occur-pos-list))
|
|
5743 (or first (zerop nlines)
|
|
5744 (insert "--------\n"))
|
|
5745 (setq first nil)
|
|
5746 (insert-buffer-substring buffer start end)
|
|
5747 (backward-char (- end start))
|
|
5748 (setq tem (if (< nlines 0) (- nlines) nlines))
|
|
5749 (while (> tem 0)
|
|
5750 (insert empty ?:)
|
|
5751 (forward-line 1)
|
|
5752 (setq tem (1- tem)))
|
|
5753 (let ((this-linenum linenum))
|
|
5754 (set-marker final-context-start
|
|
5755 (+ (point) (- (match-end 0) (match-beginning 0))))
|
|
5756 (while (< (point) final-context-start)
|
|
5757 (if (null tag)
|
|
5758 (setq tag (format "%3d" this-linenum)))
|
|
5759 (insert tag ?:)))))))
|
|
5760 (set-buffer-modified-p nil))))
|
|
5761
|
|
5762
|
|
5763 ;; Highlight helper functions
|
|
5764 (defconst verilog-directive-regexp "\\(translate\\|coverage\\|lint\\)_")
|
|
5765 (defun verilog-within-translate-off ()
|
|
5766 "Return point if within translate-off region, else nil."
|
|
5767 (and (save-excursion
|
|
5768 (re-search-backward
|
|
5769 (concat "//\\s-*.*\\s-*" verilog-directive-regexp "\\(on\\|off\\)\\>")
|
|
5770 nil t))
|
|
5771 (equal "off" (match-string 2))
|
|
5772 (point)))
|
|
5773
|
|
5774 (defun verilog-start-translate-off (limit)
|
|
5775 "Return point before translate-off directive if before LIMIT, else nil."
|
|
5776 (when (re-search-forward
|
|
5777 (concat "//\\s-*.*\\s-*" verilog-directive-regexp "off\\>")
|
|
5778 limit t)
|
|
5779 (match-beginning 0)))
|
|
5780
|
|
5781 (defun verilog-back-to-start-translate-off (limit)
|
|
5782 "Return point before translate-off directive if before LIMIT, else nil."
|
|
5783 (when (re-search-backward
|
|
5784 (concat "//\\s-*.*\\s-*" verilog-directive-regexp "off\\>")
|
|
5785 limit t)
|
|
5786 (match-beginning 0)))
|
|
5787
|
|
5788 (defun verilog-end-translate-off (limit)
|
|
5789 "Return point after translate-on directive if before LIMIT, else nil."
|
|
5790
|
|
5791 (re-search-forward (concat
|
|
5792 "//\\s-*.*\\s-*" verilog-directive-regexp "on\\>") limit t))
|
|
5793
|
|
5794 (defun verilog-match-translate-off (limit)
|
|
5795 "Match a translate-off block, setting `match-data' and returning t, else nil.
|
|
5796 Bound search by LIMIT."
|
|
5797 (when (< (point) limit)
|
|
5798 (let ((start (or (verilog-within-translate-off)
|
|
5799 (verilog-start-translate-off limit)))
|
|
5800 (case-fold-search t))
|
|
5801 (when start
|
|
5802 (let ((end (or (verilog-end-translate-off limit) limit)))
|
|
5803 (set-match-data (list start end))
|
|
5804 (goto-char end))))))
|
|
5805
|
|
5806 (defun verilog-font-lock-match-item (limit)
|
|
5807 "Match, and move over, any declaration item after point.
|
|
5808 Bound search by LIMIT. Adapted from
|
|
5809 `font-lock-match-c-style-declaration-item-and-skip-to-next'."
|
|
5810 (condition-case nil
|
|
5811 (save-restriction
|
|
5812 (narrow-to-region (point-min) limit)
|
|
5813 ;; match item
|
|
5814 (when (looking-at "\\s-*\\([a-zA-Z]\\w*\\)")
|
|
5815 (save-match-data
|
|
5816 (goto-char (match-end 1))
|
|
5817 ;; move to next item
|
|
5818 (if (looking-at "\\(\\s-*,\\)")
|
|
5819 (goto-char (match-end 1))
|
|
5820 (end-of-line) t))))
|
|
5821 (error nil)))
|
|
5822
|
|
5823
|
|
5824 ;; Added by Subbu Meiyappan for Header
|
|
5825
|
|
5826 (defun verilog-header ()
|
|
5827 "Insert a standard Verilog file header."
|
|
5828 (interactive)
|
|
5829 (let ((start (point)))
|
|
5830 (insert "\
|
|
5831 //-----------------------------------------------------------------------------
|
|
5832 // Title : <title>
|
|
5833 // Project : <project>
|
|
5834 //-----------------------------------------------------------------------------
|
|
5835 // File : <filename>
|
|
5836 // Author : <author>
|
|
5837 // Created : <credate>
|
|
5838 // Last modified : <moddate>
|
|
5839 //-----------------------------------------------------------------------------
|
|
5840 // Description :
|
|
5841 // <description>
|
|
5842 //-----------------------------------------------------------------------------
|
|
5843 // Copyright (c) <copydate> by <company> This model is the confidential and
|
|
5844 // proprietary property of <company> and the possession or use of this
|
|
5845 // file requires a written license from <company>.
|
|
5846 //------------------------------------------------------------------------------
|
|
5847 // Modification history :
|
|
5848 // <modhist>
|
|
5849 //-----------------------------------------------------------------------------
|
|
5850
|
|
5851 ")
|
|
5852 (goto-char start)
|
|
5853 (search-forward "<filename>")
|
|
5854 (replace-match (buffer-name) t t)
|
|
5855 (search-forward "<author>") (replace-match "" t t)
|
|
5856 (insert (user-full-name))
|
|
5857 (insert " <" (user-login-name) "@" (system-name) ">")
|
|
5858 (search-forward "<credate>") (replace-match "" t t)
|
|
5859 (insert-date)
|
|
5860 (search-forward "<moddate>") (replace-match "" t t)
|
|
5861 (insert-date)
|
|
5862 (search-forward "<copydate>") (replace-match "" t t)
|
|
5863 (insert-year)
|
|
5864 (search-forward "<modhist>") (replace-match "" t t)
|
|
5865 (insert-date)
|
|
5866 (insert " : created")
|
|
5867 (goto-char start)
|
|
5868 (let (string)
|
|
5869 (setq string (read-string "title: "))
|
|
5870 (search-forward "<title>")
|
|
5871 (replace-match string t t)
|
|
5872 (setq string (read-string "project: " verilog-project))
|
|
5873 (make-variable-buffer-local 'verilog-project)
|
|
5874 (setq verilog-project string)
|
|
5875 (search-forward "<project>")
|
|
5876 (replace-match string t t)
|
|
5877 (setq string (read-string "Company: " verilog-company))
|
|
5878 (make-variable-buffer-local 'verilog-company)
|
|
5879 (setq verilog-company string)
|
|
5880 (search-forward "<company>")
|
|
5881 (replace-match string t t)
|
|
5882 (search-forward "<company>")
|
|
5883 (replace-match string t t)
|
|
5884 (search-forward "<company>")
|
|
5885 (replace-match string t t)
|
|
5886 (search-backward "<description>")
|
|
5887 (replace-match "" t t)
|
|
5888 )))
|
|
5889
|
|
5890 ;; verilog-header Uses the insert-date function
|
|
5891
|
|
5892 (defun insert-date ()
|
|
5893 "Insert date from the system."
|
|
5894 (interactive)
|
|
5895 (let ((timpos))
|
|
5896 (setq timpos (point))
|
|
5897 (if verilog-date-scientific-format
|
|
5898 (shell-command "date \"+@%Y/%m/%d\"" t)
|
|
5899 (shell-command "date \"+@%d.%m.%Y\"" t))
|
|
5900 (search-forward "@")
|
|
5901 (delete-region timpos (point))
|
|
5902 (end-of-line))
|
|
5903 (delete-char 1))
|
|
5904
|
|
5905 (defun insert-year ()
|
|
5906 "Insert year from the system."
|
|
5907 (interactive)
|
|
5908 (let ((timpos))
|
|
5909 (setq timpos (point))
|
|
5910 (shell-command "date \"+@%Y\"" t)
|
|
5911 (search-forward "@")
|
|
5912 (delete-region timpos (point))
|
|
5913 (end-of-line))
|
|
5914 (delete-char 1))
|
|
5915
|
|
5916
|
|
5917 ;;
|
|
5918 ;; Signal list parsing
|
|
5919 ;;
|
|
5920
|
|
5921 ;; Elements of a signal list
|
|
5922 (defsubst verilog-sig-name (sig)
|
|
5923 (car sig))
|
|
5924 (defsubst verilog-sig-bits (sig)
|
|
5925 (nth 1 sig))
|
|
5926 (defsubst verilog-sig-comment (sig)
|
|
5927 (nth 2 sig))
|
|
5928 (defsubst verilog-sig-memory (sig)
|
|
5929 (nth 3 sig))
|
|
5930 (defsubst verilog-sig-enum (sig)
|
|
5931 (nth 4 sig))
|
|
5932 (defsubst verilog-sig-signed (sig)
|
|
5933 (nth 5 sig))
|
|
5934 (defsubst verilog-sig-type (sig)
|
|
5935 (nth 6 sig))
|
|
5936 (defsubst verilog-sig-multidim (sig)
|
|
5937 (nth 7 sig))
|
|
5938 (defsubst verilog-sig-multidim-string (sig)
|
|
5939 (if (verilog-sig-multidim sig)
|
|
5940 (let ((str "") (args (verilog-sig-multidim sig)))
|
|
5941 (while args
|
|
5942 (setq str (concat str (car args)))
|
|
5943 (setq args (cdr args)))
|
|
5944 str)))
|
|
5945 (defsubst verilog-sig-width (sig)
|
|
5946 (verilog-make-width-expression (verilog-sig-bits sig)))
|
|
5947
|
|
5948 (defsubst verilog-alw-get-inputs (sigs)
|
|
5949 (nth 2 sigs))
|
|
5950 (defsubst verilog-alw-get-outputs (sigs)
|
|
5951 (nth 0 sigs))
|
|
5952 (defsubst verilog-alw-get-uses-delayed (sigs)
|
|
5953 (nth 3 sigs))
|
|
5954
|
|
5955 (defun verilog-signals-not-in (in-list not-list)
|
|
5956 "Return list of signals in IN-LIST that aren't also in NOT-LIST,
|
|
5957 and also remove any duplicates in IN-LIST.
|
|
5958 Signals must be in standard (base vector) form."
|
|
5959 (let (out-list)
|
|
5960 (while in-list
|
|
5961 (if (not (or (assoc (car (car in-list)) not-list)
|
|
5962 (assoc (car (car in-list)) out-list)))
|
|
5963 (setq out-list (cons (car in-list) out-list)))
|
|
5964 (setq in-list (cdr in-list)))
|
|
5965 (nreverse out-list)))
|
|
5966 ;;(verilog-signals-not-in '(("A" "") ("B" "") ("DEL" "[2:3]")) '(("DEL" "") ("EXT" "")))
|
|
5967
|
|
5968 (defun verilog-signals-in (in-list other-list)
|
|
5969 "Return list of signals in IN-LIST that are also in OTHER-LIST.
|
|
5970 Signals must be in standard (base vector) form."
|
|
5971 (let (out-list)
|
|
5972 (while in-list
|
|
5973 (if (assoc (car (car in-list)) other-list)
|
|
5974 (setq out-list (cons (car in-list) out-list)))
|
|
5975 (setq in-list (cdr in-list)))
|
|
5976 (nreverse out-list)))
|
|
5977 ;;(verilog-signals-in '(("A" "") ("B" "") ("DEL" "[2:3]")) '(("DEL" "") ("EXT" "")))
|
|
5978
|
|
5979 (defun verilog-signals-memory (in-list)
|
|
5980 "Return list of signals in IN-LIST that are memoried (multidimensional)."
|
|
5981 (let (out-list)
|
|
5982 (while in-list
|
|
5983 (if (nth 3 (car in-list))
|
|
5984 (setq out-list (cons (car in-list) out-list)))
|
|
5985 (setq in-list (cdr in-list)))
|
|
5986 out-list))
|
|
5987 ;;(verilog-signals-memory '(("A" nil nil "[3:0]")) '(("B" nil nil nil)))
|
|
5988
|
|
5989 (defun verilog-signals-sort-compare (a b)
|
|
5990 "Compare signal A and B for sorting."
|
|
5991 (string< (car a) (car b)))
|
|
5992
|
|
5993 (defun verilog-signals-not-params (in-list)
|
|
5994 "Return list of signals in IN-LIST that aren't parameters or numeric constants."
|
|
5995 (let (out-list)
|
|
5996 (while in-list
|
|
5997 (unless (boundp (intern (concat "vh-" (car (car in-list)))))
|
|
5998 (setq out-list (cons (car in-list) out-list)))
|
|
5999 (setq in-list (cdr in-list)))
|
|
6000 (nreverse out-list)))
|
|
6001
|
|
6002 (defun verilog-signals-combine-bus (in-list)
|
|
6003 "Return a list of signals in IN-LIST, with busses combined.
|
|
6004 Duplicate signals are also removed. For example A[2] and A[1] become A[2:1]."
|
|
6005 (let (combo buswarn
|
|
6006 out-list
|
|
6007 sig highbit lowbit ; Temp information about current signal
|
|
6008 sv-name sv-highbit sv-lowbit ; Details about signal we are forming
|
|
6009 sv-comment sv-memory sv-enum sv-signed sv-type sv-multidim sv-busstring
|
|
6010 bus)
|
|
6011 ;; Shove signals so duplicated signals will be adjacent
|
|
6012 (setq in-list (sort in-list `verilog-signals-sort-compare))
|
|
6013 (while in-list
|
|
6014 (setq sig (car in-list))
|
|
6015 ;; No current signal; form from existing details
|
|
6016 (unless sv-name
|
|
6017 (setq sv-name (verilog-sig-name sig)
|
|
6018 sv-highbit nil
|
|
6019 sv-busstring nil
|
|
6020 sv-comment (verilog-sig-comment sig)
|
|
6021 sv-memory (verilog-sig-memory sig)
|
|
6022 sv-enum (verilog-sig-enum sig)
|
|
6023 sv-signed (verilog-sig-signed sig)
|
|
6024 sv-type (verilog-sig-type sig)
|
|
6025 sv-multidim (verilog-sig-multidim sig)
|
|
6026 combo ""
|
|
6027 buswarn ""
|
|
6028 ))
|
|
6029 ;; Extract bus details
|
|
6030 (setq bus (verilog-sig-bits sig))
|
|
6031 (cond ((and bus
|
|
6032 (or (and (string-match "\\[\\([0-9]+\\):\\([0-9]+\\)\\]" bus)
|
|
6033 (setq highbit (string-to-int (match-string 1 bus))
|
|
6034 lowbit (string-to-int (match-string 2 bus))))
|
|
6035 (and (string-match "\\[\\([0-9]+\\)\\]" bus)
|
|
6036 (setq highbit (string-to-int (match-string 1 bus))
|
|
6037 lowbit highbit))))
|
|
6038 ;; Combine bits in bus
|
|
6039 (if sv-highbit
|
|
6040 (setq sv-highbit (max highbit sv-highbit)
|
|
6041 sv-lowbit (min lowbit sv-lowbit))
|
|
6042 (setq sv-highbit highbit
|
|
6043 sv-lowbit lowbit)))
|
|
6044 (bus
|
|
6045 ;; String, probably something like `preproc:0
|
|
6046 (setq sv-busstring bus)))
|
|
6047 ;; Peek ahead to next signal
|
|
6048 (setq in-list (cdr in-list))
|
|
6049 (setq sig (car in-list))
|
|
6050 (cond ((and sig (equal sv-name (verilog-sig-name sig)))
|
|
6051 ;; Combine with this signal
|
|
6052 (when (and sv-busstring (not (equal sv-busstring (verilog-sig-bits sig))))
|
|
6053 (when nil ;; Debugging
|
|
6054 (message (concat "Warning, can't merge into single bus "
|
|
6055 sv-name bus
|
|
6056 ", the AUTOs may be wrong")))
|
|
6057 (setq buswarn ", Couldn't Merge"))
|
|
6058 (if (verilog-sig-comment sig) (setq combo ", ..."))
|
|
6059 (setq sv-memory (or sv-memory (verilog-sig-memory sig))
|
|
6060 sv-enum (or sv-enum (verilog-sig-enum sig))
|
|
6061 sv-signed (or sv-signed (verilog-sig-signed sig))
|
|
6062 sv-type (or sv-type (verilog-sig-type sig))
|
|
6063 sv-multidim (or sv-multidim (verilog-sig-multidim sig))))
|
|
6064 ;; Doesn't match next signal, add to queue, zero in prep for next
|
|
6065 ;; Note sig may also be nil for the last signal in the list
|
|
6066 (t
|
|
6067 (setq out-list
|
|
6068 (cons (list sv-name
|
|
6069 (or sv-busstring
|
|
6070 (if sv-highbit
|
|
6071 (concat "[" (int-to-string sv-highbit) ":" (int-to-string sv-lowbit) "]")))
|
|
6072 (concat sv-comment combo buswarn)
|
|
6073 sv-memory sv-enum sv-signed sv-type sv-multidim)
|
|
6074 out-list)
|
|
6075 sv-name nil)))
|
|
6076 )
|
|
6077 ;;
|
|
6078 out-list))
|
|
6079
|
|
6080 (defun verilog-sig-tieoff (sig &optional no-width)
|
|
6081 "Return tieoff expression for given SIGNAL, with appropriate width.
|
|
6082 Ignore width if optional NO-WIDTH is set."
|
|
6083 (let* ((width (if no-width nil (verilog-sig-width sig))))
|
|
6084 (concat
|
|
6085 (if (and verilog-active-low-regexp
|
|
6086 (string-match verilog-active-low-regexp (verilog-sig-name sig)))
|
|
6087 "~" "")
|
|
6088 (cond ((not width)
|
|
6089 "0")
|
|
6090 ((string-match "^[0-9]+$" width)
|
|
6091 (concat width (if (verilog-sig-signed sig) "'sh0" "'h0")))
|
|
6092 (t
|
|
6093 (concat "{" width "{1'b0}}"))))))
|
|
6094
|
|
6095 ;;
|
|
6096 ;; Port/Wire/Etc Reading
|
|
6097 ;;
|
|
6098
|
|
6099 (defun verilog-read-inst-backward-name ()
|
|
6100 "Internal. Move point back to beginning of inst-name."
|
|
6101 (verilog-backward-open-paren)
|
|
6102 (let (done)
|
|
6103 (while (not done)
|
|
6104 (verilog-re-search-backward-quick "\\()\\|\\b[a-zA-Z0-9`_\$]\\|\\]\\)" nil nil) ; ] isn't word boundary
|
|
6105 (cond ((looking-at ")")
|
|
6106 (verilog-backward-open-paren))
|
|
6107 (t (setq done t)))))
|
|
6108 (while (looking-at "\\]")
|
|
6109 (verilog-backward-open-bracket)
|
|
6110 (verilog-re-search-backward-quick "\\(\\b[a-zA-Z0-9`_\$]\\|\\]\\)" nil nil))
|
|
6111 (skip-chars-backward "a-zA-Z0-9`_$"))
|
|
6112
|
|
6113 (defun verilog-read-inst-module ()
|
|
6114 "Return module_name when point is inside instantiation."
|
|
6115 (save-excursion
|
|
6116 (verilog-read-inst-backward-name)
|
|
6117 ;; Skip over instantiation name
|
|
6118 (verilog-re-search-backward-quick "\\(\\b[a-zA-Z0-9`_\$]\\|)\\)" nil nil) ; ) isn't word boundary
|
|
6119 ;; Check for parameterized instantiations
|
|
6120 (when (looking-at ")")
|
|
6121 (verilog-backward-open-paren)
|
|
6122 (verilog-re-search-backward-quick "\\b[a-zA-Z0-9`_\$]" nil nil))
|
|
6123 (skip-chars-backward "a-zA-Z0-9'_$")
|
|
6124 (looking-at "[a-zA-Z0-9`_\$]+")
|
|
6125 ;; Important: don't use match string, this must work with emacs 19 font-lock on
|
|
6126 (buffer-substring-no-properties (match-beginning 0) (match-end 0))))
|
|
6127
|
|
6128 (defun verilog-read-inst-name ()
|
|
6129 "Return instance_name when point is inside instantiation."
|
|
6130 (save-excursion
|
|
6131 (verilog-read-inst-backward-name)
|
|
6132 (looking-at "[a-zA-Z0-9`_\$]+")
|
|
6133 ;; Important: don't use match string, this must work with emacs 19 font-lock on
|
|
6134 (buffer-substring-no-properties (match-beginning 0) (match-end 0))))
|
|
6135
|
|
6136 (defun verilog-read-module-name ()
|
|
6137 "Return module name when after its ( or ;."
|
|
6138 (save-excursion
|
|
6139 (re-search-backward "[(;]")
|
|
6140 (verilog-re-search-backward-quick "\\b[a-zA-Z0-9`_\$]" nil nil)
|
|
6141 (skip-chars-backward "a-zA-Z0-9`_$")
|
|
6142 (looking-at "[a-zA-Z0-9`_\$]+")
|
|
6143 ;; Important: don't use match string, this must work with emacs 19 font-lock on
|
|
6144 (buffer-substring-no-properties (match-beginning 0) (match-end 0))))
|
|
6145
|
|
6146 (defun verilog-read-auto-params (num-param &optional max-param)
|
|
6147 "Return parameter list inside auto.
|
|
6148 Optional NUM-PARAM and MAX-PARAM check for a specific number of parameters."
|
|
6149 (let ((olist))
|
|
6150 (save-excursion
|
|
6151 ;; /*AUTOPUNT("parameter", "parameter")*/
|
|
6152 (search-backward "(")
|
|
6153 (while (looking-at "(?\\s *\"\\([^\"]*\\)\"\\s *,?")
|
|
6154 (setq olist (cons (match-string 1) olist))
|
|
6155 (goto-char (match-end 0))))
|
|
6156 (or (eq nil num-param)
|
|
6157 (<= num-param (length olist))
|
|
6158 (error "%s: Expected %d parameters" (verilog-point-text) num-param))
|
|
6159 (if (eq max-param nil) (setq max-param num-param))
|
|
6160 (or (eq nil max-param)
|
|
6161 (>= max-param (length olist))
|
|
6162 (error "%s: Expected <= %d parameters" (verilog-point-text) max-param))
|
|
6163 (nreverse olist)))
|
|
6164
|
|
6165 (defun verilog-read-decls ()
|
|
6166 "Compute signal declaration information for the current module at point.
|
|
6167 Return a array of [outputs inouts inputs wire reg assign const]."
|
|
6168 (let ((end-mod-point (or (verilog-get-end-of-defun t) (point-max)))
|
|
6169 (functask 0) (paren 0) (sig-paren 0)
|
|
6170 sigs-in sigs-out sigs-inout sigs-wire sigs-reg sigs-assign sigs-const sigs-gparam
|
|
6171 vec expect-signal keywd newsig rvalue enum io signed typedefed multidim)
|
|
6172 (save-excursion
|
|
6173 (verilog-beg-of-defun)
|
|
6174 (setq sigs-const (verilog-read-auto-constants (point) end-mod-point))
|
|
6175 (while (< (point) end-mod-point)
|
|
6176 ;;(if dbg (setq dbg (cons (format "Pt %s Vec %s Kwd'%s'\n" (point) vec keywd) dbg)))
|
|
6177 (cond
|
|
6178 ((looking-at "//")
|
|
6179 (if (looking-at "[^\n]*synopsys\\s +enum\\s +\\([a-zA-Z0-9_]+\\)")
|
|
6180 (setq enum (match-string 1)))
|
|
6181 (search-forward "\n"))
|
|
6182 ((looking-at "/\\*")
|
|
6183 (forward-char 2)
|
|
6184 (if (looking-at "[^*]*synopsys\\s +enum\\s +\\([a-zA-Z0-9_]+\\)")
|
|
6185 (setq enum (match-string 1)))
|
|
6186 (or (search-forward "*/")
|
|
6187 (error "%s: Unmatched /* */, at char %d" (verilog-point-text) (point))))
|
|
6188 ((looking-at "(\\*")
|
|
6189 (forward-char 2)
|
|
6190 (or (looking-at "\\s-*)") ; It's a "always @ (*)"
|
|
6191 (search-forward "*)")
|
|
6192 (error "%s: Unmatched (* *), at char %d" (verilog-point-text) (point))))
|
|
6193 ((eq ?\" (following-char))
|
|
6194 (or (re-search-forward "[^\\]\"" nil t) ;; don't forward-char first, since we look for a non backslash first
|
|
6195 (error "%s: Unmatched quotes, at char %d" (verilog-point-text) (point))))
|
|
6196 ((eq ?\; (following-char))
|
|
6197 (setq vec nil io nil expect-signal nil newsig nil paren 0 rvalue nil)
|
|
6198 (forward-char 1))
|
|
6199 ((eq ?= (following-char))
|
|
6200 (setq rvalue t newsig nil)
|
|
6201 (forward-char 1))
|
|
6202 ((and (or rvalue sig-paren)
|
|
6203 (cond ((and (eq ?, (following-char))
|
|
6204 (eq paren sig-paren))
|
|
6205 (setq rvalue nil)
|
|
6206 (forward-char 1)
|
|
6207 t)
|
|
6208 ;; ,'s can occur inside {} & funcs
|
|
6209 ((looking-at "[{(]")
|
|
6210 (setq paren (1+ paren))
|
|
6211 (forward-char 1)
|
|
6212 t)
|
|
6213 ((looking-at "[})]")
|
|
6214 (setq paren (1- paren))
|
|
6215 (forward-char 1)
|
|
6216 (when (< paren sig-paren)
|
|
6217 (setq expect-signal nil)) ; ) that ends variables inside v2k arg list
|
|
6218 t)
|
|
6219 )))
|
|
6220 ((looking-at "\\s-*\\(\\[[^]]+\\]\\)")
|
|
6221 (goto-char (match-end 0))
|
|
6222 (cond (newsig ; Memory, not just width. Patch last signal added's memory (nth 3)
|
|
6223 (setcar (cdr (cdr (cdr newsig))) (match-string 1)))
|
|
6224 (vec ;; Multidimensional
|
|
6225 (setq multidim (cons vec multidim))
|
|
6226 (setq vec (verilog-string-replace-matches
|
|
6227 "\\s-+" "" nil nil (match-string 1))))
|
|
6228 (t ;; Bit width
|
|
6229 (setq vec (verilog-string-replace-matches
|
|
6230 "\\s-+" "" nil nil (match-string 1))))))
|
|
6231 ;; Normal or escaped identifier -- note we remember the \ if escaped
|
|
6232 ((looking-at "\\s-*\\([a-zA-Z0-9`_$]+\\|\\\\[^ \t\n\f]+\\)")
|
|
6233 (goto-char (match-end 0))
|
|
6234 (setq keywd (match-string 1))
|
|
6235 (when (string-match "^\\\\" keywd)
|
|
6236 (setq keywd (concat keywd " "))) ;; Escaped ID needs space at end
|
|
6237 (cond ((equal keywd "input")
|
|
6238 (setq vec nil enum nil rvalue nil newsig nil signed nil typedefed nil multidim nil sig-paren paren
|
|
6239 expect-signal 'sigs-in io t))
|
|
6240 ((equal keywd "output")
|
|
6241 (setq vec nil enum nil rvalue nil newsig nil signed nil typedefed nil multidim nil sig-paren paren
|
|
6242 expect-signal 'sigs-out io t))
|
|
6243 ((equal keywd "inout")
|
|
6244 (setq vec nil enum nil rvalue nil newsig nil signed nil typedefed nil multidim nil sig-paren paren
|
|
6245 expect-signal 'sigs-inout io t))
|
|
6246 ((or (equal keywd "wire")
|
|
6247 (equal keywd "tri")
|
|
6248 (equal keywd "tri0")
|
|
6249 (equal keywd "tri1"))
|
|
6250 (unless io (setq vec nil enum nil rvalue nil signed nil typedefed nil multidim nil sig-paren paren
|
|
6251 expect-signal 'sigs-wire)))
|
|
6252 ((or (equal keywd "reg")
|
|
6253 (equal keywd "trireg"))
|
|
6254 (unless io (setq vec nil enum nil rvalue nil signed nil typedefed nil multidim nil sig-paren paren
|
|
6255 expect-signal 'sigs-reg)))
|
|
6256 ((equal keywd "assign")
|
|
6257 (setq vec nil enum nil rvalue nil signed nil typedefed nil multidim nil sig-paren paren
|
|
6258 expect-signal 'sigs-assign))
|
|
6259 ((or (equal keywd "supply0")
|
|
6260 (equal keywd "supply1")
|
|
6261 (equal keywd "supply")
|
|
6262 (equal keywd "localparam"))
|
|
6263 (unless io (setq vec nil enum nil rvalue nil signed nil typedefed nil multidim nil sig-paren paren
|
|
6264 expect-signal 'sigs-const)))
|
|
6265 ((or (equal keywd "parameter"))
|
|
6266 (unless io (setq vec nil enum nil rvalue nil signed nil typedefed nil multidim nil sig-paren paren
|
|
6267 expect-signal 'sigs-gparam)))
|
|
6268 ((equal keywd "signed")
|
|
6269 (setq signed "signed"))
|
|
6270 ((or (equal keywd "function")
|
|
6271 (equal keywd "task"))
|
|
6272 (setq functask (1+ functask)))
|
|
6273 ((or (equal keywd "endfunction")
|
|
6274 (equal keywd "endtask"))
|
|
6275 (setq functask (1- functask)))
|
|
6276 ((or (equal keywd "`ifdef")
|
|
6277 (equal keywd "`ifndef"))
|
|
6278 (setq rvalue t))
|
|
6279 ((verilog-typedef-name-p keywd)
|
|
6280 (setq typedefed keywd))
|
|
6281 ((and expect-signal
|
|
6282 (eq functask 0)
|
|
6283 (not rvalue)
|
|
6284 (eq paren sig-paren)
|
|
6285 (not (member keywd verilog-keywords)))
|
|
6286 ;; Add new signal to expect-signal's variable
|
|
6287 (setq newsig (list keywd vec nil nil enum signed typedefed multidim))
|
|
6288 (set expect-signal (cons newsig
|
|
6289 (symbol-value expect-signal))))))
|
|
6290 (t
|
|
6291 (forward-char 1)))
|
|
6292 (skip-syntax-forward " "))
|
|
6293 ;; Return arguments
|
|
6294 (vector (nreverse sigs-out)
|
|
6295 (nreverse sigs-inout)
|
|
6296 (nreverse sigs-in)
|
|
6297 (nreverse sigs-wire)
|
|
6298 (nreverse sigs-reg)
|
|
6299 (nreverse sigs-assign)
|
|
6300 (nreverse sigs-const)
|
|
6301 (nreverse sigs-gparam)
|
|
6302 ))))
|
|
6303
|
|
6304 (defvar sigs-in nil) ; Prevent compile warning
|
|
6305 (defvar sigs-inout nil) ; Prevent compile warning
|
|
6306 (defvar sigs-out nil) ; Prevent compile warning
|
|
6307
|
|
6308 (defun verilog-read-sub-decls-sig (submodi comment port sig vec multidim)
|
|
6309 "For verilog-read-sub-decls-line, add a signal."
|
|
6310 (let (portdata)
|
|
6311 (when sig
|
|
6312 (setq port (verilog-symbol-detick-denumber port))
|
|
6313 (setq sig (verilog-symbol-detick-denumber sig))
|
|
6314 (if sig (setq sig (verilog-string-replace-matches "^[---+~!|&]+" "" nil nil sig)))
|
|
6315 (if vec (setq vec (verilog-symbol-detick-denumber vec)))
|
|
6316 (if multidim (setq multidim (mapcar `verilog-symbol-detick-denumber multidim)))
|
|
6317 (unless (or (not sig)
|
|
6318 (equal sig "")) ;; Ignore .foo(1'b1) assignments
|
|
6319 (cond ((setq portdata (assoc port (verilog-modi-get-inouts submodi)))
|
|
6320 (setq sigs-inout (cons (list sig vec (concat "To/From " comment) nil nil
|
|
6321 (verilog-sig-signed portdata)
|
|
6322 (verilog-sig-type portdata)
|
|
6323 multidim)
|
|
6324 sigs-inout)))
|
|
6325 ((setq portdata (assoc port (verilog-modi-get-outputs submodi)))
|
|
6326 (setq sigs-out (cons (list sig vec (concat "From " comment) nil nil
|
|
6327 (verilog-sig-signed portdata)
|
|
6328 (verilog-sig-type portdata)
|
|
6329 multidim)
|
|
6330 sigs-out)))
|
|
6331 ((setq portdata (assoc port (verilog-modi-get-inputs submodi)))
|
|
6332 (setq sigs-in (cons (list sig vec (concat "To " comment) nil nil
|
|
6333 (verilog-sig-signed portdata)
|
|
6334 (verilog-sig-type portdata)
|
|
6335 multidim)
|
|
6336 sigs-in)))
|
|
6337 ;; (t -- warning pin isn't defined.) ; Leave for lint tool
|
|
6338 )))))
|
|
6339
|
|
6340 (defun verilog-read-sub-decls-line (submodi comment)
|
|
6341 "For read-sub-decls, read lines of port defs until none match anymore.
|
|
6342 Return the list of signals found, using submodi to look up each port."
|
|
6343 (let (done port sig vec multidim)
|
|
6344 (save-excursion
|
|
6345 (forward-line 1)
|
|
6346 (while (not done)
|
|
6347 ;; Get port name
|
|
6348 (cond ((looking-at "\\s-*\\.\\s-*\\([a-zA-Z0-9`_$]*\\)\\s-*(\\s-*")
|
|
6349 (setq port (match-string 1))
|
|
6350 (goto-char (match-end 0)))
|
|
6351 ((looking-at "\\s-*\\.\\s-*\\(\\\\[^ \t\n\f]*\\)\\s-*(\\s-*")
|
|
6352 (setq port (concat (match-string 1) " ")) ;; escaped id's need trailing space
|
|
6353 (goto-char (match-end 0)))
|
|
6354 ((looking-at "\\s-*\\.[^(]*(")
|
|
6355 (setq port nil) ;; skip this line
|
|
6356 (goto-char (match-end 0)))
|
|
6357 (t
|
|
6358 (setq port nil done t))) ;; Unknown, ignore rest of line
|
|
6359 ;; Get signal name
|
|
6360 (when port
|
|
6361 (setq multidim nil)
|
|
6362 (cond ((looking-at "\\(\\\\[^ \t\n\f]*\\)\\s-*)")
|
|
6363 (setq sig (concat (match-string 1) " ") ;; escaped id's need trailing space
|
|
6364 vec nil))
|
|
6365 ; We intentionally ignore (non-escaped) signals with .s in them
|
|
6366 ; this prevents AUTOWIRE etc from noticing hierarchical sigs.
|
|
6367 ((looking-at "\\([^[({).]*\\)\\s-*)")
|
|
6368 (setq sig (verilog-string-remove-spaces (match-string 1))
|
|
6369 vec nil))
|
|
6370 ((looking-at "\\([^[({).]*\\)\\s-*\\(\\[[^]]+\\]\\)\\s-*)")
|
|
6371 (setq sig (verilog-string-remove-spaces (match-string 1))
|
|
6372 vec (match-string 2)))
|
|
6373 ((looking-at "\\([^[({).]*\\)\\s-*/\\*\\(\\[[^*]+\\]\\)\\*/\\s-*)")
|
|
6374 (setq sig (verilog-string-remove-spaces (match-string 1))
|
|
6375 vec nil)
|
|
6376 (let ((parse (match-string 2)))
|
|
6377 (while (string-match "^\\(\\[[^]]+\\]\\)\\(.*\\)$" parse)
|
|
6378 (when vec (setq multidim (cons vec multidim)))
|
|
6379 (setq vec (match-string 1 parse))
|
|
6380 (setq parse (match-string 2 parse)))))
|
|
6381 ((looking-at "{\\(.*\\)}.*\\s-*)")
|
|
6382 (let ((mlst (split-string (match-string 1) ","))
|
|
6383 mstr)
|
|
6384 (while (setq mstr (pop mlst))
|
|
6385 ;;(unless noninteractive (message "sig: %s " mstr))
|
|
6386 (cond
|
|
6387 ((string-match "\\(['`a-zA-Z0-9_$]+\\)\\s-*$" mstr)
|
|
6388 (setq sig (verilog-string-remove-spaces (match-string 1 mstr))
|
|
6389 vec nil)
|
|
6390 ;;(unless noninteractive (message "concat sig1: %s %s" mstr (match-string 1 mstr)))
|
|
6391 )
|
|
6392 ((string-match "\\([^[({).]+\\)\\s-*\\(\\[[^]]+\\]\\)\\s-*" mstr)
|
|
6393 (setq sig (verilog-string-remove-spaces (match-string 1 mstr))
|
|
6394 vec (match-string 2 mstr))
|
|
6395 ;;(unless noninteractive (message "concat sig2: '%s' '%s' '%s'" mstr (match-string 1 mstr) (match-string 2 mstr)))
|
|
6396 )
|
|
6397 (t
|
|
6398 (setq sig nil)))
|
|
6399 ;; Process signals
|
|
6400 (verilog-read-sub-decls-sig submodi comment port sig vec multidim))))
|
|
6401 (t
|
|
6402 (setq sig nil)))
|
|
6403 ;; Process signals
|
|
6404 (verilog-read-sub-decls-sig submodi comment port sig vec multidim))
|
|
6405 ;;
|
|
6406 (forward-line 1)))))
|
|
6407
|
|
6408 (defun verilog-read-sub-decls ()
|
|
6409 "Internally parse signals going to modules under this module.
|
|
6410 Return a array of [ outputs inouts inputs ] signals for modules that are
|
|
6411 instantiated in this module. For example if declare A A (.B(SIG)) and SIG
|
|
6412 is a output, then SIG will be included in the list.
|
|
6413
|
|
6414 This only works on instantiations created with /*AUTOINST*/ converted by
|
|
6415 \\[verilog-auto-inst]. Otherwise, it would have to read in the whole
|
|
6416 component library to determine connectivity of the design.
|
|
6417
|
|
6418 One work around for this problem is to manually create // Inputs and //
|
|
6419 Outputs comments above subcell signals, for example:
|
|
6420
|
|
6421 module1 instance1x (
|
|
6422 // Outputs
|
|
6423 .out (out),
|
|
6424 // Inputs
|
|
6425 .in (in));"
|
|
6426 (save-excursion
|
|
6427 (let ((end-mod-point (verilog-get-end-of-defun t))
|
|
6428 st-point end-inst-point
|
|
6429 ;; below 3 modified by verilog-read-sub-decls-line
|
|
6430 sigs-out sigs-inout sigs-in)
|
|
6431 (verilog-beg-of-defun)
|
|
6432 (while (re-search-forward "\\(/\\*AUTOINST\\*/\\|\\.\\*\\)" end-mod-point t)
|
|
6433 (save-excursion
|
|
6434 (goto-char (match-beginning 0))
|
|
6435 (unless (verilog-inside-comment-p)
|
|
6436 ;; Attempt to snarf a comment
|
|
6437 (let* ((submod (verilog-read-inst-module))
|
|
6438 (inst (verilog-read-inst-name))
|
|
6439 (comment (concat inst " of " submod ".v")) submodi)
|
|
6440 (when (setq submodi (verilog-modi-lookup submod t))
|
|
6441 ;; This could have used a list created by verilog-auto-inst
|
|
6442 ;; However I want it to be runnable even on user's manually added signals
|
|
6443 (verilog-backward-open-paren)
|
|
6444 (setq end-inst-point (save-excursion (forward-sexp 1) (point))
|
|
6445 st-point (point))
|
|
6446 (while (re-search-forward "\\s *(?\\s *// Outputs" end-inst-point t)
|
|
6447 (verilog-read-sub-decls-line submodi comment)) ;; Modifies sigs-out
|
|
6448 (goto-char st-point)
|
|
6449 (while (re-search-forward "\\s *// Inouts" end-inst-point t)
|
|
6450 (verilog-read-sub-decls-line submodi comment)) ;; Modifies sigs-inout
|
|
6451 (goto-char st-point)
|
|
6452 (while (re-search-forward "\\s *// Inputs" end-inst-point t)
|
|
6453 (verilog-read-sub-decls-line submodi comment)) ;; Modifies sigs-in
|
|
6454 )))))
|
|
6455 ;; Combine duplicate bits
|
|
6456 ;;(setq rr (vector sigs-out sigs-inout sigs-in))
|
|
6457 (vector (verilog-signals-combine-bus (nreverse sigs-out))
|
|
6458 (verilog-signals-combine-bus (nreverse sigs-inout))
|
|
6459 (verilog-signals-combine-bus (nreverse sigs-in))))))
|
|
6460
|
|
6461 (defun verilog-read-inst-pins ()
|
|
6462 "Return a array of [ pins ] for the current instantiation at point.
|
|
6463 For example if declare A A (.B(SIG)) then B will be included in the list."
|
|
6464 (save-excursion
|
|
6465 (let ((end-mod-point (point)) ;; presume at /*AUTOINST*/ point
|
|
6466 pins pin)
|
|
6467 (verilog-backward-open-paren)
|
|
6468 (while (re-search-forward "\\.\\([^(,) \t\n\f]*\\)\\s-*" end-mod-point t)
|
|
6469 (setq pin (match-string 1))
|
|
6470 (unless (verilog-inside-comment-p)
|
|
6471 (setq pins (cons (list pin) pins))
|
|
6472 (when (looking-at "(")
|
|
6473 (forward-sexp 1))))
|
|
6474 (vector pins))))
|
|
6475
|
|
6476 (defun verilog-read-arg-pins ()
|
|
6477 "Return a array of [ pins ] for the current argument declaration at point."
|
|
6478 (save-excursion
|
|
6479 (let ((end-mod-point (point)) ;; presume at /*AUTOARG*/ point
|
|
6480 pins pin)
|
|
6481 (verilog-backward-open-paren)
|
|
6482 (while (re-search-forward "\\([a-zA-Z0-9$_.%`]+\\)" end-mod-point t)
|
|
6483 (setq pin (match-string 1))
|
|
6484 (unless (verilog-inside-comment-p)
|
|
6485 (setq pins (cons (list pin) pins))))
|
|
6486 (vector pins))))
|
|
6487
|
|
6488 (defun verilog-read-auto-constants (beg end-mod-point)
|
|
6489 "Return a list of AUTO_CONSTANTs used in the region from BEG to END-MOD-POINT."
|
|
6490 ;; Insert new
|
|
6491 (save-excursion
|
|
6492 (let (sig-list tpl-end-pt)
|
|
6493 (goto-char beg)
|
|
6494 (while (re-search-forward "\\<AUTO_CONSTANT" end-mod-point t)
|
|
6495 (if (not (looking-at "\\s *("))
|
|
6496 (error "%s: Missing () after AUTO_CONSTANT" (verilog-point-text)))
|
|
6497 (search-forward "(" end-mod-point)
|
|
6498 (setq tpl-end-pt (save-excursion
|
|
6499 (backward-char 1)
|
|
6500 (forward-sexp 1) ;; Moves to paren that closes argdecl's
|
|
6501 (backward-char 1)
|
|
6502 (point)))
|
|
6503 (while (re-search-forward "\\s-*\\([\"a-zA-Z0-9$_.%`]+\\)\\s-*,*" tpl-end-pt t)
|
|
6504 (setq sig-list (cons (list (match-string 1) nil nil) sig-list))))
|
|
6505 sig-list)))
|
|
6506
|
|
6507 (defun verilog-read-auto-lisp (start end)
|
|
6508 "Look for and evaluate a AUTO_LISP between START and END."
|
|
6509 (save-excursion
|
|
6510 (goto-char start)
|
|
6511 (while (re-search-forward "\\<AUTO_LISP(" end t)
|
|
6512 (backward-char)
|
|
6513 (let* ((beg-pt (prog1 (point)
|
|
6514 (forward-sexp 1))) ;; Closing paren
|
|
6515 (end-pt (point)))
|
|
6516 (eval-region beg-pt end-pt nil)))))
|
|
6517
|
|
6518 (eval-when-compile
|
|
6519 ;; These are passed in a let, not global
|
|
6520 (if (not (boundp 'sigs-in))
|
|
6521 (defvar sigs-in nil) (defvar sigs-out nil)
|
|
6522 (defvar got-sig nil) (defvar got-rvalue nil) (defvar uses-delayed nil)))
|
|
6523
|
|
6524 (defun verilog-read-always-signals-recurse
|
|
6525 (exit-keywd rvalue ignore-next)
|
|
6526 "Recursive routine for parentheses/bracket matching.
|
|
6527 EXIT-KEYWD is expression to stop at, nil if top level.
|
|
6528 RVALUE is true if at right hand side of equal.
|
|
6529 IGNORE-NEXT is true to ignore next token, fake from inside case statement."
|
|
6530 (let* ((semi-rvalue (equal "endcase" exit-keywd)) ;; true if after a ; we are looking for rvalue
|
|
6531 keywd last-keywd sig-tolk sig-last-tolk gotend got-sig got-rvalue end-else-check)
|
|
6532 ;;(if dbg (setq dbg (concat dbg (format "Recursion %S %S %S\n" exit-keywd rvalue ignore-next))))
|
|
6533 (while (not (or (eobp) gotend))
|
|
6534 (cond
|
|
6535 ((looking-at "//")
|
|
6536 (search-forward "\n"))
|
|
6537 ((looking-at "/\\*")
|
|
6538 (or (search-forward "*/")
|
|
6539 (error "%s: Unmatched /* */, at char %d" (verilog-point-text) (point))))
|
|
6540 ((looking-at "(\\*")
|
|
6541 (or (looking-at "(\\*\\s-*)") ; It's a "always @ (*)"
|
|
6542 (search-forward "*)")
|
|
6543 (error "%s: Unmatched (* *), at char %d" (verilog-point-text) (point))))
|
|
6544 (t (setq keywd (buffer-substring-no-properties
|
|
6545 (point)
|
|
6546 (save-excursion (when (eq 0 (skip-chars-forward "a-zA-Z0-9$_.%`"))
|
|
6547 (forward-char 1))
|
|
6548 (point)))
|
|
6549 sig-last-tolk sig-tolk
|
|
6550 sig-tolk nil)
|
|
6551 ;;(if dbg (setq dbg (concat dbg (format "\tPt=%S %S\trv=%S in=%S ee=%S\n" (point) keywd rvalue ignore-next end-else-check))))
|
|
6552 (cond
|
|
6553 ((equal keywd "\"")
|
|
6554 (or (re-search-forward "[^\\]\"" nil t)
|
|
6555 (error "%s: Unmatched quotes, at char %d" (verilog-point-text) (point))))
|
|
6556 ;; else at top level loop, keep parsing
|
|
6557 ((and end-else-check (equal keywd "else"))
|
|
6558 ;;(if dbg (setq dbg (concat dbg (format "\tif-check-else %s\n" keywd))))
|
|
6559 ;; no forward movement, want to see else in lower loop
|
|
6560 (setq end-else-check nil))
|
|
6561 ;; End at top level loop
|
|
6562 ((and end-else-check (looking-at "[^ \t\n\f]"))
|
|
6563 ;;(if dbg (setq dbg (concat dbg (format "\tif-check-else-other %s\n" keywd))))
|
|
6564 (setq gotend t))
|
|
6565 ;; Final statement?
|
|
6566 ((and exit-keywd (equal keywd exit-keywd))
|
|
6567 (setq gotend t)
|
|
6568 (forward-char (length keywd)))
|
|
6569 ;; Standard tokens...
|
|
6570 ((equal keywd ";")
|
|
6571 (setq ignore-next nil rvalue semi-rvalue)
|
|
6572 ;; Final statement at top level loop?
|
|
6573 (when (not exit-keywd)
|
|
6574 ;;(if dbg (setq dbg (concat dbg (format "\ttop-end-check %s\n" keywd))))
|
|
6575 (setq end-else-check t))
|
|
6576 (forward-char 1))
|
|
6577 ((equal keywd "'")
|
|
6578 (if (looking-at "'s?[hdxbo][0-9a-fA-F_xz? \t]*")
|
|
6579 (goto-char (match-end 0))
|
|
6580 (forward-char 1)))
|
|
6581 ((equal keywd ":") ;; Case statement, begin/end label, x?y:z
|
|
6582 (cond ((equal "endcase" exit-keywd) ;; case x: y=z; statement next
|
|
6583 (setq ignore-next nil rvalue nil))
|
|
6584 ((equal "?" exit-keywd) ;; x?y:z rvalue
|
|
6585 ) ;; NOP
|
|
6586 (got-sig ;; label: statement
|
|
6587 (setq ignore-next nil rvalue semi-rvalue got-sig nil))
|
|
6588 ((not rvalue) ;; begin label
|
|
6589 (setq ignore-next t rvalue nil)))
|
|
6590 (forward-char 1))
|
|
6591 ((equal keywd "=")
|
|
6592 (if (eq (char-before) ?< )
|
|
6593 (setq uses-delayed 1))
|
|
6594 (setq ignore-next nil rvalue t)
|
|
6595 (forward-char 1))
|
|
6596 ((equal keywd "?")
|
|
6597 (forward-char 1)
|
|
6598 (verilog-read-always-signals-recurse ":" rvalue nil))
|
|
6599 ((equal keywd "[")
|
|
6600 (forward-char 1)
|
|
6601 (verilog-read-always-signals-recurse "]" t nil))
|
|
6602 ((equal keywd "(")
|
|
6603 (forward-char 1)
|
|
6604 (cond (sig-last-tolk ;; Function call; zap last signal
|
|
6605 (setq got-sig nil)))
|
|
6606 (cond ((equal last-keywd "for")
|
|
6607 (verilog-read-always-signals-recurse ";" nil nil)
|
|
6608 (verilog-read-always-signals-recurse ";" t nil)
|
|
6609 (verilog-read-always-signals-recurse ")" nil nil))
|
|
6610 (t (verilog-read-always-signals-recurse ")" t nil))))
|
|
6611 ((equal keywd "begin")
|
|
6612 (skip-syntax-forward "w_")
|
|
6613 (verilog-read-always-signals-recurse "end" nil nil)
|
|
6614 ;;(if dbg (setq dbg (concat dbg (format "\tgot-end %s\n" exit-keywd))))
|
|
6615 (setq ignore-next nil rvalue semi-rvalue)
|
|
6616 (if (not exit-keywd) (setq end-else-check t)))
|
|
6617 ((or (equal keywd "case")
|
|
6618 (equal keywd "casex")
|
|
6619 (equal keywd "casez"))
|
|
6620 (skip-syntax-forward "w_")
|
|
6621 (verilog-read-always-signals-recurse "endcase" t nil)
|
|
6622 (setq ignore-next nil rvalue semi-rvalue)
|
|
6623 (if (not exit-keywd) (setq gotend t))) ;; top level begin/end
|
|
6624 ((string-match "^[$`a-zA-Z_]" keywd) ;; not exactly word constituent
|
|
6625 (cond ((or (equal keywd "`ifdef")
|
|
6626 (equal keywd "`ifndef"))
|
|
6627 (setq ignore-next t))
|
|
6628 ((or ignore-next
|
|
6629 (member keywd verilog-keywords)
|
|
6630 (string-match "^\\$" keywd)) ;; PLI task
|
|
6631 (setq ignore-next nil))
|
|
6632 (t
|
|
6633 (setq keywd (verilog-symbol-detick-denumber keywd))
|
|
6634 (when got-sig
|
|
6635 (if got-rvalue (setq sigs-in (cons got-sig sigs-in))
|
|
6636 (setq sigs-out (cons got-sig sigs-out)))
|
|
6637 ;;(if dbg (setq dbg (concat dbg (format "\t\tgot-sig=%S rv=%S\n" got-sig got-rvalue))))
|
|
6638 )
|
|
6639 (setq got-rvalue rvalue
|
|
6640 got-sig (if (or (not keywd)
|
|
6641 (assoc keywd (if got-rvalue sigs-in sigs-out)))
|
|
6642 nil (list keywd nil nil))
|
|
6643 sig-tolk t)))
|
|
6644 (skip-chars-forward "a-zA-Z0-9$_.%`"))
|
|
6645 (t
|
|
6646 (forward-char 1)))
|
|
6647 ;; End of non-comment token
|
|
6648 (setq last-keywd keywd)
|
|
6649 ))
|
|
6650 (skip-syntax-forward " "))
|
|
6651 ;; Append the final pending signal
|
|
6652 (when got-sig
|
|
6653 (if got-rvalue (setq sigs-in (cons got-sig sigs-in))
|
|
6654 (setq sigs-out (cons got-sig sigs-out)))
|
|
6655 ;;(if dbg (setq dbg (concat dbg (format "\t\tgot-sig=%S rv=%S\n" got-sig got-rvalue))))
|
|
6656 (setq got-sig nil))
|
|
6657 ;;(if dbg (setq dbg (concat dbg (format "ENDRecursion %s\n" exit-keywd))))
|
|
6658 ))
|
|
6659
|
|
6660 (defun verilog-read-always-signals ()
|
|
6661 "Parse always block at point and return list of (outputs inout inputs)."
|
|
6662 ;; Insert new
|
|
6663 (save-excursion
|
|
6664 (let* (;;(dbg "")
|
|
6665 sigs-in sigs-out
|
|
6666 uses-delayed) ;; Found signal/rvalue; push if not function
|
|
6667 (search-forward ")")
|
|
6668 (verilog-read-always-signals-recurse nil nil nil)
|
|
6669 ;;(if dbg (save-excursion (set-buffer (get-buffer-create "*vl-dbg*")) (delete-region (point-min) (point-max)) (insert dbg) (setq dbg "")))
|
|
6670 ;; Return what was found
|
|
6671 (list sigs-out nil sigs-in uses-delayed))))
|
|
6672
|
|
6673 (defun verilog-read-instants ()
|
|
6674 "Parse module at point and return list of ( ( file instance ) ... )."
|
|
6675 (verilog-beg-of-defun)
|
|
6676 (let* ((end-mod-point (verilog-get-end-of-defun t))
|
|
6677 (state nil)
|
|
6678 (instants-list nil))
|
|
6679 (save-excursion
|
|
6680 (while (< (point) end-mod-point)
|
|
6681 ;; Stay at level 0, no comments
|
|
6682 (while (progn
|
|
6683 (setq state (parse-partial-sexp (point) end-mod-point 0 t nil))
|
|
6684 (or (> (car state) 0) ; in parens
|
|
6685 (nth 5 state) ; comment
|
|
6686 ))
|
|
6687 (forward-line 1))
|
|
6688 (beginning-of-line)
|
|
6689 (if (looking-at "^\\s-*\\([a-zA-Z0-9`_$]+\\)\\s-+\\([a-zA-Z0-9`_$]+\\)\\s-*(")
|
|
6690 ;;(if (looking-at "^\\(.+\\)$")
|
|
6691 (let ((module (match-string 1))
|
|
6692 (instant (match-string 2)))
|
|
6693 (if (not (member module verilog-keywords))
|
|
6694 (setq instants-list (cons (list module instant) instants-list)))))
|
|
6695 (forward-line 1)
|
|
6696 ))
|
|
6697 instants-list))
|
|
6698
|
|
6699
|
|
6700 (defun verilog-read-auto-template (module)
|
|
6701 "Look for a auto_template for the instantiation of the given MODULE.
|
|
6702 If found returns the signal name connections. Return REGEXP and
|
|
6703 list of ( (signal_name connection_name)... )"
|
|
6704 (save-excursion
|
|
6705 ;; Find beginning
|
|
6706 (let ((tpl-regexp "\\([0-9]+\\)")
|
|
6707 (lineno 0)
|
|
6708 (templateno 0)
|
|
6709 tpl-sig-list tpl-wild-list tpl-end-pt rep)
|
|
6710 (cond ((or
|
|
6711 (re-search-backward (concat "^\\s-*/?\\*?\\s-*" module "\\s-+AUTO_TEMPLATE") nil t)
|
|
6712 (progn
|
|
6713 (goto-char (point-min))
|
|
6714 (re-search-forward (concat "^\\s-*/?\\*?\\s-*" module "\\s-+AUTO_TEMPLATE") nil t)))
|
|
6715 (goto-char (match-end 0))
|
|
6716 ;; Parse "REGEXP"
|
|
6717 ;; We reserve @"..." for future lisp expressions that evaluate once-per-AUTOINST
|
|
6718 (when (looking-at "\\s-*\"\\([^\"]*)\\)\"")
|
|
6719 (setq tpl-regexp (match-string 1))
|
|
6720 (goto-char (match-end 0)))
|
|
6721 (search-forward "(")
|
|
6722 ;; Parse lines in the template
|
|
6723 (when verilog-auto-inst-template-numbers
|
|
6724 (save-excursion
|
|
6725 (goto-char (point-min))
|
|
6726 (while (search-forward "AUTO_TEMPLATE" nil t)
|
|
6727 (setq templateno (1+ templateno)))))
|
|
6728 (setq tpl-end-pt (save-excursion
|
|
6729 (backward-char 1)
|
|
6730 (forward-sexp 1) ;; Moves to paren that closes argdecl's
|
|
6731 (backward-char 1)
|
|
6732 (point)))
|
|
6733 ;;
|
|
6734 (while (< (point) tpl-end-pt)
|
|
6735 (cond ((looking-at "\\s-*\\.\\([a-zA-Z0-9`_$]+\\)\\s-*(\\(.*\\))\\s-*\\(,\\|)\\s-*;\\)")
|
|
6736 (setq tpl-sig-list (cons (list
|
|
6737 (match-string-no-properties 1)
|
|
6738 (match-string-no-properties 2)
|
|
6739 templateno lineno)
|
|
6740 tpl-sig-list))
|
|
6741 (goto-char (match-end 0)))
|
|
6742 ;; Regexp form??
|
|
6743 ((looking-at
|
|
6744 ;; Regexp bug in xemacs disallows ][ inside [], and wants + last
|
|
6745 "\\s-*\\.\\(\\([a-zA-Z0-9`_$+@^.*?|---]+\\|[][]\\|\\\\[()|]\\)+\\)\\s-*(\\(.*\\))\\s-*\\(,\\|)\\s-*;\\)")
|
|
6746 (setq rep (match-string-no-properties 3))
|
|
6747 (goto-char (match-end 0))
|
|
6748 (setq tpl-wild-list
|
|
6749 (cons (list
|
|
6750 (concat "^"
|
|
6751 (verilog-string-replace-matches "@" "\\\\([0-9]+\\\\)" nil nil
|
|
6752 (match-string 1))
|
|
6753 "$")
|
|
6754 rep
|
|
6755 templateno lineno)
|
|
6756 tpl-wild-list)))
|
|
6757 ((looking-at "[ \t\f]+")
|
|
6758 (goto-char (match-end 0)))
|
|
6759 ((looking-at "\n")
|
|
6760 (setq lineno (1+ lineno))
|
|
6761 (goto-char (match-end 0)))
|
|
6762 ((looking-at "//")
|
|
6763 (search-forward "\n"))
|
|
6764 ((looking-at "/\\*")
|
|
6765 (forward-char 2)
|
|
6766 (or (search-forward "*/")
|
|
6767 (error "%s: Unmatched /* */, at char %d" (verilog-point-text) (point))))
|
|
6768 (t
|
|
6769 (error "%s: AUTO_TEMPLATE parsing error: %s"
|
|
6770 (verilog-point-text)
|
|
6771 (progn (looking-at ".*$") (match-string 0))))
|
|
6772 ))
|
|
6773 ;; Return
|
|
6774 (vector tpl-regexp
|
|
6775 (list tpl-sig-list tpl-wild-list)))
|
|
6776 ;; If no template found
|
|
6777 (t (vector tpl-regexp nil))))))
|
|
6778 ;;(progn (find-file "auto-template.v") (verilog-read-auto-template "ptl_entry"))
|
|
6779
|
|
6780 (defun verilog-set-define (defname defvalue &optional buffer enumname)
|
|
6781 "Set the definition DEFNAME to the DEFVALUE in the given BUFFER.
|
|
6782 Optionally associate it with the specified enumeration ENUMNAME."
|
|
6783 (save-excursion
|
|
6784 (set-buffer (or buffer (current-buffer)))
|
|
6785 (let ((mac (intern (concat "vh-" defname))))
|
|
6786 ;;(message "Define %s=%s" defname defvalue) (sleep-for 1)
|
|
6787 ;; Need to define to a constant if no value given
|
|
6788 (set (make-variable-buffer-local mac)
|
|
6789 (if (equal defvalue "") "1" defvalue)))
|
|
6790 (if enumname
|
|
6791 (let ((enumvar (intern (concat "venum-" enumname))))
|
|
6792 ;;(message "Define %s=%s" defname defvalue) (sleep-for 1)
|
|
6793 (make-variable-buffer-local enumvar)
|
|
6794 (add-to-list enumvar defname)))
|
|
6795 ))
|
|
6796
|
|
6797 (defun verilog-read-defines (&optional filename recurse subcall)
|
|
6798 "Read `defines and parameters for the current file, or optional FILENAME.
|
|
6799 If the filename is provided, `verilog-library-flags' will be used to
|
|
6800 resolve it. If optional RECURSE is non-nil, recurse through `includes.
|
|
6801
|
|
6802 Parameters must be simple assignments to constants, or have their own
|
|
6803 \"parameter\" label rather than a list of parameters. Thus:
|
|
6804
|
|
6805 parameter X = 5, Y = 10; // Ok
|
|
6806 parameter X = {1'b1, 2'h2}; // Ok
|
|
6807 parameter X = {1'b1, 2'h2}, Y = 10; // Bad, make into 2 parameter lines
|
|
6808
|
|
6809 Defines must be simple text substitutions, one on a line, starting
|
|
6810 at the beginning of the line. Any ifdefs or multiline comments around the
|
|
6811 define are ignored.
|
|
6812
|
|
6813 Defines are stored inside Emacs variables using the name vh-{definename}.
|
|
6814
|
|
6815 This function is useful for setting vh-* variables. The file variables
|
|
6816 feature can be used to set defines that `verilog-mode' can see; put at the
|
|
6817 *END* of your file something like:
|
|
6818
|
|
6819 // Local Variables:
|
|
6820 // vh-macro:\"macro_definition\"
|
|
6821 // End:
|
|
6822
|
|
6823 If macros are defined earlier in the same file and you want their values,
|
|
6824 you can read them automatically (provided `enable-local-eval' is on):
|
|
6825
|
|
6826 // Local Variables:
|
|
6827 // eval:(verilog-read-defines)
|
|
6828 // eval:(verilog-read-defines \"group_standard_includes.v\")
|
|
6829 // End:
|
|
6830
|
|
6831 Note these are only read when the file is first visited, you must use
|
|
6832 \\[find-alternate-file] RET to have these take effect after editing them!
|
|
6833
|
|
6834 If you want to disable the \"Process `eval' or hook local variables\"
|
|
6835 warning message, you need to add to your .emacs file:
|
|
6836
|
|
6837 (setq enable-local-eval t)"
|
|
6838 (let ((origbuf (current-buffer)))
|
|
6839 (save-excursion
|
|
6840 (unless subcall (verilog-getopt-flags))
|
|
6841 (when filename
|
|
6842 (let ((fns (verilog-library-filenames filename (buffer-file-name))))
|
|
6843 (if fns
|
|
6844 (set-buffer (find-file-noselect (car fns)))
|
|
6845 (error (concat (verilog-point-text)
|
|
6846 ": Can't find verilog-read-defines file: " filename)))))
|
|
6847 (when recurse
|
|
6848 (goto-char (point-min))
|
|
6849 (while (re-search-forward "^\\s-*`include\\s-+\\([^ \t\n\f]+\\)" nil t)
|
|
6850 (let ((inc (verilog-string-replace-matches "\"" "" nil nil (match-string-no-properties 1))))
|
|
6851 (unless (verilog-inside-comment-p)
|
|
6852 (verilog-read-defines inc recurse t)))))
|
|
6853 ;; Read `defines
|
|
6854 ;; note we don't use verilog-re... it's faster this way, and that
|
|
6855 ;; function has problems when comments are at the end of the define
|
|
6856 (goto-char (point-min))
|
|
6857 (while (re-search-forward "^\\s-*`define\\s-+\\([a-zA-Z0-9_$]+\\)\\s-+\\(.*\\)$" nil t)
|
|
6858 (let ((defname (match-string-no-properties 1))
|
|
6859 (defvalue (match-string-no-properties 2)))
|
|
6860 (setq defvalue (verilog-string-replace-matches "\\s-*/[/*].*$" "" nil nil defvalue))
|
|
6861 (verilog-set-define defname defvalue origbuf)))
|
|
6862 ;; Hack: Read parameters
|
|
6863 (goto-char (point-min))
|
|
6864 (while (re-search-forward
|
|
6865 "^\\s-*\\(parameter\\|localparam\\)\\(\\(\\s-*\\[[^]]*\\]\\|\\)\\s-+\\([a-zA-Z0-9_$]+\\)\\s-*=\\s-*\\([^;,]*\\),?\\|\\)\\s-*" nil t)
|
|
6866 (let ((var (match-string-no-properties 4))
|
|
6867 (val (match-string-no-properties 5))
|
|
6868 enumname)
|
|
6869 ;; The primary way of getting defines is verilog-read-decls
|
|
6870 ;; However, that isn't called yet for included files, so we'll add another scheme
|
|
6871 (if (looking-at "[^\n]*synopsys\\s +enum\\s +\\([a-zA-Z0-9_]+\\)")
|
|
6872 (setq enumname (match-string-no-properties 1)))
|
|
6873 (if var
|
|
6874 (verilog-set-define var val origbuf enumname))
|
|
6875 (forward-comment 999)
|
|
6876 (while (looking-at "\\s-*,?\\s-*\\([a-zA-Z0-9_$]+\\)\\s-*=\\s-*\\([^;,]*\\),?\\s-*")
|
|
6877 (verilog-set-define (match-string-no-properties 1) (match-string-no-properties 2) origbuf enumname)
|
|
6878 (goto-char (match-end 0))
|
|
6879 (forward-comment 999))))
|
|
6880 )))
|
|
6881
|
|
6882 (defun verilog-read-includes ()
|
|
6883 "Read `includes for the current file.
|
|
6884 This will find all of the `includes which are at the beginning of lines,
|
|
6885 ignoring any ifdefs or multiline comments around them.
|
|
6886 `verilog-read-defines' is then performed on the current and each included
|
|
6887 file.
|
|
6888
|
|
6889 It is often useful put at the *END* of your file something like:
|
|
6890
|
|
6891 // Local Variables:
|
|
6892 // eval:(verilog-read-defines)
|
|
6893 // eval:(verilog-read-includes)
|
|
6894 // End:
|
|
6895
|
|
6896 Note includes are only read when the file is first visited, you must use
|
|
6897 \\[find-alternate-file] RET to have these take effect after editing them!
|
|
6898
|
|
6899 It is good to get in the habit of including all needed files in each .v
|
|
6900 file that needs it, rather than waiting for compile time. This will aid
|
|
6901 this process, Verilint, and readability. To prevent defining the same
|
|
6902 variable over and over when many modules are compiled together, put a test
|
|
6903 around the inside each include file:
|
|
6904
|
|
6905 foo.v (a include):
|
|
6906 `ifdef _FOO_V // include if not already included
|
|
6907 `else
|
|
6908 `define _FOO_V
|
|
6909 ... contents of file
|
|
6910 `endif // _FOO_V"
|
|
6911 ;;slow: (verilog-read-defines nil t))
|
|
6912 (save-excursion
|
|
6913 (verilog-getopt-flags)
|
|
6914 (goto-char (point-min))
|
|
6915 (while (re-search-forward "^\\s-*`include\\s-+\\([^ \t\n\f]+\\)" nil t)
|
|
6916 (let ((inc (verilog-string-replace-matches "\"" "" nil nil (match-string 1))))
|
|
6917 (verilog-read-defines inc nil t)))))
|
|
6918
|
|
6919 (defun verilog-read-signals (&optional start end)
|
|
6920 "Return a simple list of all possible signals in the file.
|
|
6921 Bounded by optional region from START to END. Overly aggressive but fast.
|
|
6922 Some macros and such are also found and included. For dinotrace.el"
|
|
6923 (let (sigs-all keywd)
|
|
6924 (progn;save-excursion
|
|
6925 (goto-char (or start (point-min)))
|
|
6926 (setq end (or end (point-max)))
|
|
6927 (while (re-search-forward "[\"/a-zA-Z_.%`]" end t)
|
|
6928 (forward-char -1)
|
|
6929 (cond
|
|
6930 ((looking-at "//")
|
|
6931 (search-forward "\n"))
|
|
6932 ((looking-at "/\\*")
|
|
6933 (search-forward "*/"))
|
|
6934 ((looking-at "(\\*")
|
|
6935 (or (looking-at "(\\*\\s-*)") ; It's a "always @ (*)"
|
|
6936 (search-forward "*)")))
|
|
6937 ((eq ?\" (following-char))
|
|
6938 (re-search-forward "[^\\]\"")) ;; don't forward-char first, since we look for a non backslash first
|
|
6939 ((looking-at "\\s-*\\([a-zA-Z0-9$_.%`]+\\)")
|
|
6940 (goto-char (match-end 0))
|
|
6941 (setq keywd (match-string-no-properties 1))
|
|
6942 (or (member keywd verilog-keywords)
|
|
6943 (member keywd sigs-all)
|
|
6944 (setq sigs-all (cons keywd sigs-all))))
|
|
6945 (t (forward-char 1)))
|
|
6946 )
|
|
6947 ;; Return list
|
|
6948 sigs-all)))
|
|
6949
|
|
6950 ;;
|
|
6951 ;; Argument file parsing
|
|
6952 ;;
|
|
6953
|
|
6954 (defun verilog-getopt (arglist)
|
|
6955 "Parse -f, -v etc arguments in ARGLIST list or string."
|
|
6956 (unless (listp arglist) (setq arglist (list arglist)))
|
|
6957 (let ((space-args '())
|
|
6958 arg next-param)
|
|
6959 ;; Split on spaces, so users can pass whole command lines
|
|
6960 (while arglist
|
|
6961 (setq arg (car arglist)
|
|
6962 arglist (cdr arglist))
|
|
6963 (while (string-match "^\\([^ \t\n\f]+\\)[ \t\n\f]*\\(.*$\\)" arg)
|
|
6964 (setq space-args (append space-args
|
|
6965 (list (match-string-no-properties 1 arg))))
|
|
6966 (setq arg (match-string 2 arg))))
|
|
6967 ;; Parse arguments
|
|
6968 (while space-args
|
|
6969 (setq arg (car space-args)
|
|
6970 space-args (cdr space-args))
|
|
6971 (cond
|
|
6972 ;; Need another arg
|
|
6973 ((equal arg "-f")
|
|
6974 (setq next-param arg))
|
|
6975 ((equal arg "-v")
|
|
6976 (setq next-param arg))
|
|
6977 ((equal arg "-y")
|
|
6978 (setq next-param arg))
|
|
6979 ;; +libext+(ext1)+(ext2)...
|
|
6980 ((string-match "^\\+libext\\+\\(.*\\)" arg)
|
|
6981 (setq arg (match-string 1 arg))
|
|
6982 (while (string-match "\\([^+]+\\)\\+?\\(.*\\)" arg)
|
|
6983 (verilog-add-list-unique `verilog-library-extensions
|
|
6984 (match-string 1 arg))
|
|
6985 (setq arg (match-string 2 arg))))
|
|
6986 ;;
|
|
6987 ((or (string-match "^-D\\([^+=]*\\)[+=]\\(.*\\)" arg) ;; -Ddefine=val
|
|
6988 (string-match "^-D\\([^+=]*\\)\\(\\)" arg) ;; -Ddefine
|
|
6989 (string-match "^\\+define\\([^+=]*\\)[+=]\\(.*\\)" arg) ;; +define+val
|
|
6990 (string-match "^\\+define\\([^+=]*\\)\\(\\)" arg)) ;; +define+define
|
|
6991 (verilog-set-define (match-string 1 arg) (match-string 2 arg)))
|
|
6992 ;;
|
|
6993 ((or (string-match "^\\+incdir\\+\\(.*\\)" arg) ;; +incdir+dir
|
|
6994 (string-match "^-I\\(.*\\)" arg)) ;; -Idir
|
|
6995 (verilog-add-list-unique `verilog-library-directories
|
|
6996 (match-string 1 arg)))
|
|
6997 ;; Ignore
|
|
6998 ((equal "+librescan" arg))
|
|
6999 ((string-match "^-U\\(.*\\)" arg)) ;; -Udefine
|
|
7000 ;; Second parameters
|
|
7001 ((equal next-param "-f")
|
|
7002 (setq next-param nil)
|
|
7003 (verilog-getopt-file arg))
|
|
7004 ((equal next-param "-v")
|
|
7005 (setq next-param nil)
|
|
7006 (verilog-add-list-unique `verilog-library-files arg))
|
|
7007 ((equal next-param "-y")
|
|
7008 (setq next-param nil)
|
|
7009 (verilog-add-list-unique `verilog-library-directories arg))
|
|
7010 ;; Filename
|
|
7011 ((string-match "^[^-+]" arg)
|
|
7012 (verilog-add-list-unique `verilog-library-files arg))
|
|
7013 ;; Default - ignore; no warning
|
|
7014 )
|
|
7015 )
|
|
7016 )
|
|
7017 )
|
|
7018 ;;(verilog-getopt (list "+libext+.a+.b" "+incdir+foodir" "+define+a+aval" "-f" "otherf" "-v" "library" "-y" "dir"))
|
|
7019
|
|
7020 (defun verilog-getopt-file (filename)
|
|
7021 "Read verilog options from the specified FILENAME."
|
|
7022 (save-excursion
|
|
7023 (let ((fns (verilog-library-filenames filename (buffer-file-name)))
|
|
7024 (orig-buffer (current-buffer))
|
|
7025 line)
|
|
7026 (if fns
|
|
7027 (set-buffer (find-file-noselect (car fns)))
|
|
7028 (error (concat (verilog-point-text)
|
|
7029 "Can't find verilog-getopt-file -f file: " filename)))
|
|
7030 (goto-char (point-min))
|
|
7031 (while (not (eobp))
|
|
7032 (setq line (buffer-substring (point)
|
|
7033 (save-excursion (end-of-line) (point))))
|
|
7034 (forward-line 1)
|
|
7035 (when (string-match "//" line)
|
|
7036 (setq line (substring line 0 (match-beginning 0))))
|
|
7037 (save-excursion
|
|
7038 (set-buffer orig-buffer) ; Variables are buffer-local, so need right context.
|
|
7039 (verilog-getopt line))))))
|
|
7040
|
|
7041 (defun verilog-getopt-flags ()
|
|
7042 "Convert `verilog-library-flags' into standard library variables."
|
|
7043 ;; If the flags are local, then all the outputs should be local also
|
|
7044 (when (local-variable-p `verilog-library-flags (current-buffer))
|
|
7045 (make-variable-buffer-local 'verilog-library-extensions)
|
|
7046 (make-variable-buffer-local 'verilog-library-directories)
|
|
7047 (make-variable-buffer-local 'verilog-library-files)
|
|
7048 (make-variable-buffer-local 'verilog-library-flags))
|
|
7049 ;; Allow user to customize
|
|
7050 (run-hooks 'verilog-before-getopt-flags-hook)
|
|
7051 ;; Process arguments
|
|
7052 (verilog-getopt verilog-library-flags)
|
|
7053 ;; Allow user to customize
|
|
7054 (run-hooks 'verilog-getopt-flags-hook))
|
|
7055
|
|
7056 (defun verilog-add-list-unique (varref object)
|
|
7057 "Append to VARREF list the given OBJECT,
|
|
7058 unless it is already a member of the variable's list"
|
|
7059 (unless (member object (symbol-value varref))
|
|
7060 (set varref (append (symbol-value varref) (list object))))
|
|
7061 varref)
|
|
7062 ;;(progn (setq l '()) (verilog-add-list-unique `l "a") (verilog-add-list-unique `l "a") l)
|
|
7063
|
|
7064
|
|
7065 ;;
|
|
7066 ;; Module name lookup
|
|
7067 ;;
|
|
7068
|
|
7069 (defun verilog-module-inside-filename-p (module filename)
|
|
7070 "Return point if MODULE is specified inside FILENAME, else nil.
|
|
7071 Allows version control to check out the file if need be."
|
|
7072 (and (or (file-exists-p filename)
|
|
7073 (and
|
|
7074 (condition-case nil
|
|
7075 (fboundp 'vc-backend)
|
|
7076 (error nil))
|
|
7077 (vc-backend filename)))
|
|
7078 (let (pt)
|
|
7079 (save-excursion
|
|
7080 (set-buffer (find-file-noselect filename))
|
|
7081 (goto-char (point-min))
|
|
7082 (while (and
|
|
7083 ;; It may be tempting to look for verilog-defun-re, don't, it slows things down a lot!
|
|
7084 (verilog-re-search-forward-quick "\\<module\\>" nil t)
|
|
7085 (verilog-re-search-forward-quick "[(;]" nil t))
|
|
7086 (if (equal module (verilog-read-module-name))
|
|
7087 (setq pt (point))))
|
|
7088 pt))))
|
|
7089
|
|
7090 (defun verilog-is-number (symbol)
|
|
7091 "Return true if SYMBOL is number-like."
|
|
7092 (or (string-match "^[0-9 \t:]+$" symbol)
|
|
7093 (string-match "^[---]*[0-9]+$" symbol)
|
|
7094 (string-match "^[0-9 \t]+'s?[hdxbo][0-9a-fA-F_xz? \t]*$" symbol)
|
|
7095 ))
|
|
7096
|
|
7097 (defun verilog-symbol-detick (symbol wing-it)
|
|
7098 "Return a expanded SYMBOL name without any defines.
|
|
7099 If the variable vh-{symbol} is defined, return that value.
|
|
7100 If undefined, and WING-IT, return just SYMBOL without the tick, else nil."
|
|
7101 (while (and symbol (string-match "^`" symbol))
|
|
7102 (setq symbol (substring symbol 1))
|
|
7103 (setq symbol
|
|
7104 (if (boundp (intern (concat "vh-" symbol)))
|
|
7105 ;; Emacs has a bug where boundp on a buffer-local
|
|
7106 ;; variable in only one buffer returns t in another.
|
|
7107 ;; This can confuse, so check for nil.
|
|
7108 (let ((val (eval (intern (concat "vh-" symbol)))))
|
|
7109 (if (eq val nil)
|
|
7110 (if wing-it symbol nil)
|
|
7111 val))
|
|
7112 (if wing-it symbol nil))))
|
|
7113 symbol)
|
|
7114 ;;(verilog-symbol-detick "`mod" nil)
|
|
7115
|
|
7116 (defun verilog-symbol-detick-denumber (symbol)
|
|
7117 "Return SYMBOL with defines converted and any numbers dropped to nil."
|
|
7118 (when (string-match "^`" symbol)
|
|
7119 ;; This only will work if the define is a simple signal, not
|
|
7120 ;; something like a[b]. Sorry, it should be substituted into the parser
|
|
7121 (setq symbol
|
|
7122 (verilog-string-replace-matches
|
|
7123 "\[[^0-9: \t]+\]" "" nil nil
|
|
7124 (or (verilog-symbol-detick symbol nil)
|
|
7125 (if verilog-auto-sense-defines-constant
|
|
7126 "0"
|
|
7127 symbol)))))
|
|
7128 (if (verilog-is-number symbol)
|
|
7129 nil
|
|
7130 symbol))
|
|
7131
|
|
7132 (defun verilog-symbol-detick-text (text)
|
|
7133 "Return TEXT with any without any known defines.
|
|
7134 If the variable vh-{symbol} is defined, substitute that value."
|
|
7135 (let ((ok t) symbol val)
|
|
7136 (while (and ok (string-match "`\\([a-zA-Z0-9_]+\\)" text))
|
|
7137 (setq symbol (match-string 1 text))
|
|
7138 (message symbol)
|
|
7139 (cond ((and
|
|
7140 (boundp (intern (concat "vh-" symbol)))
|
|
7141 ;; Emacs has a bug where boundp on a buffer-local
|
|
7142 ;; variable in only one buffer returns t in another.
|
|
7143 ;; This can confuse, so check for nil.
|
|
7144 (setq val (eval (intern (concat "vh-" symbol)))))
|
|
7145 (setq text (replace-match val nil nil text)))
|
|
7146 (t (setq ok nil)))))
|
|
7147 text)
|
|
7148 ;;(progn (setq vh-mod "`foo" vh-foo "bar") (verilog-symbol-detick-text "bar `mod `undefed"))
|
|
7149
|
|
7150 (defun verilog-expand-dirnames (&optional dirnames)
|
|
7151 "Return a list of existing directories given a list of wildcarded DIRNAMES.
|
|
7152 Or, just the existing dirnames themselves if there are no wildcards."
|
|
7153 (interactive)
|
|
7154 (unless dirnames (error "`verilog-library-directories' should include at least '.'"))
|
|
7155 (setq dirnames (reverse dirnames)) ; not nreverse
|
|
7156 (let ((dirlist nil)
|
|
7157 pattern dirfile dirfiles dirname root filename rest)
|
|
7158 (while dirnames
|
|
7159 (setq dirname (substitute-in-file-name (car dirnames))
|
|
7160 dirnames (cdr dirnames))
|
|
7161 (cond ((string-match (concat "^\\(\\|[/\\]*[^*?]*[/\\]\\)" ;; root
|
|
7162 "\\([^/\\]*[*?][^/\\]*\\)" ;; filename with *?
|
|
7163 "\\(.*\\)") ;; rest
|
|
7164 dirname)
|
|
7165 (setq root (match-string 1 dirname)
|
|
7166 filename (match-string 2 dirname)
|
|
7167 rest (match-string 3 dirname)
|
|
7168 pattern filename)
|
|
7169 ;; now replace those * and ? with .+ and .
|
|
7170 ;; use ^ and /> to get only whole file names
|
|
7171 ;;verilog-string-replace-matches
|
|
7172 (setq pattern (verilog-string-replace-matches "[*]" ".+" nil nil pattern)
|
|
7173 pattern (verilog-string-replace-matches "[?]" "." nil nil pattern)
|
|
7174
|
|
7175 ;; Unfortunately allows abc/*/rtl to match abc/rtl
|
|
7176 ;; because abc/.. shows up in dirfiles. Solutions welcome.
|
|
7177 dirfiles (if (file-directory-p root) ; Ignore version control external
|
|
7178 (directory-files root t pattern nil)))
|
|
7179 (while dirfiles
|
|
7180 (setq dirfile (expand-file-name (concat (car dirfiles) rest))
|
|
7181 dirfiles (cdr dirfiles))
|
|
7182 (if (file-directory-p dirfile)
|
|
7183 (setq dirlist (cons dirfile dirlist))))
|
|
7184 )
|
|
7185 ;; Defaults
|
|
7186 (t
|
|
7187 (if (file-directory-p dirname)
|
|
7188 (setq dirlist (cons dirname dirlist))))
|
|
7189 ))
|
|
7190 dirlist))
|
|
7191 ;;(verilog-expand-dirnames (list "." ".." "nonexist" "../*" "/home/wsnyder/*/v"))
|
|
7192
|
|
7193 (defun verilog-library-filenames (filename current &optional check-ext)
|
|
7194 "Return a search path to find the given FILENAME name.
|
|
7195 Uses the CURRENT filename, `verilog-library-directories' and
|
|
7196 `verilog-library-extensions' variables to build the path.
|
|
7197 With optional CHECK-EXT also check `verilog-library-extensions'."
|
|
7198 (let ((ckdir (verilog-expand-dirnames verilog-library-directories))
|
|
7199 fn outlist)
|
|
7200 (while ckdir
|
|
7201 (let ((ckext (if check-ext verilog-library-extensions `(""))))
|
|
7202 (while ckext
|
|
7203 (setq fn (expand-file-name
|
|
7204 (concat filename (car ckext))
|
|
7205 (expand-file-name (car ckdir) (file-name-directory current))))
|
|
7206 (if (file-exists-p fn)
|
|
7207 (setq outlist (cons fn outlist)))
|
|
7208 (setq ckext (cdr ckext))))
|
|
7209 (setq ckdir (cdr ckdir)))
|
|
7210 (nreverse outlist)))
|
|
7211
|
|
7212 (defun verilog-module-filenames (module current)
|
|
7213 "Return a search path to find the given MODULE name.
|
|
7214 Uses the CURRENT filename, `verilog-library-extensions',
|
|
7215 `verilog-library-directories' and `verilog-library-files'
|
|
7216 variables to build the path."
|
|
7217 ;; Return search locations for it
|
|
7218 (append (list current) ; first, current buffer
|
|
7219 (verilog-library-filenames module current t)
|
|
7220 verilog-library-files)) ; finally, any libraries
|
|
7221
|
|
7222 ;;
|
|
7223 ;; Module Information
|
|
7224 ;;
|
|
7225 ;; Many of these functions work on "modi" a module information structure
|
|
7226 ;; A modi is: [module-name-string file-name begin-point]
|
|
7227
|
|
7228 (defvar verilog-cache-enabled t
|
|
7229 "If true, enable caching of signals, etc. Set to nil for debugging to make things SLOW!")
|
|
7230
|
|
7231 (defvar verilog-modi-cache-list nil
|
|
7232 "Cache of ((Module Function) Buf-Tick Buf-Modtime Func-Returns)...
|
|
7233 For speeding up verilog-modi-get-* commands.
|
|
7234 Buffer-local.")
|
|
7235
|
|
7236 (defvar verilog-modi-cache-preserve-tick nil
|
|
7237 "Modification tick after which the cache is still considered valid.
|
|
7238 Use verilog-preserve-cache's to set")
|
|
7239 (defvar verilog-modi-cache-preserve-buffer nil
|
|
7240 "Modification tick after which the cache is still considered valid.
|
|
7241 Use verilog-preserve-cache's to set")
|
|
7242
|
|
7243 (defun verilog-modi-current ()
|
|
7244 "Return the modi structure for the module currently at point."
|
|
7245 (let* (name pt)
|
|
7246 ;; read current module's name
|
|
7247 (save-excursion
|
|
7248 (verilog-re-search-backward-quick verilog-defun-re nil nil)
|
|
7249 (verilog-re-search-forward-quick "(" nil nil)
|
|
7250 (setq name (verilog-read-module-name))
|
|
7251 (setq pt (point)))
|
|
7252 ;; return
|
|
7253 (vector name (or (buffer-file-name) (current-buffer)) pt)))
|
|
7254
|
|
7255 (defvar verilog-modi-lookup-last-mod nil "Cache of last module looked up.")
|
|
7256 (defvar verilog-modi-lookup-last-modi nil "Cache of last modi returned.")
|
|
7257 (defvar verilog-modi-lookup-last-current nil "Cache of last `current-buffer' looked up.")
|
|
7258 (defvar verilog-modi-lookup-last-tick nil "Cache of last `buffer-modified-tick' looked up.")
|
|
7259
|
|
7260 (defun verilog-modi-lookup (module allow-cache &optional ignore-error)
|
|
7261 "Find the file and point at which MODULE is defined.
|
|
7262 If ALLOW-CACHE is set, check and remember cache of previous lookups.
|
|
7263 Return modi if successful, else print message unless IGNORE-ERROR is true."
|
|
7264 (let* ((current (or (buffer-file-name) (current-buffer))))
|
|
7265 (cond ((and verilog-modi-lookup-last-modi
|
|
7266 verilog-cache-enabled
|
|
7267 allow-cache
|
|
7268 (equal verilog-modi-lookup-last-mod module)
|
|
7269 (equal verilog-modi-lookup-last-current current)
|
|
7270 (equal verilog-modi-lookup-last-tick (buffer-modified-tick)))
|
|
7271 ;; ok as is
|
|
7272 )
|
|
7273 (t (let* ((realmod (verilog-symbol-detick module t))
|
|
7274 (orig-filenames (verilog-module-filenames realmod current))
|
|
7275 (filenames orig-filenames)
|
|
7276 pt)
|
|
7277 (while (and filenames (not pt))
|
|
7278 (if (not (setq pt (verilog-module-inside-filename-p realmod (car filenames))))
|
|
7279 (setq filenames (cdr filenames))))
|
|
7280 (cond (pt (setq verilog-modi-lookup-last-modi
|
|
7281 (vector realmod (car filenames) pt)))
|
|
7282 (t (setq verilog-modi-lookup-last-modi nil)
|
|
7283 (or ignore-error
|
|
7284 (error (concat (verilog-point-text)
|
|
7285 ": Can't locate " module " module definition"
|
|
7286 (if (not (equal module realmod))
|
|
7287 (concat " (Expanded macro to " realmod ")")
|
|
7288 "")
|
|
7289 "\n Check the verilog-library-directories variable."
|
|
7290 "\n I looked in (if not listed, doesn't exist):\n\t"
|
|
7291 (mapconcat 'concat orig-filenames "\n\t")))))
|
|
7292 )
|
|
7293 (setq verilog-modi-lookup-last-mod module
|
|
7294 verilog-modi-lookup-last-current current
|
|
7295 verilog-modi-lookup-last-tick (buffer-modified-tick)))))
|
|
7296 verilog-modi-lookup-last-modi
|
|
7297 ))
|
|
7298
|
|
7299 (defsubst verilog-modi-name (modi)
|
|
7300 (aref modi 0))
|
|
7301 (defsubst verilog-modi-file-or-buffer (modi)
|
|
7302 (aref modi 1))
|
|
7303 (defsubst verilog-modi-point (modi)
|
|
7304 (aref modi 2))
|
|
7305
|
|
7306 (defun verilog-modi-filename (modi)
|
|
7307 "Filename of MODI, or name of buffer if its never been saved."
|
|
7308 (if (bufferp (verilog-modi-file-or-buffer modi))
|
|
7309 (or (buffer-file-name (verilog-modi-file-or-buffer modi))
|
|
7310 (buffer-name (verilog-modi-file-or-buffer modi)))
|
|
7311 (verilog-modi-file-or-buffer modi)))
|
|
7312
|
|
7313 (defun verilog-modi-goto (modi)
|
|
7314 "Move point/buffer to specified MODI."
|
|
7315 (or modi (error "Passed unfound modi to goto, check earlier"))
|
|
7316 (set-buffer (if (bufferp (verilog-modi-file-or-buffer modi))
|
|
7317 (verilog-modi-file-or-buffer modi)
|
|
7318 (find-file-noselect (verilog-modi-file-or-buffer modi))))
|
|
7319 (or (equal major-mode `verilog-mode) ;; Put into verilog mode to get syntax
|
|
7320 (verilog-mode))
|
|
7321 (goto-char (verilog-modi-point modi)))
|
|
7322
|
|
7323 (defun verilog-goto-defun-file (module)
|
|
7324 "Move point to the file at which a given MODULE is defined."
|
|
7325 (interactive "sGoto File for Module: ")
|
|
7326 (let* ((modi (verilog-modi-lookup module nil)))
|
|
7327 (when modi
|
|
7328 (verilog-modi-goto modi)
|
|
7329 (switch-to-buffer (current-buffer)))))
|
|
7330
|
|
7331 (defun verilog-modi-cache-results (modi function)
|
|
7332 "Run on MODI the given FUNCTION. Locate the module in a file.
|
|
7333 Cache the output of function so next call may have faster access."
|
|
7334 (let (func-returns fass)
|
|
7335 (save-excursion
|
|
7336 (verilog-modi-goto modi)
|
|
7337 (if (and (setq fass (assoc (list (verilog-modi-name modi) function)
|
|
7338 verilog-modi-cache-list))
|
|
7339 ;; Destroy caching when incorrect; Modified or file changed
|
|
7340 (not (and verilog-cache-enabled
|
|
7341 (or (equal (buffer-modified-tick) (nth 1 fass))
|
|
7342 (and verilog-modi-cache-preserve-tick
|
|
7343 (<= verilog-modi-cache-preserve-tick (nth 1 fass))
|
|
7344 (equal verilog-modi-cache-preserve-buffer (current-buffer))))
|
|
7345 (equal (visited-file-modtime) (nth 2 fass)))))
|
|
7346 (setq verilog-modi-cache-list nil
|
|
7347 fass nil))
|
|
7348 (cond (fass
|
|
7349 ;; Found
|
|
7350 (setq func-returns (nth 3 fass)))
|
|
7351 (t
|
|
7352 ;; Read from file
|
|
7353 ;; Clear then restore any hilighting to make emacs19 happy
|
|
7354 (let ((fontlocked (when (and (boundp 'font-lock-mode)
|
|
7355 font-lock-mode)
|
|
7356 (font-lock-mode nil)
|
|
7357 t)))
|
|
7358 (setq func-returns (funcall function))
|
|
7359 (when fontlocked (font-lock-mode t)))
|
|
7360 ;; Cache for next time
|
|
7361 (make-variable-buffer-local 'verilog-modi-cache-list)
|
|
7362 (setq verilog-modi-cache-list
|
|
7363 (cons (list (list (verilog-modi-name modi) function)
|
|
7364 (buffer-modified-tick)
|
|
7365 (visited-file-modtime)
|
|
7366 func-returns)
|
|
7367 verilog-modi-cache-list)))
|
|
7368 ))
|
|
7369 ;;
|
|
7370 func-returns))
|
|
7371
|
|
7372 (defun verilog-modi-cache-add (modi function element sig-list)
|
|
7373 "Add function return results to the module cache.
|
|
7374 Update MODI's cache for given FUNCTION so that the return ELEMENT of that
|
|
7375 function now contains the additional SIG-LIST parameters."
|
|
7376 (let (fass)
|
|
7377 (save-excursion
|
|
7378 (verilog-modi-goto modi)
|
|
7379 (if (setq fass (assoc (list (verilog-modi-name modi) function)
|
|
7380 verilog-modi-cache-list))
|
|
7381 (let ((func-returns (nth 3 fass)))
|
|
7382 (aset func-returns element
|
|
7383 (append sig-list (aref func-returns element))))))))
|
|
7384
|
|
7385 (defmacro verilog-preserve-cache (&rest body)
|
|
7386 "Execute the BODY forms, allowing cache preservation within BODY.
|
|
7387 This means that changes to the buffer will not result in the cache being
|
|
7388 flushed. If the changes affect the modsig state, they must call the
|
|
7389 modsig-cache-add-* function, else the results of later calls may be
|
|
7390 incorrect. Without this, changes are assumed to be adding/removing signals
|
|
7391 and invalidating the cache."
|
|
7392 `(let ((verilog-modi-cache-preserve-tick (buffer-modified-tick))
|
|
7393 (verilog-modi-cache-preserve-buffer (current-buffer)))
|
|
7394 (progn ,@body)))
|
|
7395
|
|
7396 (defsubst verilog-modi-get-decls (modi)
|
|
7397 (verilog-modi-cache-results modi 'verilog-read-decls))
|
|
7398
|
|
7399 (defsubst verilog-modi-get-sub-decls (modi)
|
|
7400 (verilog-modi-cache-results modi 'verilog-read-sub-decls))
|
|
7401
|
|
7402 ;; Signal reading for given module
|
|
7403 ;; Note these all take modi's - as returned from the verilog-modi-current function
|
|
7404 (defsubst verilog-modi-get-outputs (modi)
|
|
7405 (aref (verilog-modi-get-decls modi) 0))
|
|
7406 (defsubst verilog-modi-get-inouts (modi)
|
|
7407 (aref (verilog-modi-get-decls modi) 1))
|
|
7408 (defsubst verilog-modi-get-inputs (modi)
|
|
7409 (aref (verilog-modi-get-decls modi) 2))
|
|
7410 (defsubst verilog-modi-get-wires (modi)
|
|
7411 (aref (verilog-modi-get-decls modi) 3))
|
|
7412 (defsubst verilog-modi-get-regs (modi)
|
|
7413 (aref (verilog-modi-get-decls modi) 4))
|
|
7414 (defsubst verilog-modi-get-assigns (modi)
|
|
7415 (aref (verilog-modi-get-decls modi) 5))
|
|
7416 (defsubst verilog-modi-get-consts (modi)
|
|
7417 (aref (verilog-modi-get-decls modi) 6))
|
|
7418 (defsubst verilog-modi-get-gparams (modi)
|
|
7419 (aref (verilog-modi-get-decls modi) 7))
|
|
7420 (defsubst verilog-modi-get-sub-outputs (modi)
|
|
7421 (aref (verilog-modi-get-sub-decls modi) 0))
|
|
7422 (defsubst verilog-modi-get-sub-inouts (modi)
|
|
7423 (aref (verilog-modi-get-sub-decls modi) 1))
|
|
7424 (defsubst verilog-modi-get-sub-inputs (modi)
|
|
7425 (aref (verilog-modi-get-sub-decls modi) 2))
|
|
7426
|
|
7427
|
|
7428 (defun verilog-signals-matching-enum (in-list enum)
|
|
7429 "Return all signals in IN-LIST matching the given ENUM."
|
|
7430 (let (out-list)
|
|
7431 (while in-list
|
|
7432 (if (equal (verilog-sig-enum (car in-list)) enum)
|
|
7433 (setq out-list (cons (car in-list) out-list)))
|
|
7434 (setq in-list (cdr in-list)))
|
|
7435 ;; New scheme
|
|
7436 (let* ((enumvar (intern (concat "venum-" enum)))
|
|
7437 (enumlist (and (boundp enumvar) (eval enumvar))))
|
|
7438 (while enumlist
|
|
7439 (add-to-list 'out-list (list (car enumlist)))
|
|
7440 (setq enumlist (cdr enumlist))))
|
|
7441 (nreverse out-list)))
|
|
7442
|
|
7443 (defun verilog-signals-not-matching-regexp (in-list regexp)
|
|
7444 "Return all signals in IN-LIST not matching the given REGEXP, if non-nil."
|
|
7445 (if (not regexp)
|
|
7446 in-list
|
|
7447 (let (out-list)
|
|
7448 (while in-list
|
|
7449 (if (not (string-match regexp (verilog-sig-name (car in-list))))
|
|
7450 (setq out-list (cons (car in-list) out-list)))
|
|
7451 (setq in-list (cdr in-list)))
|
|
7452 (nreverse out-list))))
|
|
7453
|
|
7454 ;; Combined
|
|
7455 (defun verilog-modi-get-signals (modi)
|
|
7456 (append
|
|
7457 (verilog-modi-get-outputs modi)
|
|
7458 (verilog-modi-get-inouts modi)
|
|
7459 (verilog-modi-get-inputs modi)
|
|
7460 (verilog-modi-get-wires modi)
|
|
7461 (verilog-modi-get-regs modi)
|
|
7462 (verilog-modi-get-assigns modi)
|
|
7463 (verilog-modi-get-consts modi)
|
|
7464 (verilog-modi-get-gparams modi)))
|
|
7465
|
|
7466 (defun verilog-modi-get-ports (modi)
|
|
7467 (append
|
|
7468 (verilog-modi-get-outputs modi)
|
|
7469 (verilog-modi-get-inouts modi)
|
|
7470 (verilog-modi-get-inputs modi)))
|
|
7471
|
|
7472 (defsubst verilog-modi-cache-add-outputs (modi sig-list)
|
|
7473 (verilog-modi-cache-add modi 'verilog-read-decls 0 sig-list))
|
|
7474 (defsubst verilog-modi-cache-add-inouts (modi sig-list)
|
|
7475 (verilog-modi-cache-add modi 'verilog-read-decls 1 sig-list))
|
|
7476 (defsubst verilog-modi-cache-add-inputs (modi sig-list)
|
|
7477 (verilog-modi-cache-add modi 'verilog-read-decls 2 sig-list))
|
|
7478 (defsubst verilog-modi-cache-add-wires (modi sig-list)
|
|
7479 (verilog-modi-cache-add modi 'verilog-read-decls 3 sig-list))
|
|
7480 (defsubst verilog-modi-cache-add-regs (modi sig-list)
|
|
7481 (verilog-modi-cache-add modi 'verilog-read-decls 4 sig-list))
|
|
7482
|
|
7483 (defun verilog-signals-from-signame (signame-list)
|
|
7484 "Return signals in standard form from SIGNAME-LIST, a simple list of signal names."
|
|
7485 (mapcar (function (lambda (name) (list name nil nil)))
|
|
7486 signame-list))
|
|
7487
|
|
7488 ;;
|
|
7489 ;; Auto creation utilities
|
|
7490 ;;
|
|
7491
|
|
7492 (defun verilog-auto-search-do (search-for func)
|
|
7493 "Search for the given auto text SEARCH-FOR, and perform FUNC where it occurs."
|
|
7494 (goto-char (point-min))
|
|
7495 (while (search-forward search-for nil t)
|
|
7496 (if (not (save-excursion
|
|
7497 (goto-char (match-beginning 0))
|
|
7498 (verilog-inside-comment-p)))
|
|
7499 (funcall func))))
|
|
7500
|
|
7501 (defun verilog-auto-re-search-do (search-for func)
|
|
7502 "Search for the given auto text SEARCH-FOR, and perform FUNC where it occurs."
|
|
7503 (goto-char (point-min))
|
|
7504 (while (re-search-forward search-for nil t)
|
|
7505 (if (not (save-excursion
|
|
7506 (goto-char (match-beginning 0))
|
|
7507 (verilog-inside-comment-p)))
|
|
7508 (funcall func))))
|
|
7509
|
|
7510 (defun verilog-insert-one-definition (sig type indent-pt)
|
|
7511 "Print out a definition for SIGNAL of the given TYPE,
|
|
7512 with appropriate INDENT-PT indentation."
|
|
7513 (indent-to indent-pt)
|
|
7514 (insert type)
|
|
7515 (when (verilog-sig-signed sig)
|
|
7516 (insert " " (verilog-sig-signed sig)))
|
|
7517 (when (verilog-sig-multidim sig)
|
|
7518 (insert " " (verilog-sig-multidim-string sig)))
|
|
7519 (when (verilog-sig-bits sig)
|
|
7520 (insert " " (verilog-sig-bits sig)))
|
|
7521 (indent-to (max 24 (+ indent-pt 16)))
|
|
7522 (unless (= (char-syntax (preceding-char)) ?\ )
|
|
7523 (insert " ")) ; Need space between "]name" if indent-to did nothing
|
|
7524 (insert (verilog-sig-name sig)))
|
|
7525
|
|
7526 (defun verilog-insert-definition (sigs direction indent-pt v2k &optional dont-sort)
|
|
7527 "Print out a definition for a list of SIGS of the given DIRECTION,
|
|
7528 with appropriate INDENT-PT indentation. If V2K, use Verilog 2001 I/O
|
|
7529 format. Sort unless DONT-SORT. DIRECTION is normally wire/reg/output."
|
|
7530 (or dont-sort
|
|
7531 (setq sigs (sort (copy-alist sigs) `verilog-signals-sort-compare)))
|
|
7532 (while sigs
|
|
7533 (let ((sig (car sigs)))
|
|
7534 (verilog-insert-one-definition
|
|
7535 sig
|
|
7536 ;; Want "type x" or "output type x", not "wire type x"
|
|
7537 (cond ((verilog-sig-type sig)
|
|
7538 (concat
|
|
7539 (if (not (equal direction "wire"))
|
|
7540 (concat direction " "))
|
|
7541 (verilog-sig-type sig)))
|
|
7542 (t direction))
|
|
7543 indent-pt)
|
|
7544 (insert (if v2k "," ";"))
|
|
7545 (if (or (not (verilog-sig-comment sig))
|
|
7546 (equal "" (verilog-sig-comment sig)))
|
|
7547 (insert "\n")
|
|
7548 (indent-to (max 48 (+ indent-pt 40)))
|
|
7549 (insert (concat "// " (verilog-sig-comment sig) "\n")))
|
|
7550 (setq sigs (cdr sigs)))))
|
|
7551
|
|
7552 (eval-when-compile
|
|
7553 (if (not (boundp 'indent-pt))
|
|
7554 (defvar indent-pt nil "Local used by insert-indent")))
|
|
7555
|
|
7556 (defun verilog-insert-indent (&rest stuff)
|
|
7557 "Indent to position stored in local `indent-pt' variable, then insert STUFF.
|
|
7558 Presumes that any newlines end a list element."
|
|
7559 (let ((need-indent t))
|
|
7560 (while stuff
|
|
7561 (if need-indent (indent-to indent-pt))
|
|
7562 (setq need-indent nil)
|
|
7563 (insert (car stuff))
|
|
7564 (setq need-indent (string-match "\n$" (car stuff))
|
|
7565 stuff (cdr stuff)))))
|
|
7566 ;;(let ((indent-pt 10)) (verilog-insert-indent "hello\n" "addon" "there\n"))
|
|
7567
|
|
7568 (defun verilog-repair-open-comma ()
|
|
7569 "If backwards-from-point is other than a open parenthesis insert comma."
|
|
7570 (save-excursion
|
|
7571 (verilog-backward-syntactic-ws)
|
|
7572 (when (save-excursion
|
|
7573 (backward-char 1)
|
|
7574 (and (not (looking-at "[(,]"))
|
|
7575 (progn
|
|
7576 (verilog-re-search-backward "[(`]" nil t)
|
|
7577 (looking-at "("))))
|
|
7578 (insert ","))))
|
|
7579
|
|
7580 (defun verilog-repair-close-comma ()
|
|
7581 "If point is at a comma followed by a close parenthesis, fix it.
|
|
7582 This repairs those mis-inserted by a AUTOARG."
|
|
7583 ;; It would be much nicer if Verilog allowed extra commas like Perl does!
|
|
7584 (save-excursion
|
|
7585 (verilog-forward-close-paren)
|
|
7586 (backward-char 1)
|
|
7587 (verilog-backward-syntactic-ws)
|
|
7588 (backward-char 1)
|
|
7589 (when (looking-at ",")
|
|
7590 (delete-char 1))))
|
|
7591
|
|
7592 (defun verilog-get-list (start end)
|
|
7593 "Return the elements of a comma separated list between START and END."
|
|
7594 (interactive)
|
|
7595 (let ((my-list (list))
|
|
7596 my-string)
|
|
7597 (save-excursion
|
|
7598 (while (< (point) end)
|
|
7599 (when (re-search-forward "\\([^,{]+\\)" end t)
|
|
7600 (setq my-string (verilog-string-remove-spaces (match-string 1)))
|
|
7601 (setq my-list (nconc my-list (list my-string) ))
|
|
7602 (goto-char (match-end 0))))
|
|
7603 my-list)))
|
|
7604
|
|
7605 (defun verilog-make-width-expression (range-exp)
|
|
7606 "Return an expression calculating the length of a range [x:y] in RANGE-EXP."
|
|
7607 ;; strip off the []
|
|
7608 (cond ((not range-exp)
|
|
7609 "1")
|
|
7610 (t
|
|
7611 (if (string-match "^\\[\\(.*\\)\\]$" range-exp)
|
|
7612 (setq range-exp (match-string 1 range-exp)))
|
|
7613 (cond ((not range-exp)
|
|
7614 "1")
|
|
7615 ((string-match "^\\s *\\([0-9]+\\)\\s *:\\s *\\([0-9]+\\)\\s *$" range-exp)
|
|
7616 (int-to-string (1+ (abs (- (string-to-int (match-string 1 range-exp))
|
|
7617 (string-to-int (match-string 2 range-exp)))))))
|
|
7618 ((string-match "^\\(.*\\)\\s *:\\s *\\(.*\\)\\s *$" range-exp)
|
|
7619 (concat "(1+(" (match-string 1 range-exp)
|
|
7620 ")"
|
|
7621 (if (equal "0" (match-string 2 range-exp)) ;; Don't bother with -(0)
|
|
7622 ""
|
|
7623 (concat "-(" (match-string 2 range-exp) ")"))
|
|
7624 ")"))
|
|
7625 (t nil)))))
|
|
7626 ;;(verilog-make-width-expression "`A:`B")
|
|
7627
|
|
7628 (defun verilog-typedef-name-p (variable-name)
|
|
7629 "Return true if the VARIABLE-NAME is a type definition."
|
|
7630 (when verilog-typedef-regexp
|
|
7631 (string-match verilog-typedef-regexp variable-name)))
|
|
7632
|
|
7633 ;;
|
|
7634 ;; Auto deletion
|
|
7635 ;;
|
|
7636
|
|
7637 (defun verilog-delete-autos-lined ()
|
|
7638 "Delete autos that occupy multiple lines, between begin and end comments."
|
|
7639 (let ((pt (point)))
|
|
7640 (forward-line 1)
|
|
7641 (when (and
|
|
7642 (looking-at "\\s-*// Beginning")
|
|
7643 (search-forward "// End of automatic" nil t))
|
|
7644 ;; End exists
|
|
7645 (end-of-line)
|
|
7646 (delete-region pt (point))
|
|
7647 (forward-line 1))
|
|
7648 ))
|
|
7649
|
|
7650 (defun verilog-forward-close-paren ()
|
|
7651 "Find the close parenthesis that match the current point,
|
|
7652 ignore other close parenthesis with matching open parens"
|
|
7653 (let ((parens 1))
|
|
7654 (while (> parens 0)
|
|
7655 (unless (verilog-re-search-forward-quick "[()]" nil t)
|
|
7656 (error "%s: Mismatching ()" (verilog-point-text)))
|
|
7657 (cond ((= (preceding-char) ?\( )
|
|
7658 (setq parens (1+ parens)))
|
|
7659 ((= (preceding-char) ?\) )
|
|
7660 (setq parens (1- parens)))))))
|
|
7661
|
|
7662 (defun verilog-backward-open-paren ()
|
|
7663 "Find the open parenthesis that match the current point,
|
|
7664 ignore other open parenthesis with matching close parens"
|
|
7665 (let ((parens 1))
|
|
7666 (while (> parens 0)
|
|
7667 (unless (verilog-re-search-backward-quick "[()]" nil t)
|
|
7668 (error "%s: Mismatching ()" (verilog-point-text)))
|
|
7669 (cond ((= (following-char) ?\) )
|
|
7670 (setq parens (1+ parens)))
|
|
7671 ((= (following-char) ?\( )
|
|
7672 (setq parens (1- parens)))))))
|
|
7673
|
|
7674 (defun verilog-backward-open-bracket ()
|
|
7675 "Find the open bracket that match the current point,
|
|
7676 ignore other open bracket with matching close bracket"
|
|
7677 (let ((parens 1))
|
|
7678 (while (> parens 0)
|
|
7679 (unless (verilog-re-search-backward-quick "[][]" nil t)
|
|
7680 (error "%s: Mismatching []" (verilog-point-text)))
|
|
7681 (cond ((= (following-char) ?\] )
|
|
7682 (setq parens (1+ parens)))
|
|
7683 ((= (following-char) ?\[ )
|
|
7684 (setq parens (1- parens)))))))
|
|
7685
|
|
7686 (defun verilog-delete-to-paren ()
|
|
7687 "Delete the automatic inst/sense/arg created by autos.
|
|
7688 Deletion stops at the matching end parenthesis."
|
|
7689 (delete-region (point)
|
|
7690 (save-excursion
|
|
7691 (verilog-backward-open-paren)
|
|
7692 (forward-sexp 1) ;; Moves to paren that closes argdecl's
|
|
7693 (backward-char 1)
|
|
7694 (point))))
|
|
7695
|
|
7696 (defun verilog-auto-star-safe ()
|
|
7697 "Return if a .* AUTOINST is safe to delete or expand.
|
|
7698 It was created by the AUTOS themselves, or by the user."
|
|
7699 (and verilog-auto-star-expand
|
|
7700 (looking-at "[ \t\n\f,]*\\([)]\\|// \\(Outputs\\|Inouts\\|Inputs\\)\\)")))
|
|
7701
|
|
7702 (defun verilog-delete-auto-star-all ()
|
|
7703 "Delete a .* AUTOINST, if it is safe."
|
|
7704 (when (verilog-auto-star-safe)
|
|
7705 (verilog-delete-to-paren)))
|
|
7706
|
|
7707 (defun verilog-delete-auto-star-implicit ()
|
|
7708 "Delete all .* implicit connections created by `verilog-auto-star'.
|
|
7709 This function will be called automatically at save unless
|
|
7710 `verilog-auto-star-save' is set, any non-templated expanded pins will be
|
|
7711 removed."
|
|
7712 (interactive)
|
|
7713 (let (paren-pt indent have-close-paren)
|
|
7714 (save-excursion
|
|
7715 (goto-char (point-min))
|
|
7716 ;; We need to match these even outside of comments.
|
|
7717 ;; For reasonable performance, we don't check if inside comments, sorry.
|
|
7718 (while (re-search-forward "// Implicit \\.\\*" nil t)
|
|
7719 (setq paren-pt (point))
|
|
7720 (beginning-of-line)
|
|
7721 (setq have-close-paren
|
|
7722 (save-excursion
|
|
7723 (when (search-forward ");" paren-pt t)
|
|
7724 (setq indent (current-indentation))
|
|
7725 t)))
|
|
7726 (delete-region (point) (+ 1 paren-pt)) ; Nuke line incl CR
|
|
7727 (when have-close-paren
|
|
7728 ;; Delete extra commentary
|
|
7729 (save-excursion
|
|
7730 (while (progn
|
|
7731 (forward-line -1)
|
|
7732 (looking-at "\\s *//\\s *\\(Outputs\\|Inouts\\|Inputs\\)\n"))
|
|
7733 (delete-region (match-beginning 0) (match-end 0))))
|
|
7734 ;; If it is simple, we can put the ); on the same line as the last text
|
|
7735 (let ((rtn-pt (point)))
|
|
7736 (save-excursion
|
|
7737 (while (progn (backward-char 1)
|
|
7738 (looking-at "[ \t\n\f]")))
|
|
7739 (when (looking-at ",")
|
|
7740 (delete-region (+ 1 (point)) rtn-pt))))
|
|
7741 (when (bolp)
|
|
7742 (indent-to indent))
|
|
7743 (insert ");\n")
|
|
7744 ;; Still need to kill final comma - always is one as we put one after the .*
|
|
7745 (re-search-backward ",")
|
|
7746 (delete-char 1))))))
|
|
7747
|
|
7748 (defun verilog-delete-auto ()
|
|
7749 "Delete the automatic outputs, regs, and wires created by \\[verilog-auto].
|
|
7750 Use \\[verilog-auto] to re-insert the updated AUTOs.
|
|
7751
|
|
7752 The hooks `verilog-before-delete-auto-hook' and `verilog-delete-auto-hook' are
|
|
7753 called before and after this function, respectively."
|
|
7754 (interactive)
|
|
7755 (save-excursion
|
|
7756 (if (buffer-file-name)
|
|
7757 (find-file-noselect (buffer-file-name))) ;; To check we have latest version
|
|
7758 ;; Allow user to customize
|
|
7759 (run-hooks 'verilog-before-delete-auto-hook)
|
|
7760
|
|
7761 ;; Remove those that have multi-line insertions
|
|
7762 (verilog-auto-re-search-do "/\\*AUTO\\(OUTPUTEVERY\\|CONCATCOMMENT\\|WIRE\\|REG\\|DEFINEVALUE\\|REGINPUT\\|INPUT\\|OUTPUT\\|INOUT\\|RESET\\|TIEOFF\\|UNUSED\\)\\*/"
|
|
7763 'verilog-delete-autos-lined)
|
|
7764 ;; Remove those that have multi-line insertions with parameters
|
|
7765 (verilog-auto-re-search-do "/\\*AUTO\\(INOUTMODULE\\|ASCIIENUM\\)([^)]*)\\*/"
|
|
7766 'verilog-delete-autos-lined)
|
|
7767 ;; Remove those that are in parenthesis
|
|
7768 (verilog-auto-re-search-do "/\\*\\(AS\\|AUTO\\(ARG\\|CONCATWIDTH\\|INST\\|INSTPARAM\\|SENSE\\)\\)\\*/"
|
|
7769 'verilog-delete-to-paren)
|
|
7770 ;; Do .* instantiations, but avoid removing any user pins by looking for our magic comments
|
|
7771 (verilog-auto-re-search-do "\\.\\*"
|
|
7772 'verilog-delete-auto-star-all)
|
|
7773 ;; Remove template comments ... anywhere in case was pasted after AUTOINST removed
|
|
7774 (goto-char (point-min))
|
|
7775 (while (re-search-forward "\\s-*// \\(Templated\\|Implicit \\.\\*\\)[ \tLT0-9]*$" nil t)
|
|
7776 (replace-match ""))
|
|
7777
|
|
7778 ;; Final customize
|
|
7779 (run-hooks 'verilog-delete-auto-hook)))
|
|
7780
|
|
7781 ;;
|
|
7782 ;; Auto inject
|
|
7783 ;;
|
|
7784
|
|
7785 (defun verilog-inject-auto ()
|
|
7786 "Examine legacy non-AUTO code and insert AUTOs in appropriate places.
|
|
7787
|
|
7788 Any always @ blocks with sensitivity lists that match computed lists will
|
|
7789 be replaced with /*AS*/ comments.
|
|
7790
|
|
7791 Any cells will get /*AUTOINST*/ added to the end of the pin list. Pins with
|
|
7792 have identical names will be deleted.
|
|
7793
|
|
7794 Argument lists will not be deleted, /*AUTOARG*/ will only be inserted to
|
|
7795 support adding new ports. You may wish to delete older ports yourself.
|
|
7796
|
|
7797 For example:
|
|
7798
|
|
7799 module ex_inject (i, o);
|
|
7800 input i;
|
|
7801 input j;
|
|
7802 output o;
|
|
7803 always @ (i or j)
|
|
7804 o = i | j;
|
|
7805 cell cell (.foobar(baz),
|
|
7806 .j(j));
|
|
7807 endmodule
|
|
7808
|
|
7809 Typing \\[verilog-inject-auto] will make this into:
|
|
7810
|
|
7811 module ex_inject (i, o/*AUTOARG*/
|
|
7812 // Inputs
|
|
7813 j);
|
|
7814 input i;
|
|
7815 output o;
|
|
7816 always @ (/*AS*/i or j)
|
|
7817 o = i | j;
|
|
7818 cell cell (.foobar(baz),
|
|
7819 /*AUTOINST*/
|
|
7820 // Outputs
|
|
7821 .j(j));
|
|
7822 endmodule"
|
|
7823 (interactive)
|
|
7824 (verilog-auto t))
|
|
7825
|
|
7826 (defun verilog-inject-arg ()
|
|
7827 "Inject AUTOARG into new code. See `verilog-inject-auto'."
|
|
7828 ;; Presume one module per file.
|
|
7829 (save-excursion
|
|
7830 (goto-char (point-min))
|
|
7831 (while (verilog-re-search-forward-quick "\\<module\\>" nil t)
|
|
7832 (let ((endmodp (save-excursion
|
|
7833 (verilog-re-search-forward-quick "\\<endmodule\\>" nil t)
|
|
7834 (point))))
|
|
7835 ;; See if there's already a comment .. inside a comment so not verilog-re-search
|
|
7836 (when (not (re-search-forward "/\\*AUTOARG\\*/" endmodp t))
|
|
7837 (verilog-re-search-forward-quick ";" nil t)
|
|
7838 (backward-char 1)
|
|
7839 (verilog-backward-syntactic-ws)
|
|
7840 (backward-char 1) ; Moves to paren that closes argdecl's
|
|
7841 (when (looking-at ")")
|
|
7842 (insert "/*AUTOARG*/")))))))
|
|
7843
|
|
7844 (defun verilog-inject-sense ()
|
|
7845 "Inject AUTOSENSE into new code. See `verilog-inject-auto'."
|
|
7846 (save-excursion
|
|
7847 (goto-char (point-min))
|
|
7848 (while (verilog-re-search-forward-quick "\\<always\\s *@\\s *(" nil t)
|
|
7849 (let ((start-pt (point))
|
|
7850 (modi (verilog-modi-current))
|
|
7851 pre-sigs
|
|
7852 got-sigs)
|
|
7853 (backward-char 1)
|
|
7854 (forward-sexp 1)
|
|
7855 (backward-char 1) ;; End )
|
|
7856 (when (not (verilog-re-search-backward "/\\*\\(AUTOSENSE\\|AS\\)\\*/" start-pt t))
|
|
7857 (setq pre-sigs (verilog-signals-from-signame
|
|
7858 (verilog-read-signals start-pt (point)))
|
|
7859 got-sigs (verilog-auto-sense-sigs modi nil))
|
|
7860 (when (not (or (verilog-signals-not-in pre-sigs got-sigs) ; Both are equal?
|
|
7861 (verilog-signals-not-in got-sigs pre-sigs)))
|
|
7862 (delete-region start-pt (point))
|
|
7863 (insert "/*AS*/")))))))
|
|
7864
|
|
7865 (defun verilog-inject-inst ()
|
|
7866 "Inject AUTOINST into new code. See `verilog-inject-auto'."
|
|
7867 (save-excursion
|
|
7868 (goto-char (point-min))
|
|
7869 ;; It's hard to distinguish modules; we'll instead search for pins.
|
|
7870 (while (verilog-re-search-forward-quick "\\.\\s *[a-zA-Z0-9`_\$]+\\s *(\\s *[a-zA-Z0-9`_\$]+\\s *)" nil t)
|
|
7871 (verilog-backward-open-paren) ;; Inst start
|
|
7872 (cond
|
|
7873 ((= (preceding-char) ?\#) ;; #(...) parameter section, not pin. Skip.
|
|
7874 (forward-char 1)
|
|
7875 (verilog-forward-close-paren)) ;; Parameters done
|
|
7876 (t
|
|
7877 (forward-char 1)
|
|
7878 (let ((indent-pt (+ (current-column)))
|
|
7879 (end-pt (save-excursion (verilog-forward-close-paren) (point))))
|
|
7880 (cond ((verilog-re-search-forward "\\(/\\*AUTOINST\\*/\\|\\.\\*\\)" end-pt t)
|
|
7881 (goto-char end-pt)) ;; Already there, continue search with next instance
|
|
7882 (t
|
|
7883 ;; Delete identical interconnect
|
|
7884 (let ((case-fold-search nil)) ;; So we don't convert upper-to-lower, etc
|
|
7885 (while (verilog-re-search-forward "\\.\\s *\\([a-zA-Z0-9`_\$]+\\)*\\s *(\\s *\\1\\s *)\\s *" end-pt t)
|
|
7886 (delete-region (match-beginning 0) (match-end 0))
|
|
7887 (setq end-pt (- end-pt (- (match-end 0) (match-beginning 0)))) ;; Keep it correct
|
|
7888 (while (or (looking-at "[ \t\n\f,]+")
|
|
7889 (looking-at "//[^\n]*"))
|
|
7890 (delete-region (match-beginning 0) (match-end 0))
|
|
7891 (setq end-pt (- end-pt (- (match-end 0) (match-beginning 0)))))))
|
|
7892 (verilog-forward-close-paren)
|
|
7893 (backward-char 1)
|
|
7894 ;; Not verilog-re-search, as we don't want to strip comments
|
|
7895 (while (re-search-backward "[ \t\n\f]+" (- (point) 1) t)
|
|
7896 (delete-region (match-beginning 0) (match-end 0)))
|
|
7897 (insert "\n")
|
|
7898 (indent-to indent-pt)
|
|
7899 (insert "/*AUTOINST*/")))))))))
|
|
7900
|
|
7901 ;;
|
|
7902 ;; Auto save
|
|
7903 ;;
|
|
7904
|
|
7905 (defun verilog-auto-save-check ()
|
|
7906 "On saving see if we need auto update."
|
|
7907 (cond ((not verilog-auto-save-policy)) ; disabled
|
|
7908 ((not (save-excursion
|
|
7909 (save-match-data
|
|
7910 (let ((case-fold-search nil))
|
|
7911 (goto-char (point-min))
|
|
7912 (re-search-forward "AUTO" nil t))))))
|
|
7913 ((eq verilog-auto-save-policy 'force)
|
|
7914 (verilog-auto))
|
|
7915 ((not (buffer-modified-p)))
|
|
7916 ((eq verilog-auto-update-tick (buffer-modified-tick))) ; up-to-date
|
|
7917 ((eq verilog-auto-save-policy 'detect)
|
|
7918 (verilog-auto))
|
|
7919 (t
|
|
7920 (when (yes-or-no-p "AUTO statements not recomputed, do it now? ")
|
|
7921 (verilog-auto))
|
|
7922 ;; Don't ask again if didn't update
|
|
7923 (set (make-local-variable 'verilog-auto-update-tick) (buffer-modified-tick))
|
|
7924 ))
|
|
7925 (when (not verilog-auto-star-save)
|
|
7926 (verilog-delete-auto-star-implicit))
|
|
7927 nil) ;; Always return nil -- we don't write the file ourselves
|
|
7928
|
|
7929 (defun verilog-auto-read-locals ()
|
|
7930 "Return file local variable segment at bottom of file."
|
|
7931 (save-excursion
|
|
7932 (goto-char (point-max))
|
|
7933 (if (re-search-backward "Local Variables:" nil t)
|
|
7934 (buffer-substring-no-properties (point) (point-max))
|
|
7935 "")))
|
|
7936
|
|
7937 (defun verilog-auto-reeval-locals (&optional force)
|
|
7938 "Read file local variable segment at bottom of file if it has changed.
|
|
7939 If FORCE, always reread it."
|
|
7940 (make-variable-buffer-local 'verilog-auto-last-file-locals)
|
|
7941 (let ((curlocal (verilog-auto-read-locals)))
|
|
7942 (when (or force (not (equal verilog-auto-last-file-locals curlocal)))
|
|
7943 (setq verilog-auto-last-file-locals curlocal)
|
|
7944 ;; Note this may cause this function to be recursively invoked.
|
|
7945 ;; The above when statement will prevent it from recursing forever.
|
|
7946 (hack-local-variables)
|
|
7947 t)))
|
|
7948
|
|
7949 ;;
|
|
7950 ;; Auto creation
|
|
7951 ;;
|
|
7952
|
|
7953 (defun verilog-auto-arg-ports (sigs message indent-pt)
|
|
7954 "Print a list of ports for a AUTOINST.
|
|
7955 Takes SIGS list, adds MESSAGE to front and inserts each at INDENT-PT."
|
|
7956 (when sigs
|
|
7957 (insert "\n")
|
|
7958 (indent-to indent-pt)
|
|
7959 (insert message)
|
|
7960 (insert "\n")
|
|
7961 (let ((space ""))
|
|
7962 (indent-to indent-pt)
|
|
7963 (while sigs
|
|
7964 (cond ((> (+ 2 (current-column) (length (verilog-sig-name (car sigs)))) fill-column)
|
|
7965 (insert "\n")
|
|
7966 (indent-to indent-pt))
|
|
7967 (t (insert space)))
|
|
7968 (insert (verilog-sig-name (car sigs)) ",")
|
|
7969 (setq sigs (cdr sigs)
|
|
7970 space " ")))))
|
|
7971
|
|
7972 (defun verilog-auto-arg ()
|
|
7973 "Expand AUTOARG statements.
|
|
7974 Replace the argument declarations at the beginning of the
|
|
7975 module with ones automatically derived from input and output
|
|
7976 statements. This can be dangerous if the module is instantiated
|
|
7977 using position-based connections, so use only name-based when
|
|
7978 instantiating the resulting module. Long lines are split based
|
|
7979 on the `fill-column', see \\[set-fill-column].
|
|
7980
|
|
7981 Limitations:
|
|
7982 Concatenation and outputting partial busses is not supported.
|
|
7983
|
|
7984 Typedefs must match `verilog-typedef-regexp', which is disabled by default.
|
|
7985
|
|
7986 For example:
|
|
7987
|
|
7988 module ex_arg (/*AUTOARG*/);
|
|
7989 input i;
|
|
7990 output o;
|
|
7991 endmodule
|
|
7992
|
|
7993 Typing \\[verilog-auto] will make this into:
|
|
7994
|
|
7995 module ex_arg (/*AUTOARG*/
|
|
7996 // Outputs
|
|
7997 o,
|
|
7998 // Inputs
|
|
7999 i
|
|
8000 );
|
|
8001 input i;
|
|
8002 output o;
|
|
8003 endmodule
|
|
8004
|
|
8005 Any ports declared between the ( and /*AUTOARG*/ are presumed to be
|
|
8006 predeclared and are not redeclared by AUTOARG. AUTOARG will make a
|
|
8007 conservative guess on adding a comma for the first signal, if you have any
|
|
8008 ifdefs or complicated expressions before the AUTOARG you will need to
|
|
8009 choose the comma yourself.
|
|
8010
|
|
8011 Avoid declaring ports manually, as it makes code harder to maintain."
|
|
8012 (save-excursion
|
|
8013 (let ((modi (verilog-modi-current))
|
|
8014 (skip-pins (aref (verilog-read-arg-pins) 0)))
|
|
8015 (verilog-repair-open-comma)
|
|
8016 (verilog-auto-arg-ports (verilog-signals-not-in
|
|
8017 (verilog-modi-get-outputs modi)
|
|
8018 skip-pins)
|
|
8019 "// Outputs"
|
|
8020 verilog-indent-level-declaration)
|
|
8021 (verilog-auto-arg-ports (verilog-signals-not-in
|
|
8022 (verilog-modi-get-inouts modi)
|
|
8023 skip-pins)
|
|
8024 "// Inouts"
|
|
8025 verilog-indent-level-declaration)
|
|
8026 (verilog-auto-arg-ports (verilog-signals-not-in
|
|
8027 (verilog-modi-get-inputs modi)
|
|
8028 skip-pins)
|
|
8029 "// Inputs"
|
|
8030 verilog-indent-level-declaration)
|
|
8031 (verilog-repair-close-comma)
|
|
8032 (unless (eq (char-before) ?/ )
|
|
8033 (insert "\n"))
|
|
8034 (indent-to verilog-indent-level-declaration)
|
|
8035 )))
|
|
8036
|
|
8037 (defun verilog-auto-inst-port-map (port-st)
|
|
8038 nil)
|
|
8039
|
|
8040 (defvar vector-skip-list nil) ; Prevent compile warning
|
|
8041 (defvar vl-cell-type nil "See `verilog-auto-inst'.") ; Prevent compile warning
|
|
8042 (defvar vl-cell-name nil "See `verilog-auto-inst'.") ; Prevent compile warning
|
|
8043 (defvar vl-name nil "See `verilog-auto-inst'.") ; Prevent compile warning
|
|
8044 (defvar vl-width nil "See `verilog-auto-inst'.") ; Prevent compile warning
|
|
8045 (defvar vl-dir nil "See `verilog-auto-inst'.") ; Prevent compile warning
|
|
8046
|
|
8047 (defun verilog-auto-inst-port (port-st indent-pt tpl-list tpl-num for-star)
|
|
8048 "Print out a instantiation connection for this PORT-ST.
|
|
8049 Insert to INDENT-PT, use template TPL-LIST.
|
|
8050 @ are instantiation numbers, replaced with TPL-NUM.
|
|
8051 @\"(expression @)\" are evaluated, with @ as a variable."
|
|
8052 (let* ((port (verilog-sig-name port-st))
|
|
8053 (tpl-ass (or (assoc port (car tpl-list))
|
|
8054 (verilog-auto-inst-port-map port-st)))
|
|
8055 ;; vl-* are documented for user use
|
|
8056 (vl-name (verilog-sig-name port-st))
|
|
8057 (vl-width (verilog-sig-width port-st))
|
|
8058 (vl-bits (if (or verilog-auto-inst-vector
|
|
8059 (not (assoc port vector-skip-list))
|
|
8060 (not (equal (verilog-sig-bits port-st)
|
|
8061 (verilog-sig-bits (assoc port vector-skip-list)))))
|
|
8062 (or (verilog-sig-bits port-st) "")
|
|
8063 ""))
|
|
8064 ;; Default if not found
|
|
8065 (tpl-net (if (verilog-sig-multidim port-st)
|
|
8066 (concat port "/*" (verilog-sig-multidim-string port-st)
|
|
8067 vl-bits "*/")
|
|
8068 (concat port vl-bits)))
|
|
8069 (case-fold-search nil))
|
|
8070 ;; Find template
|
|
8071 (cond (tpl-ass ; Template of exact port name
|
|
8072 (setq tpl-net (nth 1 tpl-ass)))
|
|
8073 ((nth 1 tpl-list) ; Wildcards in template, search them
|
|
8074 (let ((wildcards (nth 1 tpl-list)))
|
|
8075 (while wildcards
|
|
8076 (when (string-match (nth 0 (car wildcards)) port)
|
|
8077 (setq tpl-ass (car wildcards) ; so allow @ parsing
|
|
8078 tpl-net (replace-match (nth 1 (car wildcards))
|
|
8079 t nil port)))
|
|
8080 (setq wildcards (cdr wildcards))))))
|
|
8081 ;; Parse Templated variable
|
|
8082 (when tpl-ass
|
|
8083 ;; Evaluate @"(lispcode)"
|
|
8084 (when (string-match "@\".*[^\\]\"" tpl-net)
|
|
8085 (while (string-match "@\"\\(\\([^\\\"]*\\(\\\\.\\)*\\)*\\)\"" tpl-net)
|
|
8086 (setq tpl-net
|
|
8087 (concat
|
|
8088 (substring tpl-net 0 (match-beginning 0))
|
|
8089 (save-match-data
|
|
8090 (let* ((expr (match-string 1 tpl-net))
|
|
8091 (value
|
|
8092 (progn
|
|
8093 (setq expr (verilog-string-replace-matches "\\\\\"" "\"" nil nil expr))
|
|
8094 (setq expr (verilog-string-replace-matches "@" tpl-num nil nil expr))
|
|
8095 (prin1 (eval (car (read-from-string expr)))
|
|
8096 (lambda (ch) ())))))
|
|
8097 (if (numberp value) (setq value (number-to-string value)))
|
|
8098 value
|
|
8099 ))
|
|
8100 (substring tpl-net (match-end 0))))))
|
|
8101 ;; Replace @ and [] magic variables in final output
|
|
8102 (setq tpl-net (verilog-string-replace-matches "@" tpl-num nil nil tpl-net))
|
|
8103 (setq tpl-net (verilog-string-replace-matches "\\[\\]" vl-bits nil nil tpl-net))
|
|
8104 )
|
|
8105 (indent-to indent-pt)
|
|
8106 (insert "." port)
|
|
8107 (indent-to verilog-auto-inst-column)
|
|
8108 (insert "(" tpl-net "),")
|
|
8109 (cond (tpl-ass
|
|
8110 (indent-to (+ (if (< verilog-auto-inst-column 48) 24 16)
|
|
8111 verilog-auto-inst-column))
|
|
8112 (insert " // Templated")
|
|
8113 (when verilog-auto-inst-template-numbers
|
|
8114 (insert " T" (int-to-string (nth 2 tpl-ass))
|
|
8115 " L" (int-to-string (nth 3 tpl-ass)))))
|
|
8116 (for-star
|
|
8117 (indent-to (+ (if (< verilog-auto-inst-column 48) 24 16)
|
|
8118 verilog-auto-inst-column))
|
|
8119 (insert " // Implicit .\*"))) ;For some reason the . or * must be escaped...
|
|
8120 (insert "\n")))
|
|
8121 ;;(verilog-auto-inst-port (list "foo" "[5:0]") 10 (list (list "foo" "a@\"(% (+ @ 1) 4)\"a")) "3")
|
|
8122 ;;(x "incom[@\"(+ (* 8 @) 7)\":@\"(* 8 @)\"]")
|
|
8123 ;;(x ".out (outgo[@\"(concat (+ (* 8 @) 7) \\\":\\\" ( * 8 @))\"]));")
|
|
8124
|
|
8125 (defun verilog-auto-inst-first ()
|
|
8126 "Insert , etc before first ever port in this instant, as part of \\[verilog-auto-inst]."
|
|
8127 ;; Do we need a trailing comma?
|
|
8128 ;; There maybe a ifdef or something similar before us. What a mess. Thus
|
|
8129 ;; to avoid trouble we only insert on preceeding ) or *.
|
|
8130 ;; Insert first port on new line
|
|
8131 (insert "\n") ;; Must insert before search, so point will move forward if insert comma
|
|
8132 (save-excursion
|
|
8133 (verilog-re-search-backward "[^ \t\n\f]" nil nil)
|
|
8134 (when (looking-at ")\\|\\*") ;; Generally don't insert, unless we are fairly sure
|
|
8135 (forward-char 1)
|
|
8136 (insert ","))))
|
|
8137
|
|
8138 (defun verilog-auto-star ()
|
|
8139 "Expand SystemVerilog .* pins, as part of \\[verilog-auto].
|
|
8140
|
|
8141 If `verilog-auto-star-expand' is set, .* pins are treated if they were
|
|
8142 AUTOINST statements, otherwise they are ignored. For safety, Verilog-Mode
|
|
8143 will also ignore any .* that are not last in your pin list (this prevents
|
|
8144 it from deleting pins following the .* when it expands the AUTOINST.)
|
|
8145
|
|
8146 On writing your file, unless `verilog-auto-star-save' is set, any
|
|
8147 non-templated expanded pins will be removed. You may do this at any time
|
|
8148 with \\[verilog-delete-auto-star-implicit].
|
|
8149
|
|
8150 If you are converting a module to use .* for the first time, you may wish
|
|
8151 to use \\[verilog-inject-auto] and then replace the created AUTOINST with .*.
|
|
8152
|
|
8153 See `verilog-auto-inst' for examples, templates, and more information."
|
|
8154 (when (verilog-auto-star-safe)
|
|
8155 (verilog-auto-inst)))
|
|
8156
|
|
8157 (defun verilog-auto-inst ()
|
|
8158 "Expand AUTOINST statements, as part of \\[verilog-auto].
|
|
8159 Replace the pin connections to an instantiation with ones
|
|
8160 automatically derived from the module header of the instantiated netlist.
|
|
8161
|
|
8162 If `verilog-auto-star-expand' is set, also expand SystemVerilog .* ports,
|
|
8163 and delete them before saving unless `verilog-auto-star-save' is set.
|
|
8164 See `verilog-auto-star' for more information.
|
|
8165
|
|
8166 Limitations:
|
|
8167 Module names must be resolvable to filenames by adding a
|
|
8168 `verilog-library-extensions', and being found in the same directory, or
|
|
8169 by changing the variable `verilog-library-flags' or
|
|
8170 `verilog-library-directories'. Macros `modname are translated through the
|
|
8171 vh-{name} Emacs variable, if that is not found, it just ignores the `.
|
|
8172
|
|
8173 In templates you must have one signal per line, ending in a ), or ));,
|
|
8174 and have proper () nesting, including a final ); to end the template.
|
|
8175
|
|
8176 Typedefs must match `verilog-typedef-regexp', which is disabled by default.
|
|
8177
|
|
8178 SystemVerilog multidimmensional input/output has only experimental support.
|
|
8179
|
|
8180 For example, first take the submodule inst.v:
|
|
8181
|
|
8182 module inst (o,i)
|
|
8183 output [31:0] o;
|
|
8184 input i;
|
|
8185 wire [31:0] o = {32{i}};
|
|
8186 endmodule
|
|
8187
|
|
8188 This is then used in a upper level module:
|
|
8189
|
|
8190 module ex_inst (o,i)
|
|
8191 output o;
|
|
8192 input i;
|
|
8193 inst inst (/*AUTOINST*/);
|
|
8194 endmodule
|
|
8195
|
|
8196 Typing \\[verilog-auto] will make this into:
|
|
8197
|
|
8198 module ex_inst (o,i)
|
|
8199 output o;
|
|
8200 input i;
|
|
8201 inst inst (/*AUTOINST*/
|
|
8202 // Outputs
|
|
8203 .ov (ov[31:0]),
|
|
8204 // Inputs
|
|
8205 .i (i));
|
|
8206 endmodule
|
|
8207
|
|
8208 Where the list of inputs and outputs came from the inst module.
|
|
8209
|
|
8210 Exceptions:
|
|
8211
|
|
8212 Unless you are instantiating a module multiple times, or the module is
|
|
8213 something trivial like a adder, DO NOT CHANGE SIGNAL NAMES ACROSS HIERARCHY.
|
|
8214 It just makes for unmaintainable code. To sanitize signal names, try
|
|
8215 vrename from http://www.veripool.com
|
|
8216
|
|
8217 When you need to violate this suggestion there are two ways to list
|
|
8218 exceptions, placing them before the AUTOINST, or using templates.
|
|
8219
|
|
8220 Any ports defined before the /*AUTOINST*/ are not included in the list of
|
|
8221 automatics. This is similar to making a template as described below, but
|
|
8222 is restricted to simple connections just like you normally make. Also note
|
|
8223 that any signals before the AUTOINST will only be picked up by AUTOWIRE if
|
|
8224 you have the appropriate // Input or // Output comment, and exactly the
|
|
8225 same line formatting as AUTOINST itself uses.
|
|
8226
|
|
8227 inst inst (// Inputs
|
|
8228 .i (my_i_dont_mess_with_it),
|
|
8229 /*AUTOINST*/
|
|
8230 // Outputs
|
|
8231 .ov (ov[31:0]));
|
|
8232
|
|
8233
|
|
8234 Templates:
|
|
8235
|
|
8236 For multiple instantiations based upon a single template, create a
|
|
8237 commented out template:
|
|
8238
|
|
8239 /* instantiating_module_name AUTO_TEMPLATE (
|
|
8240 .sig3 (sigz[]),
|
|
8241 );
|
|
8242 */
|
|
8243
|
|
8244 Templates go ABOVE the instantiation(s). When a instantiation is
|
|
8245 expanded `verilog-mode' simply searches up for the closest template.
|
|
8246 Thus you can have multiple templates for the same module, just alternate
|
|
8247 between the template for a instantiation and the instantiation itself.
|
|
8248
|
|
8249 The module name must be the same as the name of the module in the
|
|
8250 instantiation name, and the code \"AUTO_TEMPLATE\" must be in these exact
|
|
8251 words and capitalized. Only signals that must be different for each
|
|
8252 instantiation need to be listed.
|
|
8253
|
|
8254 Inside a template, a [] in a connection name (with nothing else inside
|
|
8255 the brackets) will be replaced by the same bus subscript as it is being
|
|
8256 connected to, or the [] will be removed if it is a single bit signal.
|
|
8257 Generally it is a good idea to do this for all connections in a template,
|
|
8258 as then they will work for any width signal, and with AUTOWIRE. See
|
|
8259 PTL_BUS becoming PTL_BUSNEW below.
|
|
8260
|
|
8261 If you have a complicated template, set `verilog-auto-inst-template-numbers'
|
|
8262 to see which regexps are matching. Don't leave that mode set after
|
|
8263 debugging is completed though, it will result in lots of extra differences
|
|
8264 and merge conflicts.
|
|
8265
|
|
8266 For example:
|
|
8267
|
|
8268 /* psm_mas AUTO_TEMPLATE (
|
|
8269 .ptl_bus (ptl_busnew[]),
|
|
8270 );
|
|
8271 */
|
|
8272 psm_mas ms2m (/*AUTOINST*/);
|
|
8273
|
|
8274 Typing \\[verilog-auto] will make this into:
|
|
8275
|
|
8276 psm_mas ms2m (/*AUTOINST*/
|
|
8277 // Outputs
|
|
8278 .NotInTemplate (NotInTemplate),
|
|
8279 .ptl_bus (ptl_busnew[3:0]), // Templated
|
|
8280 ....
|
|
8281
|
|
8282 @ Templates:
|
|
8283
|
|
8284 It is common to instantiate a cell multiple times, so templates make it
|
|
8285 trivial to substitute part of the cell name into the connection name.
|
|
8286
|
|
8287 /* cell_type AUTO_TEMPLATE <optional \"REGEXP\"> (
|
|
8288 .sig1 (sigx[@]),
|
|
8289 .sig2 (sigy[@\"(% (+ 1 @) 4)\"]),
|
|
8290 );
|
|
8291 */
|
|
8292
|
|
8293 If no regular expression is provided immediately after the AUTO_TEMPLATE
|
|
8294 keyword, then the @ character in any connection names will be replaced
|
|
8295 with the instantiation number; the first digits found in the cell's
|
|
8296 instantiation name.
|
|
8297
|
|
8298 If a regular expression is provided, the @ character will be replaced
|
|
8299 with the first \(\) grouping that matches against the cell name. Using a
|
|
8300 regexp of \"\\([0-9]+\\)\" provides identical values for @ as when no
|
|
8301 regexp is provided. If you use multiple layers of parenthesis,
|
|
8302 \"test\\([^0-9]+\\)_\\([0-9]+\\)\" would replace @ with non-number
|
|
8303 characters after test and before _, whereas
|
|
8304 \"\\(test\\([a-z]+\\)_\\([0-9]+\\)\\)\" would replace @ with the entire
|
|
8305 match.
|
|
8306
|
|
8307 For example:
|
|
8308
|
|
8309 /* psm_mas AUTO_TEMPLATE (
|
|
8310 .ptl_mapvalidx (ptl_mapvalid[@]),
|
|
8311 .ptl_mapvalidp1x (ptl_mapvalid[@\"(% (+ 1 @) 4)\"]),
|
|
8312 );
|
|
8313 */
|
|
8314 psm_mas ms2m (/*AUTOINST*/);
|
|
8315
|
|
8316 Typing \\[verilog-auto] will make this into:
|
|
8317
|
|
8318 psm_mas ms2m (/*AUTOINST*/
|
|
8319 // Outputs
|
|
8320 .ptl_mapvalidx (ptl_mapvalid[2]),
|
|
8321 .ptl_mapvalidp1x (ptl_mapvalid[3]));
|
|
8322
|
|
8323 Note the @ character was replaced with the 2 from \"ms2m\".
|
|
8324
|
|
8325 Alternatively, using a regular expression for @:
|
|
8326
|
|
8327 /* psm_mas AUTO_TEMPLATE \"_\\([a-z]+\\)\" (
|
|
8328 .ptl_mapvalidx (@_ptl_mapvalid),
|
|
8329 .ptl_mapvalidp1x (ptl_mapvalid_@),
|
|
8330 );
|
|
8331 */
|
|
8332 psm_mas ms2_FOO (/*AUTOINST*/);
|
|
8333 psm_mas ms2_BAR (/*AUTOINST*/);
|
|
8334
|
|
8335 Typing \\[verilog-auto] will make this into:
|
|
8336
|
|
8337 psm_mas ms2_FOO (/*AUTOINST*/
|
|
8338 // Outputs
|
|
8339 .ptl_mapvalidx (FOO_ptl_mapvalid),
|
|
8340 .ptl_mapvalidp1x (ptl_mapvalid_FOO));
|
|
8341 psm_mas ms2_BAR (/*AUTOINST*/
|
|
8342 // Outputs
|
|
8343 .ptl_mapvalidx (BAR_ptl_mapvalid),
|
|
8344 .ptl_mapvalidp1x (ptl_mapvalid_BAR));
|
|
8345
|
|
8346
|
|
8347 Regexp Templates:
|
|
8348
|
|
8349 A template entry of the form
|
|
8350
|
|
8351 .pci_req\\([0-9]+\\)_l (pci_req_jtag_[\\1]),
|
|
8352
|
|
8353 will apply a Emacs style regular expression search for any port beginning
|
|
8354 in pci_req followed by numbers and ending in _l and connecting that to
|
|
8355 the pci_req_jtag_[] net, with the bus subscript coming from what matches
|
|
8356 inside the first set of \\( \\). Thus pci_req2_l becomes pci_req_jtag_[2].
|
|
8357
|
|
8358 Since \\([0-9]+\\) is so common and ugly to read, a @ in the port name
|
|
8359 does the same thing. (Note a @ in the connection/replacement text is
|
|
8360 completely different -- still use \\1 there!) Thus this is the same as
|
|
8361 the above template:
|
|
8362
|
|
8363 .pci_req@_l (pci_req_jtag_[\\1]),
|
|
8364
|
|
8365 Here's another example to remove the _l, useful when naming conventions
|
|
8366 specify _ alone to mean active low. Note the use of [] to keep the bus
|
|
8367 subscript:
|
|
8368
|
|
8369 .\\(.*\\)_l (\\1_[]),
|
|
8370
|
|
8371 Lisp Templates:
|
|
8372
|
|
8373 First any regular expression template is expanded.
|
|
8374
|
|
8375 If the syntax @\"( ... )\" is found in a connection, the expression in
|
|
8376 quotes will be evaluated as a Lisp expression, with @ replaced by the
|
|
8377 instantiation number. The MAPVALIDP1X example above would put @+1 modulo
|
|
8378 4 into the brackets. Quote all double-quotes inside the expression with
|
|
8379 a leading backslash (\\\"). There are special variables defined that are
|
|
8380 useful in these Lisp functions:
|
|
8381
|
|
8382 vl-name Name portion of the input/output port
|
|
8383 vl-bits Bus bits portion of the input/output port ('[2:0]')
|
|
8384 vl-width Width of the input/output port ('3' for [2:0])
|
|
8385 May be a (...) expression if bits isn't a constant.
|
|
8386 vl-dir Direction of the pin input/output/inout.
|
|
8387 vl-cell-type Module name/type of the cell ('psm_mas')
|
|
8388 vl-cell-name Instance name of the cell ('ms2m')
|
|
8389
|
|
8390 Normal Lisp variables may be used in expressions. See
|
|
8391 `verilog-read-defines' which can set vh-{definename} variables for use
|
|
8392 here. Also, any comments of the form:
|
|
8393
|
|
8394 /*AUTO_LISP(setq foo 1)*/
|
|
8395
|
|
8396 will evaluate any Lisp expression inside the parenthesis between the
|
|
8397 beginning of the buffer and the point of the AUTOINST. This allows
|
|
8398 functions to be defined or variables to be changed between instantiations.
|
|
8399
|
|
8400 Note that when using lisp expressions errors may occur when @ is not a
|
|
8401 number, you may need to use the standard Emacs Lisp functions
|
|
8402 `number-to-string' and `string-to-number'.
|
|
8403
|
|
8404 After the evaluation is completed, @ substitution and [] substitution
|
|
8405 occur."
|
|
8406 (save-excursion
|
|
8407 ;; Find beginning
|
|
8408 (let* ((pt (point))
|
|
8409 (for-star (save-excursion (backward-char 2) (looking-at "\\.\\*")))
|
|
8410 (indent-pt (save-excursion (verilog-backward-open-paren)
|
|
8411 (1+ (current-column))))
|
|
8412 (verilog-auto-inst-column (max verilog-auto-inst-column
|
|
8413 (+ 16 (* 8 (/ (+ indent-pt 7) 8)))))
|
|
8414 (modi (verilog-modi-current))
|
|
8415 (vector-skip-list (unless verilog-auto-inst-vector
|
|
8416 (verilog-modi-get-signals modi)))
|
|
8417 submod submodi inst skip-pins tpl-list tpl-num did-first)
|
|
8418 ;; Find module name that is instantiated
|
|
8419 (setq submod (verilog-read-inst-module)
|
|
8420 inst (verilog-read-inst-name)
|
|
8421 vl-cell-type submod
|
|
8422 vl-cell-name inst
|
|
8423 skip-pins (aref (verilog-read-inst-pins) 0))
|
|
8424
|
|
8425 ;; Parse any AUTO_LISP() before here
|
|
8426 (verilog-read-auto-lisp (point-min) pt)
|
|
8427
|
|
8428 ;; Lookup position, etc of submodule
|
|
8429 ;; Note this may raise an error
|
|
8430 (when (setq submodi (verilog-modi-lookup submod t))
|
|
8431 ;; If there's a number in the instantiation, it may be a argument to the
|
|
8432 ;; automatic variable instantiation program.
|
|
8433 (let* ((tpl-info (verilog-read-auto-template submod))
|
|
8434 (tpl-regexp (aref tpl-info 0)))
|
|
8435 (setq tpl-num (if (string-match tpl-regexp inst)
|
|
8436 (match-string 1 inst)
|
|
8437 "")
|
|
8438 tpl-list (aref tpl-info 1)))
|
|
8439 ;; Find submodule's signals and dump
|
|
8440 (let ((sig-list (verilog-signals-not-in
|
|
8441 (verilog-modi-get-outputs submodi)
|
|
8442 skip-pins))
|
|
8443 (vl-dir "output"))
|
|
8444 (when sig-list
|
|
8445 (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
|
|
8446 (indent-to indent-pt)
|
|
8447 (insert "// Outputs\n") ;; Note these are searched for in verilog-read-sub-decls
|
|
8448 (mapcar (function (lambda (port)
|
|
8449 (verilog-auto-inst-port port indent-pt tpl-list tpl-num for-star)))
|
|
8450 sig-list)))
|
|
8451 (let ((sig-list (verilog-signals-not-in
|
|
8452 (verilog-modi-get-inouts submodi)
|
|
8453 skip-pins))
|
|
8454 (vl-dir "inout"))
|
|
8455 (when sig-list
|
|
8456 (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
|
|
8457 (indent-to indent-pt)
|
|
8458 (insert "// Inouts\n")
|
|
8459 (mapcar (function (lambda (port)
|
|
8460 (verilog-auto-inst-port port indent-pt tpl-list tpl-num for-star)))
|
|
8461 sig-list)))
|
|
8462 (let ((sig-list (verilog-signals-not-in
|
|
8463 (verilog-modi-get-inputs submodi)
|
|
8464 skip-pins))
|
|
8465 (vl-dir "input"))
|
|
8466 (when sig-list
|
|
8467 (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
|
|
8468 (indent-to indent-pt)
|
|
8469 (insert "// Inputs\n")
|
|
8470 (mapcar (function (lambda (port)
|
|
8471 (verilog-auto-inst-port port indent-pt tpl-list tpl-num for-star)))
|
|
8472 sig-list)))
|
|
8473 ;; Kill extra semi
|
|
8474 (save-excursion
|
|
8475 (cond (did-first
|
|
8476 (re-search-backward "," pt t)
|
|
8477 (delete-char 1)
|
|
8478 (insert ");")
|
|
8479 (search-forward "\n") ;; Added by inst-port
|
|
8480 (delete-backward-char 1)
|
|
8481 (if (search-forward ")" nil t) ;; From user, moved up a line
|
|
8482 (delete-backward-char 1))
|
|
8483 (if (search-forward ";" nil t) ;; Don't error if user had syntax error and forgot it
|
|
8484 (delete-backward-char 1))
|
|
8485 )))
|
|
8486 ))))
|
|
8487
|
|
8488 (defun verilog-auto-inst-param ()
|
|
8489 "Expand AUTOINSTPARAM statements, as part of \\[verilog-auto].
|
|
8490 Replace the parameter connections to an instantiation with ones
|
|
8491 automatically derived from the module header of the instantiated netlist.
|
|
8492
|
|
8493 See \\[verilog-auto-inst] for limitations, and templates to customize the
|
|
8494 output.
|
|
8495
|
|
8496 For example, first take the submodule inst.v:
|
|
8497
|
|
8498 module inst (o,i)
|
|
8499 parameter PAR;
|
|
8500 endmodule
|
|
8501
|
|
8502 This is then used in a upper level module:
|
|
8503
|
|
8504 module ex_inst (o,i)
|
|
8505 parameter PAR;
|
|
8506 inst #(/*AUTOINSTPARAM*/)
|
|
8507 inst (/*AUTOINST*/);
|
|
8508 endmodule
|
|
8509
|
|
8510 Typing \\[verilog-auto] will make this into:
|
|
8511
|
|
8512 module ex_inst (o,i)
|
|
8513 output o;
|
|
8514 input i;
|
|
8515 inst (/*AUTOINSTPARAM*/
|
|
8516 // Parameters
|
|
8517 .PAR (PAR));
|
|
8518 inst (/*AUTOINST*/);
|
|
8519 endmodule
|
|
8520
|
|
8521 Where the list of parameter connections come from the inst module.
|
|
8522
|
|
8523 Templates:
|
|
8524
|
|
8525 You can customize the parameter connections using AUTO_TEMPLATEs,
|
|
8526 just as you would with \\[verilog-auto-inst]."
|
|
8527 (save-excursion
|
|
8528 ;; Find beginning
|
|
8529 (let* ((pt (point))
|
|
8530 (indent-pt (save-excursion (verilog-backward-open-paren)
|
|
8531 (1+ (current-column))))
|
|
8532 (verilog-auto-inst-column (max verilog-auto-inst-column
|
|
8533 (+ 16 (* 8 (/ (+ indent-pt 7) 8)))))
|
|
8534 (modi (verilog-modi-current))
|
|
8535 (vector-skip-list (unless verilog-auto-inst-vector
|
|
8536 (verilog-modi-get-signals modi)))
|
|
8537 submod submodi inst skip-pins tpl-list tpl-num did-first)
|
|
8538 ;; Find module name that is instantiated
|
|
8539 (setq submod (save-excursion
|
|
8540 ;; Get to the point where AUTOINST normally is to read the module
|
|
8541 (verilog-re-search-forward-quick "[(;]" nil nil)
|
|
8542 (verilog-read-inst-module))
|
|
8543 inst (save-excursion
|
|
8544 ;; Get to the point where AUTOINST normally is to read the module
|
|
8545 (verilog-re-search-forward-quick "[(;]" nil nil)
|
|
8546 (verilog-read-inst-name))
|
|
8547 vl-cell-type submod
|
|
8548 vl-cell-name inst
|
|
8549 skip-pins (aref (verilog-read-inst-pins) 0))
|
|
8550
|
|
8551 ;; Parse any AUTO_LISP() before here
|
|
8552 (verilog-read-auto-lisp (point-min) pt)
|
|
8553
|
|
8554 ;; Lookup position, etc of submodule
|
|
8555 ;; Note this may raise an error
|
|
8556 (when (setq submodi (verilog-modi-lookup submod t))
|
|
8557 ;; If there's a number in the instantiation, it may be a argument to the
|
|
8558 ;; automatic variable instantiation program.
|
|
8559 (let* ((tpl-info (verilog-read-auto-template submod))
|
|
8560 (tpl-regexp (aref tpl-info 0)))
|
|
8561 (setq tpl-num (if (string-match tpl-regexp inst)
|
|
8562 (match-string 1 inst)
|
|
8563 "")
|
|
8564 tpl-list (aref tpl-info 1)))
|
|
8565 ;; Find submodule's signals and dump
|
|
8566 (let ((sig-list (verilog-signals-not-in
|
|
8567 (verilog-modi-get-gparams submodi)
|
|
8568 skip-pins))
|
|
8569 (vl-dir "parameter"))
|
|
8570 (when sig-list
|
|
8571 (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
|
|
8572 (indent-to indent-pt)
|
|
8573 (insert "// Parameters\n") ;; Note these are searched for in verilog-read-sub-decls
|
|
8574 (mapcar (function (lambda (port)
|
|
8575 (verilog-auto-inst-port port indent-pt tpl-list tpl-num nil)))
|
|
8576 sig-list)))
|
|
8577 ;; Kill extra semi
|
|
8578 (save-excursion
|
|
8579 (cond (did-first
|
|
8580 (re-search-backward "," pt t)
|
|
8581 (delete-char 1)
|
|
8582 (insert ")")
|
|
8583 (search-forward "\n") ;; Added by inst-port
|
|
8584 (delete-backward-char 1)
|
|
8585 (if (search-forward ")" nil t) ;; From user, moved up a line
|
|
8586 (delete-backward-char 1))
|
|
8587 )))
|
|
8588 ))))
|
|
8589
|
|
8590 (defun verilog-auto-reg ()
|
|
8591 "Expand AUTOREG statements, as part of \\[verilog-auto].
|
|
8592 Make reg statements for any output that isn't already declared,
|
|
8593 and isn't a wire output from a block.
|
|
8594
|
|
8595 Limitations:
|
|
8596 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls').
|
|
8597
|
|
8598 This does NOT work on memories, declare those yourself.
|
|
8599
|
|
8600 An example:
|
|
8601
|
|
8602 module ex_reg (o,i)
|
|
8603 output o;
|
|
8604 input i;
|
|
8605 /*AUTOREG*/
|
|
8606 always o = i;
|
|
8607 endmodule
|
|
8608
|
|
8609 Typing \\[verilog-auto] will make this into:
|
|
8610
|
|
8611 module ex_reg (o,i)
|
|
8612 output o;
|
|
8613 input i;
|
|
8614 /*AUTOREG*/
|
|
8615 // Beginning of automatic regs (for this module's undeclared outputs)
|
|
8616 reg o;
|
|
8617 // End of automatics
|
|
8618 always o = i;
|
|
8619 endmodule"
|
|
8620 (save-excursion
|
|
8621 ;; Point must be at insertion point.
|
|
8622 (let* ((indent-pt (current-indentation))
|
|
8623 (modi (verilog-modi-current))
|
|
8624 (sig-list (verilog-signals-not-in
|
|
8625 (verilog-modi-get-outputs modi)
|
|
8626 (append (verilog-modi-get-wires modi)
|
|
8627 (verilog-modi-get-regs modi)
|
|
8628 (verilog-modi-get-assigns modi)
|
|
8629 (verilog-modi-get-consts modi)
|
|
8630 (verilog-modi-get-gparams modi)
|
|
8631 (verilog-modi-get-sub-outputs modi)
|
|
8632 (verilog-modi-get-sub-inouts modi)
|
|
8633 ))))
|
|
8634 (forward-line 1)
|
|
8635 (when sig-list
|
|
8636 (verilog-insert-indent "// Beginning of automatic regs (for this module's undeclared outputs)\n")
|
|
8637 (verilog-insert-definition sig-list "reg" indent-pt nil)
|
|
8638 (verilog-modi-cache-add-regs modi sig-list)
|
|
8639 (verilog-insert-indent "// End of automatics\n"))
|
|
8640 )))
|
|
8641
|
|
8642 (defun verilog-auto-reg-input ()
|
|
8643 "Expand AUTOREGINPUT statements, as part of \\[verilog-auto].
|
|
8644 Make reg statements instantiation inputs that aren't already declared.
|
|
8645 This is useful for making a top level shell for testing the module that is
|
|
8646 to be instantiated.
|
|
8647
|
|
8648 Limitations:
|
|
8649 This ONLY detects inputs of AUTOINSTants (see `verilog-read-sub-decls').
|
|
8650
|
|
8651 This does NOT work on memories, declare those yourself.
|
|
8652
|
|
8653 An example (see `verilog-auto-inst' for what else is going on here):
|
|
8654
|
|
8655 module ex_reg_input (o,i)
|
|
8656 output o;
|
|
8657 input i;
|
|
8658 /*AUTOREGINPUT*/
|
|
8659 inst inst (/*AUTOINST*/);
|
|
8660 endmodule
|
|
8661
|
|
8662 Typing \\[verilog-auto] will make this into:
|
|
8663
|
|
8664 module ex_reg_input (o,i)
|
|
8665 output o;
|
|
8666 input i;
|
|
8667 /*AUTOREGINPUT*/
|
|
8668 // Beginning of automatic reg inputs (for undeclared ...
|
|
8669 reg [31:0] iv; // From inst of inst.v
|
|
8670 // End of automatics
|
|
8671 inst inst (/*AUTOINST*/
|
|
8672 // Outputs
|
|
8673 .o (o[31:0]),
|
|
8674 // Inputs
|
|
8675 .iv (iv));
|
|
8676 endmodule"
|
|
8677 (save-excursion
|
|
8678 ;; Point must be at insertion point.
|
|
8679 (let* ((indent-pt (current-indentation))
|
|
8680 (modi (verilog-modi-current))
|
|
8681 (sig-list (verilog-signals-combine-bus
|
|
8682 (verilog-signals-not-in
|
|
8683 (append (verilog-modi-get-sub-inputs modi)
|
|
8684 (verilog-modi-get-sub-inouts modi))
|
|
8685 (verilog-modi-get-signals modi)
|
|
8686 ))))
|
|
8687 (forward-line 1)
|
|
8688 (when sig-list
|
|
8689 (verilog-insert-indent "// Beginning of automatic reg inputs (for undeclared instantiated-module inputs)\n")
|
|
8690 (verilog-insert-definition sig-list "reg" indent-pt nil)
|
|
8691 (verilog-modi-cache-add-regs modi sig-list)
|
|
8692 (verilog-insert-indent "// End of automatics\n"))
|
|
8693 )))
|
|
8694
|
|
8695 (defun verilog-auto-wire ()
|
|
8696 "Expand AUTOWIRE statements, as part of \\[verilog-auto].
|
|
8697 Make wire statements for instantiations outputs that aren't
|
|
8698 already declared.
|
|
8699
|
|
8700 Limitations:
|
|
8701 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls'),
|
|
8702 and all busses must have widths, such as those from AUTOINST, or using []
|
|
8703 in AUTO_TEMPLATEs.
|
|
8704
|
|
8705 This does NOT work on memories or SystemVerilog .name connections,
|
|
8706 declare those yourself.
|
|
8707
|
|
8708 Verilog-mode will add \"Couldn't Merge\" comments to signals it cannot
|
|
8709 determine how to bus together. This occurs when you have ports with
|
|
8710 non-numeric or non-sequential bus subscripts. If Verilog-Mode
|
|
8711 mis-guessed, you'll have to declare them yourself.
|
|
8712
|
|
8713 An example (see `verilog-auto-inst' for what else is going on here):
|
|
8714
|
|
8715 module ex_wire (o,i)
|
|
8716 output o;
|
|
8717 input i;
|
|
8718 /*AUTOWIRE*/
|
|
8719 inst inst (/*AUTOINST*/);
|
|
8720 endmodule
|
|
8721
|
|
8722 Typing \\[verilog-auto] will make this into:
|
|
8723
|
|
8724 module ex_wire (o,i)
|
|
8725 output o;
|
|
8726 input i;
|
|
8727 /*AUTOWIRE*/
|
|
8728 // Beginning of automatic wires
|
|
8729 wire [31:0] ov; // From inst of inst.v
|
|
8730 // End of automatics
|
|
8731 inst inst (/*AUTOINST*/
|
|
8732 // Outputs
|
|
8733 .ov (ov[31:0]),
|
|
8734 // Inputs
|
|
8735 .i (i));
|
|
8736 wire o = | ov;
|
|
8737 endmodule"
|
|
8738 (save-excursion
|
|
8739 ;; Point must be at insertion point.
|
|
8740 (let* ((indent-pt (current-indentation))
|
|
8741 (modi (verilog-modi-current))
|
|
8742 (sig-list (verilog-signals-combine-bus
|
|
8743 (verilog-signals-not-in
|
|
8744 (append (verilog-modi-get-sub-outputs modi)
|
|
8745 (verilog-modi-get-sub-inouts modi))
|
|
8746 (verilog-modi-get-signals modi)
|
|
8747 ))))
|
|
8748 (forward-line 1)
|
|
8749 (when sig-list
|
|
8750 (verilog-insert-indent "// Beginning of automatic wires (for undeclared instantiated-module outputs)\n")
|
|
8751 (verilog-insert-definition sig-list "wire" indent-pt nil)
|
|
8752 (verilog-modi-cache-add-wires modi sig-list)
|
|
8753 (verilog-insert-indent "// End of automatics\n")
|
|
8754 (when nil ;; Too slow on huge modules, plus makes everyone's module change
|
|
8755 (beginning-of-line)
|
|
8756 (setq pnt (point))
|
|
8757 (verilog-pretty-declarations)
|
|
8758 (goto-char pnt)
|
|
8759 (verilog-pretty-expr "//")))
|
|
8760 )))
|
|
8761
|
|
8762 (defun verilog-auto-output ()
|
|
8763 "Expand AUTOOUTPUT statements, as part of \\[verilog-auto].
|
|
8764 Make output statements for any output signal from an /*AUTOINST*/ that
|
|
8765 isn't a input to another AUTOINST. This is useful for modules which
|
|
8766 only instantiate other modules.
|
|
8767
|
|
8768 Limitations:
|
|
8769 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls').
|
|
8770
|
|
8771 If placed inside the parenthesis of a module declaration, it creates
|
|
8772 Verilog 2001 style, else uses Verilog 1995 style.
|
|
8773
|
|
8774 If any concatenation, or bit-subscripts are missing in the AUTOINSTant's
|
|
8775 instantiation, all bets are off. (For example due to a AUTO_TEMPLATE).
|
|
8776
|
|
8777 Typedefs must match `verilog-typedef-regexp', which is disabled by default.
|
|
8778
|
|
8779 Signals matching `verilog-auto-output-ignore-regexp' are not included.
|
|
8780
|
|
8781 An example (see `verilog-auto-inst' for what else is going on here):
|
|
8782
|
|
8783 module ex_output (ov,i)
|
|
8784 input i;
|
|
8785 /*AUTOOUTPUT*/
|
|
8786 inst inst (/*AUTOINST*/);
|
|
8787 endmodule
|
|
8788
|
|
8789 Typing \\[verilog-auto] will make this into:
|
|
8790
|
|
8791 module ex_output (ov,i)
|
|
8792 input i;
|
|
8793 /*AUTOOUTPUT*/
|
|
8794 // Beginning of automatic outputs (from unused autoinst outputs)
|
|
8795 output [31:0] ov; // From inst of inst.v
|
|
8796 // End of automatics
|
|
8797 inst inst (/*AUTOINST*/
|
|
8798 // Outputs
|
|
8799 .ov (ov[31:0]),
|
|
8800 // Inputs
|
|
8801 .i (i));
|
|
8802 endmodule"
|
|
8803 (save-excursion
|
|
8804 ;; Point must be at insertion point.
|
|
8805 (let* ((indent-pt (current-indentation))
|
|
8806 (v2k (verilog-in-paren))
|
|
8807 (modi (verilog-modi-current))
|
|
8808 (sig-list (verilog-signals-not-in
|
|
8809 (verilog-modi-get-sub-outputs modi)
|
|
8810 (append (verilog-modi-get-outputs modi)
|
|
8811 (verilog-modi-get-inouts modi)
|
|
8812 (verilog-modi-get-sub-inputs modi)
|
|
8813 (verilog-modi-get-sub-inouts modi)
|
|
8814 ))))
|
|
8815 (setq sig-list (verilog-signals-not-matching-regexp
|
|
8816 sig-list verilog-auto-output-ignore-regexp))
|
|
8817 (forward-line 1)
|
|
8818 (when v2k (verilog-repair-open-comma))
|
|
8819 (when sig-list
|
|
8820 (verilog-insert-indent "// Beginning of automatic outputs (from unused autoinst outputs)\n")
|
|
8821 (verilog-insert-definition sig-list "output" indent-pt v2k)
|
|
8822 (verilog-modi-cache-add-outputs modi sig-list)
|
|
8823 (verilog-insert-indent "// End of automatics\n"))
|
|
8824 (when v2k (verilog-repair-close-comma))
|
|
8825 )))
|
|
8826
|
|
8827 (defun verilog-auto-output-every ()
|
|
8828 "Expand AUTOOUTPUTEVERY statements, as part of \\[verilog-auto].
|
|
8829 Make output statements for any signals that aren't primary inputs or
|
|
8830 outputs already. This makes every signal in the design a output. This is
|
|
8831 useful to get Synopsys to preserve every signal in the design, since it
|
|
8832 won't optimize away the outputs.
|
|
8833
|
|
8834 An example:
|
|
8835
|
|
8836 module ex_output_every (o,i,tempa,tempb)
|
|
8837 output o;
|
|
8838 input i;
|
|
8839 /*AUTOOUTPUTEVERY*/
|
|
8840 wire tempa = i;
|
|
8841 wire tempb = tempa;
|
|
8842 wire o = tempb;
|
|
8843 endmodule
|
|
8844
|
|
8845 Typing \\[verilog-auto] will make this into:
|
|
8846
|
|
8847 module ex_output_every (o,i,tempa,tempb)
|
|
8848 output o;
|
|
8849 input i;
|
|
8850 /*AUTOOUTPUTEVERY*/
|
|
8851 // Beginning of automatic outputs (every signal)
|
|
8852 output tempb;
|
|
8853 output tempa;
|
|
8854 // End of automatics
|
|
8855 wire tempa = i;
|
|
8856 wire tempb = tempa;
|
|
8857 wire o = tempb;
|
|
8858 endmodule"
|
|
8859 (save-excursion
|
|
8860 ;;Point must be at insertion point
|
|
8861 (let* ((indent-pt (current-indentation))
|
|
8862 (v2k (verilog-in-paren))
|
|
8863 (modi (verilog-modi-current))
|
|
8864 (sig-list (verilog-signals-combine-bus
|
|
8865 (verilog-signals-not-in
|
|
8866 (verilog-modi-get-signals modi)
|
|
8867 (verilog-modi-get-ports modi)
|
|
8868 ))))
|
|
8869 (forward-line 1)
|
|
8870 (when v2k (verilog-repair-open-comma))
|
|
8871 (when sig-list
|
|
8872 (verilog-insert-indent "// Beginning of automatic outputs (every signal)\n")
|
|
8873 (verilog-insert-definition sig-list "output" indent-pt v2k)
|
|
8874 (verilog-modi-cache-add-outputs modi sig-list)
|
|
8875 (verilog-insert-indent "// End of automatics\n"))
|
|
8876 (when v2k (verilog-repair-close-comma))
|
|
8877 )))
|
|
8878
|
|
8879 (defun verilog-auto-input ()
|
|
8880 "Expand AUTOINPUT statements, as part of \\[verilog-auto].
|
|
8881 Make input statements for any input signal into an /*AUTOINST*/ that
|
|
8882 isn't declared elsewhere inside the module. This is useful for modules which
|
|
8883 only instantiate other modules.
|
|
8884
|
|
8885 Limitations:
|
|
8886 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls').
|
|
8887
|
|
8888 If placed inside the parenthesis of a module declaration, it creates
|
|
8889 Verilog 2001 style, else uses Verilog 1995 style.
|
|
8890
|
|
8891 If any concatenation, or bit-subscripts are missing in the AUTOINSTant's
|
|
8892 instantiation, all bets are off. (For example due to a AUTO_TEMPLATE).
|
|
8893
|
|
8894 Typedefs must match `verilog-typedef-regexp', which is disabled by default.
|
|
8895
|
|
8896 Signals matching `verilog-auto-input-ignore-regexp' are not included.
|
|
8897
|
|
8898 An example (see `verilog-auto-inst' for what else is going on here):
|
|
8899
|
|
8900 module ex_input (ov,i)
|
|
8901 output [31:0] ov;
|
|
8902 /*AUTOINPUT*/
|
|
8903 inst inst (/*AUTOINST*/);
|
|
8904 endmodule
|
|
8905
|
|
8906 Typing \\[verilog-auto] will make this into:
|
|
8907
|
|
8908 module ex_input (ov,i)
|
|
8909 output [31:0] ov;
|
|
8910 /*AUTOINPUT*/
|
|
8911 // Beginning of automatic inputs (from unused autoinst inputs)
|
|
8912 input i; // From inst of inst.v
|
|
8913 // End of automatics
|
|
8914 inst inst (/*AUTOINST*/
|
|
8915 // Outputs
|
|
8916 .ov (ov[31:0]),
|
|
8917 // Inputs
|
|
8918 .i (i));
|
|
8919 endmodule"
|
|
8920 (save-excursion
|
|
8921 (let* ((indent-pt (current-indentation))
|
|
8922 (v2k (verilog-in-paren))
|
|
8923 (modi (verilog-modi-current))
|
|
8924 (sig-list (verilog-signals-not-in
|
|
8925 (verilog-modi-get-sub-inputs modi)
|
|
8926 (append (verilog-modi-get-inputs modi)
|
|
8927 (verilog-modi-get-inouts modi)
|
|
8928 (verilog-modi-get-wires modi)
|
|
8929 (verilog-modi-get-regs modi)
|
|
8930 (verilog-modi-get-consts modi)
|
|
8931 (verilog-modi-get-gparams modi)
|
|
8932 (verilog-modi-get-sub-outputs modi)
|
|
8933 (verilog-modi-get-sub-inouts modi)
|
|
8934 ))))
|
|
8935 (setq sig-list (verilog-signals-not-matching-regexp
|
|
8936 sig-list verilog-auto-input-ignore-regexp))
|
|
8937 (forward-line 1)
|
|
8938 (when v2k (verilog-repair-open-comma))
|
|
8939 (when sig-list
|
|
8940 (verilog-insert-indent "// Beginning of automatic inputs (from unused autoinst inputs)\n")
|
|
8941 (verilog-insert-definition sig-list "input" indent-pt v2k)
|
|
8942 (verilog-modi-cache-add-inputs modi sig-list)
|
|
8943 (verilog-insert-indent "// End of automatics\n"))
|
|
8944 (when v2k (verilog-repair-close-comma))
|
|
8945 )))
|
|
8946
|
|
8947 (defun verilog-auto-inout ()
|
|
8948 "Expand AUTOINOUT statements, as part of \\[verilog-auto].
|
|
8949 Make inout statements for any inout signal in an /*AUTOINST*/ that
|
|
8950 isn't declared elsewhere inside the module.
|
|
8951
|
|
8952 Limitations:
|
|
8953 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls').
|
|
8954
|
|
8955 If placed inside the parenthesis of a module declaration, it creates
|
|
8956 Verilog 2001 style, else uses Verilog 1995 style.
|
|
8957
|
|
8958 If any concatenation, or bit-subscripts are missing in the AUTOINSTant's
|
|
8959 instantiation, all bets are off. (For example due to a AUTO_TEMPLATE).
|
|
8960
|
|
8961 Typedefs must match `verilog-typedef-regexp', which is disabled by default.
|
|
8962
|
|
8963 Signals matching `verilog-auto-inout-ignore-regexp' are not included.
|
|
8964
|
|
8965 An example (see `verilog-auto-inst' for what else is going on here):
|
|
8966
|
|
8967 module ex_inout (ov,i)
|
|
8968 input i;
|
|
8969 /*AUTOINOUT*/
|
|
8970 inst inst (/*AUTOINST*/);
|
|
8971 endmodule
|
|
8972
|
|
8973 Typing \\[verilog-auto] will make this into:
|
|
8974
|
|
8975 module ex_inout (ov,i)
|
|
8976 input i;
|
|
8977 /*AUTOINOUT*/
|
|
8978 // Beginning of automatic inouts (from unused autoinst inouts)
|
|
8979 inout [31:0] ov; // From inst of inst.v
|
|
8980 // End of automatics
|
|
8981 inst inst (/*AUTOINST*/
|
|
8982 // Inouts
|
|
8983 .ov (ov[31:0]),
|
|
8984 // Inputs
|
|
8985 .i (i));
|
|
8986 endmodule"
|
|
8987 (save-excursion
|
|
8988 ;; Point must be at insertion point.
|
|
8989 (let* ((indent-pt (current-indentation))
|
|
8990 (v2k (verilog-in-paren))
|
|
8991 (modi (verilog-modi-current))
|
|
8992 (sig-list (verilog-signals-not-in
|
|
8993 (verilog-modi-get-sub-inouts modi)
|
|
8994 (append (verilog-modi-get-outputs modi)
|
|
8995 (verilog-modi-get-inouts modi)
|
|
8996 (verilog-modi-get-inputs modi)
|
|
8997 (verilog-modi-get-sub-inputs modi)
|
|
8998 (verilog-modi-get-sub-outputs modi)
|
|
8999 ))))
|
|
9000 (setq sig-list (verilog-signals-not-matching-regexp
|
|
9001 sig-list verilog-auto-inout-ignore-regexp))
|
|
9002 (forward-line 1)
|
|
9003 (when v2k (verilog-repair-open-comma))
|
|
9004 (when sig-list
|
|
9005 (verilog-insert-indent "// Beginning of automatic inouts (from unused autoinst inouts)\n")
|
|
9006 (verilog-insert-definition sig-list "inout" indent-pt v2k)
|
|
9007 (verilog-modi-cache-add-inouts modi sig-list)
|
|
9008 (verilog-insert-indent "// End of automatics\n"))
|
|
9009 (when v2k (verilog-repair-close-comma))
|
|
9010 )))
|
|
9011
|
|
9012 (defun verilog-auto-inout-module ()
|
|
9013 "Expand AUTOINOUTMODULE statements, as part of \\[verilog-auto].
|
|
9014 Take input/output/inout statements from the specified module and insert
|
|
9015 into the current module. This is useful for making null templates and
|
|
9016 shell modules which need to have identical I/O with another module. Any
|
|
9017 I/O which are already defined in this module will not be redefined.
|
|
9018
|
|
9019 Limitations:
|
|
9020 If placed inside the parenthesis of a module declaration, it creates
|
|
9021 Verilog 2001 style, else uses Verilog 1995 style.
|
|
9022
|
|
9023 Concatenation and outputting partial busses is not supported.
|
|
9024
|
|
9025 Module names must be resolvable to filenames. See `verilog-auto-inst'.
|
|
9026
|
|
9027 Signals are not inserted in the same order as in the original module,
|
|
9028 though they will appear to be in the same order to a AUTOINST
|
|
9029 instantiating either module.
|
|
9030
|
|
9031 An example:
|
|
9032
|
|
9033 module ex_shell (/*AUTOARG*/)
|
|
9034 /*AUTOINOUTMODULE(\"ex_main\")*/
|
|
9035 endmodule
|
|
9036
|
|
9037 module ex_main (i,o,io)
|
|
9038 input i;
|
|
9039 output o;
|
|
9040 inout io;
|
|
9041 endmodule
|
|
9042
|
|
9043 Typing \\[verilog-auto] will make this into:
|
|
9044
|
|
9045 module ex_shell (/*AUTOARG*/i,o,io)
|
|
9046 /*AUTOINOUTMODULE(\"ex_main\")*/
|
|
9047 // Beginning of automatic in/out/inouts (from specific module)
|
|
9048 input i;
|
|
9049 output o;
|
|
9050 inout io;
|
|
9051 // End of automatics
|
|
9052 endmodule"
|
|
9053 (save-excursion
|
|
9054 (let* ((submod (car (verilog-read-auto-params 1))) submodi)
|
|
9055 ;; Lookup position, etc of co-module
|
|
9056 ;; Note this may raise an error
|
|
9057 (when (setq submodi (verilog-modi-lookup submod t))
|
|
9058 (let* ((indent-pt (current-indentation))
|
|
9059 (v2k (verilog-in-paren))
|
|
9060 (modi (verilog-modi-current))
|
|
9061 (sig-list-i (verilog-signals-not-in
|
|
9062 (verilog-modi-get-inputs submodi)
|
|
9063 (append (verilog-modi-get-inputs modi))))
|
|
9064 (sig-list-o (verilog-signals-not-in
|
|
9065 (verilog-modi-get-outputs submodi)
|
|
9066 (append (verilog-modi-get-outputs modi))))
|
|
9067 (sig-list-io (verilog-signals-not-in
|
|
9068 (verilog-modi-get-inouts submodi)
|
|
9069 (append (verilog-modi-get-inouts modi)))))
|
|
9070 (forward-line 1)
|
|
9071 (when v2k (verilog-repair-open-comma))
|
|
9072 (when (or sig-list-i sig-list-o sig-list-io)
|
|
9073 (verilog-insert-indent "// Beginning of automatic in/out/inouts (from specific module)\n")
|
|
9074 ;; Don't sort them so a upper AUTOINST will match the main module
|
|
9075 (verilog-insert-definition sig-list-o "output" indent-pt v2k t)
|
|
9076 (verilog-insert-definition sig-list-io "inout" indent-pt v2k t)
|
|
9077 (verilog-insert-definition sig-list-i "input" indent-pt v2k t)
|
|
9078 (verilog-modi-cache-add-inputs modi sig-list-i)
|
|
9079 (verilog-modi-cache-add-outputs modi sig-list-o)
|
|
9080 (verilog-modi-cache-add-inouts modi sig-list-io)
|
|
9081 (verilog-insert-indent "// End of automatics\n"))
|
|
9082 (when v2k (verilog-repair-close-comma))
|
|
9083 )))))
|
|
9084
|
|
9085 (defun verilog-auto-sense-sigs (modi presense-sigs)
|
|
9086 "Return list of signals for current AUTOSENSE block."
|
|
9087 (let* ((sigss (verilog-read-always-signals))
|
|
9088 (sig-list (verilog-signals-not-params
|
|
9089 (verilog-signals-not-in (verilog-alw-get-inputs sigss)
|
|
9090 (append (and (not verilog-auto-sense-include-inputs)
|
|
9091 (verilog-alw-get-outputs sigss))
|
|
9092 (verilog-modi-get-consts modi)
|
|
9093 (verilog-modi-get-gparams modi)
|
|
9094 presense-sigs)))))
|
|
9095 sig-list))
|
|
9096
|
|
9097 (defun verilog-auto-sense ()
|
|
9098 "Expand AUTOSENSE statements, as part of \\[verilog-auto].
|
|
9099 Replace the always (/*AUTOSENSE*/) sensitivity list (/*AS*/ for short)
|
|
9100 with one automatically derived from all inputs declared in the always
|
|
9101 statement. Signals that are generated within the same always block are NOT
|
|
9102 placed into the sensitivity list (see `verilog-auto-sense-include-inputs').
|
|
9103 Long lines are split based on the `fill-column', see \\[set-fill-column].
|
|
9104
|
|
9105 Limitations:
|
|
9106 Verilog does not allow memories (multidimensional arrays) in sensitivity
|
|
9107 lists. AUTOSENSE will thus exclude them, and add a /*memory or*/ comment.
|
|
9108
|
|
9109 Constant signals:
|
|
9110 AUTOSENSE cannot always determine if a `define is a constant or a signal
|
|
9111 (it could be in a include file for example). If a `define or other signal
|
|
9112 is put into the AUTOSENSE list and is not desired, use the AUTO_CONSTANT
|
|
9113 declaration anywhere in the module (parenthesis are required):
|
|
9114
|
|
9115 /* AUTO_CONSTANT ( `this_is_really_constant_dont_autosense_it ) */
|
|
9116
|
|
9117 Better yet, use a parameter, which will be understood to be constant
|
|
9118 automatically.
|
|
9119
|
|
9120 OOps!
|
|
9121 If AUTOSENSE makes a mistake, please report it. (First try putting
|
|
9122 a begin/end after your always!) As a workaround, if a signal that
|
|
9123 shouldn't be in the sensitivity list was, use the AUTO_CONSTANT above.
|
|
9124 If a signal should be in the sensitivity list wasn't, placing it before
|
|
9125 the /*AUTOSENSE*/ comment will prevent it from being deleted when the
|
|
9126 autos are updated (or added if it occurs there already).
|
|
9127
|
|
9128 An example:
|
|
9129
|
|
9130 always @ (/*AUTOSENSE*/) begin
|
|
9131 /* AUTO_CONSTANT (`constant) */
|
|
9132 outin = ina | inb | `constant;
|
|
9133 out = outin;
|
|
9134 end
|
|
9135
|
|
9136 Typing \\[verilog-auto] will make this into:
|
|
9137
|
|
9138 always @ (/*AUTOSENSE*/ina or inb) begin
|
|
9139 /* AUTO_CONSTANT (`constant) */
|
|
9140 outin = ina | inb | `constant;
|
|
9141 out = outin;
|
|
9142 end"
|
|
9143 (save-excursion
|
|
9144 ;; Find beginning
|
|
9145 (let* ((start-pt (save-excursion
|
|
9146 (verilog-re-search-backward "(" nil t)
|
|
9147 (point)))
|
|
9148 (indent-pt (save-excursion
|
|
9149 (or (and (goto-char start-pt) (1+ (current-column)))
|
|
9150 (current-indentation))))
|
|
9151 (modi (verilog-modi-current))
|
|
9152 (sig-memories (verilog-signals-memory
|
|
9153 (append
|
|
9154 (verilog-modi-get-regs modi)
|
|
9155 (verilog-modi-get-wires modi))))
|
|
9156 sig-list not-first presense-sigs)
|
|
9157 ;; Read signals in always, eliminate outputs from sense list
|
|
9158 (setq presense-sigs (verilog-signals-from-signame
|
|
9159 (save-excursion
|
|
9160 (verilog-read-signals start-pt (point)))))
|
|
9161 (setq sig-list (verilog-auto-sense-sigs modi presense-sigs))
|
|
9162 (when sig-memories
|
|
9163 (let ((tlen (length sig-list)))
|
|
9164 (setq sig-list (verilog-signals-not-in sig-list sig-memories))
|
|
9165 (if (not (eq tlen (length sig-list))) (insert " /*memory or*/ "))))
|
|
9166 (if (and presense-sigs ;; Add a "or" if not "(.... or /*AUTOSENSE*/"
|
|
9167 (save-excursion (goto-char (point))
|
|
9168 (verilog-re-search-backward "[a-zA-Z0-9$_.%`]+" start-pt t)
|
|
9169 (verilog-re-search-backward "\\s-" start-pt t)
|
|
9170 (while (looking-at "\\s-`endif")
|
|
9171 (verilog-re-search-backward "[a-zA-Z0-9$_.%`]+" start-pt t)
|
|
9172 (verilog-re-search-backward "\\s-" start-pt t))
|
|
9173 (not (looking-at "\\s-or\\b"))))
|
|
9174 (setq not-first t))
|
|
9175 (setq sig-list (sort sig-list `verilog-signals-sort-compare))
|
|
9176 (while sig-list
|
|
9177 (cond ((> (+ 4 (current-column) (length (verilog-sig-name (car sig-list)))) fill-column) ;+4 for width of or
|
|
9178 (insert "\n")
|
|
9179 (indent-to indent-pt)
|
|
9180 (if not-first (insert "or ")))
|
|
9181 (not-first (insert " or ")))
|
|
9182 (insert (verilog-sig-name (car sig-list)))
|
|
9183 (setq sig-list (cdr sig-list)
|
|
9184 not-first t))
|
|
9185 )))
|
|
9186
|
|
9187 (defun verilog-auto-reset ()
|
|
9188 "Expand AUTORESET statements, as part of \\[verilog-auto].
|
|
9189 Replace the /*AUTORESET*/ comment with code to initialize all
|
|
9190 registers set elsewhere in the always block.
|
|
9191
|
|
9192 Limitations:
|
|
9193 AUTORESET will not clear memories.
|
|
9194
|
|
9195 AUTORESET uses <= if there are any <= in the block, else it uses =.
|
|
9196
|
|
9197 /*AUTORESET*/ presumes that any signals mentioned between the previous
|
|
9198 begin/case/if statement and the AUTORESET comment are being reset manually
|
|
9199 and should not be automatically reset. This includes omitting any signals
|
|
9200 used on the right hand side of assignments.
|
|
9201
|
|
9202 By default, AUTORESET will include the width of the signal in the autos,
|
|
9203 this is a recent change. To control this behavior, see
|
|
9204 `verilog-auto-reset-widths'.
|
|
9205
|
|
9206 AUTORESET ties signals to deasserted, which is presumed to be zero.
|
|
9207 Signals that match `verilog-active-low-regexp' will be deasserted by tieing
|
|
9208 them to a one.
|
|
9209
|
|
9210 An example:
|
|
9211
|
|
9212 always @(posedge clk or negedge reset_l) begin
|
|
9213 if (!reset_l) begin
|
|
9214 c <= 1;
|
|
9215 /*AUTORESET*/
|
|
9216 end
|
|
9217 else begin
|
|
9218 a <= in_a;
|
|
9219 b <= in_b;
|
|
9220 c <= in_c;
|
|
9221 end
|
|
9222 end
|
|
9223
|
|
9224 Typing \\[verilog-auto] will make this into:
|
|
9225
|
|
9226 always @(posedge core_clk or negedge reset_l) begin
|
|
9227 if (!reset_l) begin
|
|
9228 c <= 1;
|
|
9229 /*AUTORESET*/
|
|
9230 // Beginning of autoreset for uninitialized flops
|
|
9231 a <= 0;
|
|
9232 b <= 0;
|
|
9233 // End of automatics
|
|
9234 end
|
|
9235 else begin
|
|
9236 a <= in_a;
|
|
9237 b <= in_b;
|
|
9238 c <= in_c;
|
|
9239 end
|
|
9240 end"
|
|
9241
|
|
9242 (interactive)
|
|
9243 (save-excursion
|
|
9244 ;; Find beginning
|
|
9245 (let* ((indent-pt (current-indentation))
|
|
9246 (modi (verilog-modi-current))
|
|
9247 (all-list (verilog-modi-get-signals modi))
|
|
9248 sigss sig-list prereset-sigs assignment-str)
|
|
9249 ;; Read signals in always, eliminate outputs from reset list
|
|
9250 (setq prereset-sigs (verilog-signals-from-signame
|
|
9251 (save-excursion
|
|
9252 (verilog-read-signals
|
|
9253 (save-excursion
|
|
9254 (verilog-re-search-backward "\\(@\\|\\<begin\\>\\|\\<if\\>\\|\\<case\\>\\)" nil t)
|
|
9255 (point))
|
|
9256 (point)))))
|
|
9257 (save-excursion
|
|
9258 (verilog-re-search-backward "@" nil t)
|
|
9259 (setq sigss (verilog-read-always-signals)))
|
|
9260 (setq assignment-str (if (verilog-alw-get-uses-delayed sigss)
|
|
9261 (concat " <= " verilog-assignment-delay)
|
|
9262 " = "))
|
|
9263 (setq sig-list (verilog-signals-not-in (verilog-alw-get-outputs sigss)
|
|
9264 prereset-sigs))
|
|
9265 (setq sig-list (sort sig-list `verilog-signals-sort-compare))
|
|
9266 (when sig-list
|
|
9267 (insert "\n");
|
|
9268 (indent-to indent-pt)
|
|
9269 (insert "// Beginning of autoreset for uninitialized flops\n");
|
|
9270 (indent-to indent-pt)
|
|
9271 (while sig-list
|
|
9272 (let ((sig (or (assoc (verilog-sig-name (car sig-list)) all-list) ;; As sig-list has no widths
|
|
9273 (car sig-list))))
|
|
9274 (insert (verilog-sig-name sig)
|
|
9275 assignment-str
|
|
9276 (verilog-sig-tieoff sig (not verilog-auto-reset-widths))
|
|
9277 ";\n")
|
|
9278 (indent-to indent-pt)
|
|
9279 (setq sig-list (cdr sig-list))))
|
|
9280 (insert "// End of automatics"))
|
|
9281 )))
|
|
9282
|
|
9283 (defun verilog-auto-tieoff ()
|
|
9284 "Expand AUTOTIEOFF statements, as part of \\[verilog-auto].
|
|
9285 Replace the /*AUTOTIEOFF*/ comment with code to wire-tie all unused output
|
|
9286 signals to deasserted.
|
|
9287
|
|
9288 /*AUTOTIEOFF*/ is used to make stub modules; modules that have the same
|
|
9289 input/output list as another module, but no internals. Specifically, it
|
|
9290 finds all outputs in the module, and if that input is not otherwise declared
|
|
9291 as a register or wire, creates a tieoff.
|
|
9292
|
|
9293 AUTORESET ties signals to deasserted, which is presumed to be zero.
|
|
9294 Signals that match `verilog-active-low-regexp' will be deasserted by tieing
|
|
9295 them to a one.
|
|
9296
|
|
9297 An example of making a stub for another module:
|
|
9298
|
|
9299 module FooStub (/*AUTOINST*/);
|
|
9300 /*AUTOINOUTMODULE(\"Foo\")*/
|
|
9301 /*AUTOTIEOFF*/
|
|
9302 // verilator lint_off UNUSED
|
|
9303 wire _unused_ok = &{1'b0,
|
|
9304 /*AUTOUNUSED*/
|
|
9305 1'b0};
|
|
9306 // verilator lint_on UNUSED
|
|
9307 endmodule
|
|
9308
|
|
9309 Typing \\[verilog-auto] will make this into:
|
|
9310
|
|
9311 module FooStub (/*AUTOINST*/...);
|
|
9312 /*AUTOINOUTMODULE(\"Foo\")*/
|
|
9313 // Beginning of autotieoff
|
|
9314 output [2:0] foo;
|
|
9315 // End of automatics
|
|
9316
|
|
9317 /*AUTOTIEOFF*/
|
|
9318 // Beginning of autotieoff
|
|
9319 wire [2:0] foo = 3'b0;
|
|
9320 // End of automatics
|
|
9321 ...
|
|
9322 endmodule"
|
|
9323 (interactive)
|
|
9324 (save-excursion
|
|
9325 ;; Find beginning
|
|
9326 (let* ((indent-pt (current-indentation))
|
|
9327 (modi (verilog-modi-current))
|
|
9328 (sig-list (verilog-signals-not-in
|
|
9329 (verilog-modi-get-outputs modi)
|
|
9330 (append (verilog-modi-get-wires modi)
|
|
9331 (verilog-modi-get-regs modi)
|
|
9332 (verilog-modi-get-assigns modi)
|
|
9333 (verilog-modi-get-consts modi)
|
|
9334 (verilog-modi-get-gparams modi)
|
|
9335 (verilog-modi-get-sub-outputs modi)
|
|
9336 (verilog-modi-get-sub-inouts modi)
|
|
9337 ))))
|
|
9338 (when sig-list
|
|
9339 (forward-line 1)
|
|
9340 (verilog-insert-indent "// Beginning of automatic tieoffs (for this module's unterminated outputs)\n")
|
|
9341 (setq sig-list (sort (copy-alist sig-list) `verilog-signals-sort-compare))
|
|
9342 (verilog-modi-cache-add-wires modi sig-list) ; Before we trash list
|
|
9343 (while sig-list
|
|
9344 (let ((sig (car sig-list)))
|
|
9345 (verilog-insert-one-definition sig "wire" indent-pt)
|
|
9346 (indent-to (max 48 (+ indent-pt 40)))
|
|
9347 (insert "= " (verilog-sig-tieoff sig)
|
|
9348 ";\n")
|
|
9349 (setq sig-list (cdr sig-list))))
|
|
9350 (verilog-insert-indent "// End of automatics\n")
|
|
9351 ))))
|
|
9352
|
|
9353 (defun verilog-auto-unused ()
|
|
9354 "Expand AUTOUNUSED statements, as part of \\[verilog-auto].
|
|
9355 Replace the /*AUTOUNUSED*/ comment with a comma separated list of all unused
|
|
9356 input and inout signals.
|
|
9357
|
|
9358 /*AUTOUNUSED*/ is used to make stub modules; modules that have the same
|
|
9359 input/output list as another module, but no internals. Specifically, it
|
|
9360 finds all inputs and inouts in the module, and if that input is not otherwise
|
|
9361 used, adds it to a comma separated list.
|
|
9362
|
|
9363 The comma separated list is intended to be used to create a _unused_ok
|
|
9364 signal. Using the exact name \"_unused_ok\" for name of the temporary
|
|
9365 signal is recommended as it will insure maximum forward compatibility, it
|
|
9366 also makes lint warnings easy to understand; ignore any unused warnings
|
|
9367 with \"unused\" in the signal name.
|
|
9368
|
|
9369 To reduce simulation time, the _unused_ok signal should be forced to a
|
|
9370 constant to prevent wiggling. The easiest thing to do is use a
|
|
9371 reduction-and with 1'b0 as shown.
|
|
9372
|
|
9373 This way all unused signals are in one place, making it convenient to add
|
|
9374 your tool's specific pragmas around the assignment to disable any unused
|
|
9375 warnings.
|
|
9376
|
|
9377 You can add signals you do not want included in AUTOUNUSED with
|
|
9378 `verilog-auto-unused-ignore-regexp'.
|
|
9379
|
|
9380 An example of making a stub for another module:
|
|
9381
|
|
9382 module FooStub (/*AUTOINST*/);
|
|
9383 /*AUTOINOUTMODULE(\"Foo\")*/
|
|
9384 /*AUTOTIEOFF*/
|
|
9385 // verilator lint_off UNUSED
|
|
9386 wire _unused_ok = &{1'b0,
|
|
9387 /*AUTOUNUSED*/
|
|
9388 1'b0};
|
|
9389 // verilator lint_on UNUSED
|
|
9390 endmodule
|
|
9391
|
|
9392 Typing \\[verilog-auto] will make this into:
|
|
9393
|
|
9394 ...
|
|
9395 // verilator lint_off UNUSED
|
|
9396 wire _unused_ok = &{1'b0,
|
|
9397 /*AUTOUNUSED*/
|
|
9398 // Beginning of automatics
|
|
9399 unused_input_a,
|
|
9400 unused_input_b,
|
|
9401 unused_input_c,
|
|
9402 // End of automatics
|
|
9403 1'b0};
|
|
9404 // verilator lint_on UNUSED
|
|
9405 endmodule"
|
|
9406 (interactive)
|
|
9407 (save-excursion
|
|
9408 ;; Find beginning
|
|
9409 (let* ((indent-pt (progn (search-backward "/*") (current-column)))
|
|
9410 (modi (verilog-modi-current))
|
|
9411 (sig-list (verilog-signals-not-in
|
|
9412 (append (verilog-modi-get-inputs modi)
|
|
9413 (verilog-modi-get-inouts modi))
|
|
9414 (append (verilog-modi-get-sub-inputs modi)
|
|
9415 (verilog-modi-get-sub-inouts modi)
|
|
9416 ))))
|
|
9417 (setq sig-list (verilog-signals-not-matching-regexp
|
|
9418 sig-list verilog-auto-unused-ignore-regexp))
|
|
9419 (when sig-list
|
|
9420 (forward-line 1)
|
|
9421 (verilog-insert-indent "// Beginning of automatic unused inputs\n")
|
|
9422 (setq sig-list (sort (copy-alist sig-list) `verilog-signals-sort-compare))
|
|
9423 (while sig-list
|
|
9424 (let ((sig (car sig-list)))
|
|
9425 (indent-to indent-pt)
|
|
9426 (insert (verilog-sig-name sig) ",\n")
|
|
9427 (setq sig-list (cdr sig-list))))
|
|
9428 (verilog-insert-indent "// End of automatics\n")
|
|
9429 ))))
|
|
9430
|
|
9431 (defun verilog-enum-ascii (signm elim-regexp)
|
|
9432 "Convert a enum name SIGNM to a ascii string for insertion.
|
|
9433 Remove user provided prefix ELIM-REGEXP."
|
|
9434 (or elim-regexp (setq elim-regexp "_ DONT MATCH IT_"))
|
|
9435 (let ((case-fold-search t))
|
|
9436 ;; All upper becomes all lower for readability
|
|
9437 (downcase (verilog-string-replace-matches elim-regexp "" nil nil signm))))
|
|
9438
|
|
9439 (defun verilog-auto-ascii-enum ()
|
|
9440 "Expand AUTOASCIIENUM statements, as part of \\[verilog-auto].
|
|
9441 Create a register to contain the ASCII decode of a enumerated signal type.
|
|
9442 This will allow trace viewers to show the ASCII name of states.
|
|
9443
|
|
9444 First, parameters are built into a enumeration using the synopsys enum
|
|
9445 comment. The comment must be between the keyword and the symbol.
|
|
9446 (Annoying, but that's what Synopsys's dc_shell FSM reader requires.)
|
|
9447
|
|
9448 Next, registers which that enum applies to are also tagged with the same
|
|
9449 enum. Synopsys also suggests labeling state vectors, but `verilog-mode'
|
|
9450 doesn't care.
|
|
9451
|
|
9452 Finally, a AUTOASCIIENUM command is used.
|
|
9453
|
|
9454 The first parameter is the name of the signal to be decoded.
|
|
9455
|
|
9456 The second parameter is the name to store the ASCII code into. For the
|
|
9457 signal foo, I suggest the name _foo__ascii, where the leading _ indicates
|
|
9458 a signal that is just for simulation, and the magic characters _ascii
|
|
9459 tell viewers like Dinotrace to display in ASCII format.
|
|
9460
|
|
9461 The final optional parameter is a string which will be removed from the
|
|
9462 state names.
|
|
9463
|
|
9464 An example:
|
|
9465
|
|
9466 //== State enumeration
|
|
9467 parameter [2:0] // synopsys enum state_info
|
|
9468 SM_IDLE = 3'b000,
|
|
9469 SM_SEND = 3'b001,
|
|
9470 SM_WAIT1 = 3'b010;
|
|
9471 //== State variables
|
|
9472 reg [2:0] /* synopsys enum state_info */
|
|
9473 state_r; /* synopsys state_vector state_r */
|
|
9474 reg [2:0] /* synopsys enum state_info */
|
|
9475 state_e1;
|
|
9476
|
|
9477 //== ASCII state decoding
|
|
9478
|
|
9479 /*AUTOASCIIENUM(\"state_r\", \"state_ascii_r\", \"SM_\")*/
|
|
9480
|
|
9481 Typing \\[verilog-auto] will make this into:
|
|
9482
|
|
9483 ... same front matter ...
|
|
9484
|
|
9485 /*AUTOASCIIENUM(\"state_r\", \"state_ascii_r\", \"SM_\")*/
|
|
9486 // Beginning of automatic ASCII enum decoding
|
|
9487 reg [39:0] state_ascii_r; // Decode of state_r
|
|
9488 always @(state_r) begin
|
|
9489 case ({state_r})
|
|
9490 SM_IDLE: state_ascii_r = \"idle \";
|
|
9491 SM_SEND: state_ascii_r = \"send \";
|
|
9492 SM_WAIT1: state_ascii_r = \"wait1\";
|
|
9493 default: state_ascii_r = \"%Erro\";
|
|
9494 endcase
|
|
9495 end
|
|
9496 // End of automatics"
|
|
9497 (save-excursion
|
|
9498 (let* ((params (verilog-read-auto-params 2 3))
|
|
9499 (undecode-name (nth 0 params))
|
|
9500 (ascii-name (nth 1 params))
|
|
9501 (elim-regexp (nth 2 params))
|
|
9502 ;;
|
|
9503 (indent-pt (current-indentation))
|
|
9504 (modi (verilog-modi-current))
|
|
9505 ;;
|
|
9506 (sig-list-consts (append (verilog-modi-get-consts modi)
|
|
9507 (verilog-modi-get-gparams modi)))
|
|
9508 (sig-list-all (append (verilog-modi-get-regs modi)
|
|
9509 (verilog-modi-get-outputs modi)
|
|
9510 (verilog-modi-get-inouts modi)
|
|
9511 (verilog-modi-get-inputs modi)
|
|
9512 (verilog-modi-get-wires modi)))
|
|
9513 ;;
|
|
9514 (undecode-sig (or (assoc undecode-name sig-list-all)
|
|
9515 (error "%s: Signal %s not found in design" (verilog-point-text) undecode-name)))
|
|
9516 (undecode-enum (or (verilog-sig-enum undecode-sig)
|
|
9517 (error "%s: Signal %s does not have a enum tag" (verilog-point-text) undecode-name)))
|
|
9518 ;;
|
|
9519 (enum-sigs (or (verilog-signals-matching-enum sig-list-consts undecode-enum)
|
|
9520 (error "%s: No state definitions for %s" (verilog-point-text) undecode-enum)))
|
|
9521 ;;
|
|
9522 (enum-chars 0)
|
|
9523 (ascii-chars 0))
|
|
9524 ;;
|
|
9525 ;; Find number of ascii chars needed
|
|
9526 (let ((tmp-sigs enum-sigs))
|
|
9527 (while tmp-sigs
|
|
9528 (setq enum-chars (max enum-chars (length (verilog-sig-name (car tmp-sigs))))
|
|
9529 ascii-chars (max ascii-chars (length (verilog-enum-ascii
|
|
9530 (verilog-sig-name (car tmp-sigs))
|
|
9531 elim-regexp)))
|
|
9532 tmp-sigs (cdr tmp-sigs))))
|
|
9533 ;;
|
|
9534 (forward-line 1)
|
|
9535 (verilog-insert-indent "// Beginning of automatic ASCII enum decoding\n")
|
|
9536 (let ((decode-sig-list (list (list ascii-name (format "[%d:0]" (- (* ascii-chars 8) 1))
|
|
9537 (concat "Decode of " undecode-name) nil nil))))
|
|
9538 (verilog-insert-definition decode-sig-list "reg" indent-pt nil)
|
|
9539 (verilog-modi-cache-add-regs modi decode-sig-list))
|
|
9540 ;;
|
|
9541 (verilog-insert-indent "always @(" undecode-name ") begin\n")
|
|
9542 (setq indent-pt (+ indent-pt verilog-indent-level))
|
|
9543 (indent-to indent-pt)
|
|
9544 (insert "case ({" undecode-name "})\n")
|
|
9545 (setq indent-pt (+ indent-pt verilog-case-indent))
|
|
9546 ;;
|
|
9547 (let ((tmp-sigs enum-sigs)
|
|
9548 (chrfmt (format "%%-%ds %s = \"%%-%ds\";\n" (1+ (max 8 enum-chars))
|
|
9549 ascii-name ascii-chars))
|
|
9550 (errname (substring "%Error" 0 (min 6 ascii-chars))))
|
|
9551 (while tmp-sigs
|
|
9552 (verilog-insert-indent
|
|
9553 (format chrfmt (concat (verilog-sig-name (car tmp-sigs)) ":")
|
|
9554 (verilog-enum-ascii (verilog-sig-name (car tmp-sigs))
|
|
9555 elim-regexp)))
|
|
9556 (setq tmp-sigs (cdr tmp-sigs)))
|
|
9557 (verilog-insert-indent (format chrfmt "default:" errname)))
|
|
9558 ;;
|
|
9559 (setq indent-pt (- indent-pt verilog-case-indent))
|
|
9560 (verilog-insert-indent "endcase\n")
|
|
9561 (setq indent-pt (- indent-pt verilog-indent-level))
|
|
9562 (verilog-insert-indent "end\n"
|
|
9563 "// End of automatics\n")
|
|
9564 )))
|
|
9565
|
|
9566 (defun verilog-auto-templated-rel ()
|
|
9567 "Replace Templated relative line numbers with absolute line numbers.
|
|
9568 Internal use only. This hacks around the line numbers in AUTOINST Templates
|
|
9569 being different from the final output's line numbering."
|
|
9570 (let ((templateno 0) (template-line (list 0)))
|
|
9571 ;; Find line number each template is on
|
|
9572 (goto-char (point-min))
|
|
9573 (while (search-forward "AUTO_TEMPLATE" nil t)
|
|
9574 (setq templateno (1+ templateno))
|
|
9575 (setq template-line (cons (count-lines (point-min) (point)) template-line)))
|
|
9576 (setq template-line (nreverse template-line))
|
|
9577 ;; Replace T# L# with absolute line number
|
|
9578 (goto-char (point-min))
|
|
9579 (while (re-search-forward " Templated T\\([0-9]+\\) L\\([0-9]+\\)" nil t)
|
|
9580 (replace-match (concat " Templated "
|
|
9581 (int-to-string (+ (nth (string-to-int (match-string 1))
|
|
9582 template-line)
|
|
9583 (string-to-int (match-string 2)))))
|
|
9584 t t))))
|
|
9585
|
|
9586
|
|
9587 ;;
|
|
9588 ;; Auto top level
|
|
9589 ;;
|
|
9590
|
|
9591 (defun verilog-auto (&optional inject) ; Use verilog-inject-auto instead of passing a arg
|
|
9592 "Expand AUTO statements.
|
|
9593 Look for any /*AUTO...*/ commands in the code, as used in
|
|
9594 instantiations or argument headers. Update the list of signals
|
|
9595 following the /*AUTO...*/ command.
|
|
9596
|
|
9597 Use \\[verilog-delete-auto] to remove the AUTOs.
|
|
9598
|
|
9599 Use \\[verilog-inject-auto] to insert AUTOs for the first time.
|
|
9600
|
|
9601 Use \\[verilog-faq] for a pointer to frequently asked questions.
|
|
9602
|
|
9603 The hooks `verilog-before-auto-hook' and `verilog-auto-hook' are
|
|
9604 called before and after this function, respectively.
|
|
9605
|
|
9606 For example:
|
|
9607 module (/*AUTOARG*/)
|
|
9608 /*AUTOINPUT*/
|
|
9609 /*AUTOOUTPUT*/
|
|
9610 /*AUTOWIRE*/
|
|
9611 /*AUTOREG*/
|
|
9612 somesub sub #(/*AUTOINSTPARAM*/) (/*AUTOINST*/);
|
|
9613
|
|
9614 You can also update the AUTOs from the shell using:
|
|
9615 emacs --batch <filenames.v> -f verilog-batch-auto
|
|
9616 Or fix indentation with:
|
|
9617 emacs --batch <filenames.v> -f verilog-batch-indent
|
|
9618 Likewise, you can delete or inject AUTOs with:
|
|
9619 emacs --batch <filenames.v> -f verilog-batch-delete-auto
|
|
9620 emacs --batch <filenames.v> -f verilog-batch-inject-auto
|
|
9621
|
|
9622 Using \\[describe-function], see also:
|
|
9623 `verilog-auto-arg' for AUTOARG module instantiations
|
|
9624 `verilog-auto-ascii-enum' for AUTOASCIIENUM enumeration decoding
|
|
9625 `verilog-auto-inout-module' for AUTOINOUTMODULE copying i/o from elsewhere
|
|
9626 `verilog-auto-inout' for AUTOINOUT making hierarchy inouts
|
|
9627 `verilog-auto-input' for AUTOINPUT making hierarchy inputs
|
|
9628 `verilog-auto-inst' for AUTOINST instantiation pins
|
|
9629 `verilog-auto-star' for AUTOINST .* SystemVerilog pins
|
|
9630 `verilog-auto-inst-param' for AUTOINSTPARAM instantiation params
|
|
9631 `verilog-auto-output' for AUTOOUTPUT making hierarchy outputs
|
|
9632 `verilog-auto-output-every' for AUTOOUTPUTEVERY making all outputs
|
|
9633 `verilog-auto-reg' for AUTOREG registers
|
|
9634 `verilog-auto-reg-input' for AUTOREGINPUT instantiation registers
|
|
9635 `verilog-auto-reset' for AUTORESET flop resets
|
|
9636 `verilog-auto-sense' for AUTOSENSE always sensitivity lists
|
|
9637 `verilog-auto-tieoff' for AUTOTIEOFF output tieoffs
|
|
9638 `verilog-auto-unused' for AUTOUNUSED unused inputs/inouts
|
|
9639 `verilog-auto-wire' for AUTOWIRE instantiation wires
|
|
9640
|
|
9641 `verilog-read-defines' for reading `define values
|
|
9642 `verilog-read-includes' for reading `includes
|
|
9643
|
|
9644 If you have bugs with these autos, try contacting the AUTOAUTHOR
|
|
9645 Wilson Snyder (wsnyder@wsnyder.org), and/or see http://www.veripool.com."
|
|
9646 (interactive)
|
|
9647 (unless noninteractive (message "Updating AUTOs..."))
|
|
9648 (if (featurep 'dinotrace)
|
|
9649 (dinotrace-unannotate-all))
|
|
9650 (let ((oldbuf (if (not (buffer-modified-p))
|
|
9651 (buffer-string)))
|
|
9652 ;; Before version 20, match-string with font-lock returns a
|
|
9653 ;; vector that is not equal to the string. IE if on "input"
|
|
9654 ;; nil==(equal "input" (progn (looking-at "input") (match-string 0)))
|
|
9655 (fontlocked (when (and (boundp 'font-lock-mode)
|
|
9656 font-lock-mode)
|
|
9657 (font-lock-mode nil)
|
|
9658 t)))
|
|
9659 (unwind-protect
|
|
9660 (save-excursion
|
|
9661 ;; If we're not in verilog-mode, change syntax table so parsing works right
|
|
9662 (unless (eq major-mode `verilog-mode) (verilog-mode))
|
|
9663 ;; Allow user to customize
|
|
9664 (run-hooks 'verilog-before-auto-hook)
|
|
9665 ;; Try to save the user from needing to revert-file to reread file local-variables
|
|
9666 (verilog-auto-reeval-locals)
|
|
9667 (verilog-read-auto-lisp (point-min) (point-max))
|
|
9668 (verilog-getopt-flags)
|
|
9669 ;; These two may seem obvious to do always, but on large includes it can be way too slow
|
|
9670 (when verilog-auto-read-includes
|
|
9671 (verilog-read-includes)
|
|
9672 (verilog-read-defines nil nil t))
|
|
9673 ;; This particular ordering is important
|
|
9674 ;; INST: Lower modules correct, no internal dependencies, FIRST
|
|
9675 (verilog-preserve-cache
|
|
9676 ;; Clear existing autos else we'll be screwed by existing ones
|
|
9677 (verilog-delete-auto)
|
|
9678 ;; Injection if appropriate
|
|
9679 (when inject
|
|
9680 (verilog-inject-inst)
|
|
9681 (verilog-inject-sense)
|
|
9682 (verilog-inject-arg))
|
|
9683 ;;
|
|
9684 (verilog-auto-search-do "/*AUTOINSTPARAM*/" 'verilog-auto-inst-param)
|
|
9685 (verilog-auto-search-do "/*AUTOINST*/" 'verilog-auto-inst)
|
|
9686 (verilog-auto-search-do ".*" 'verilog-auto-star)
|
|
9687 ;; Doesn't matter when done, but combine it with a common changer
|
|
9688 (verilog-auto-re-search-do "/\\*\\(AUTOSENSE\\|AS\\)\\*/" 'verilog-auto-sense)
|
|
9689 (verilog-auto-re-search-do "/\\*AUTORESET\\*/" 'verilog-auto-reset)
|
|
9690 ;; Must be done before autoin/out as creates a reg
|
|
9691 (verilog-auto-re-search-do "/\\*AUTOASCIIENUM([^)]*)\\*/" 'verilog-auto-ascii-enum)
|
|
9692 ;;
|
|
9693 ;; first in/outs from other files
|
|
9694 (verilog-auto-re-search-do "/\\*AUTOINOUTMODULE([^)]*)\\*/" 'verilog-auto-inout-module)
|
|
9695 ;; next in/outs which need previous sucked inputs first
|
|
9696 (verilog-auto-search-do "/*AUTOOUTPUT*/" 'verilog-auto-output)
|
|
9697 (verilog-auto-search-do "/*AUTOINPUT*/" 'verilog-auto-input)
|
|
9698 (verilog-auto-search-do "/*AUTOINOUT*/" 'verilog-auto-inout)
|
|
9699 ;; Then tie off those in/outs
|
|
9700 (verilog-auto-search-do "/*AUTOTIEOFF*/" 'verilog-auto-tieoff)
|
|
9701 ;; Wires/regs must be after inputs/outputs
|
|
9702 (verilog-auto-search-do "/*AUTOWIRE*/" 'verilog-auto-wire)
|
|
9703 (verilog-auto-search-do "/*AUTOREG*/" 'verilog-auto-reg)
|
|
9704 (verilog-auto-search-do "/*AUTOREGINPUT*/" 'verilog-auto-reg-input)
|
|
9705 ;; outputevery needs AUTOOUTPUTs done first
|
|
9706 (verilog-auto-search-do "/*AUTOOUTPUTEVERY*/" 'verilog-auto-output-every)
|
|
9707 ;; After we've created all new variables
|
|
9708 (verilog-auto-search-do "/*AUTOUNUSED*/" 'verilog-auto-unused)
|
|
9709 ;; Must be after all inputs outputs are generated
|
|
9710 (verilog-auto-search-do "/*AUTOARG*/" 'verilog-auto-arg)
|
|
9711 ;; Fix line numbers (comments only)
|
|
9712 (verilog-auto-templated-rel)
|
|
9713 )
|
|
9714 ;;
|
|
9715 (run-hooks 'verilog-auto-hook)
|
|
9716 ;;
|
|
9717 (set (make-local-variable 'verilog-auto-update-tick) (buffer-modified-tick))
|
|
9718 ;;
|
|
9719 ;; If end result is same as when started, clear modified flag
|
|
9720 (cond ((and oldbuf (equal oldbuf (buffer-string)))
|
|
9721 (set-buffer-modified-p nil)
|
|
9722 (unless noninteractive (message "Updating AUTOs...done (no changes)")))
|
|
9723 (t (unless noninteractive (message "Updating AUTOs...done")))))
|
|
9724 ;; Unwind forms
|
|
9725 (progn
|
|
9726 ;; Restore font-lock
|
|
9727 (when fontlocked (font-lock-mode t)))
|
|
9728 )))
|
|
9729
|
|
9730
|
|
9731 ;;
|
|
9732 ;; Skeleton based code insertion
|
|
9733 ;;
|
|
9734 (defvar verilog-template-map nil
|
|
9735 "Keymap used in Verilog mode for smart template operations.")
|
|
9736
|
|
9737 (let ((verilog-mp (make-sparse-keymap)))
|
|
9738 (define-key verilog-mp "a" 'verilog-sk-always)
|
|
9739 (define-key verilog-mp "b" 'verilog-sk-begin)
|
|
9740 (define-key verilog-mp "c" 'verilog-sk-case)
|
|
9741 (define-key verilog-mp "f" 'verilog-sk-for)
|
|
9742 (define-key verilog-mp "g" 'verilog-sk-generate)
|
|
9743 (define-key verilog-mp "h" 'verilog-sk-header)
|
|
9744 (define-key verilog-mp "i" 'verilog-sk-initial)
|
|
9745 (define-key verilog-mp "j" 'verilog-sk-fork)
|
|
9746 (define-key verilog-mp "m" 'verilog-sk-module)
|
|
9747 (define-key verilog-mp "p" 'verilog-sk-primitive)
|
|
9748 (define-key verilog-mp "r" 'verilog-sk-repeat)
|
|
9749 (define-key verilog-mp "s" 'verilog-sk-specify)
|
|
9750 (define-key verilog-mp "t" 'verilog-sk-task)
|
|
9751 (define-key verilog-mp "w" 'verilog-sk-while)
|
|
9752 (define-key verilog-mp "x" 'verilog-sk-casex)
|
|
9753 (define-key verilog-mp "z" 'verilog-sk-casez)
|
|
9754 (define-key verilog-mp "?" 'verilog-sk-if)
|
|
9755 (define-key verilog-mp ":" 'verilog-sk-else-if)
|
|
9756 (define-key verilog-mp "/" 'verilog-sk-comment)
|
|
9757 (define-key verilog-mp "A" 'verilog-sk-assign)
|
|
9758 (define-key verilog-mp "F" 'verilog-sk-function)
|
|
9759 (define-key verilog-mp "I" 'verilog-sk-input)
|
|
9760 (define-key verilog-mp "O" 'verilog-sk-output)
|
|
9761 (define-key verilog-mp "S" 'verilog-sk-state-machine)
|
|
9762 (define-key verilog-mp "=" 'verilog-sk-inout)
|
|
9763 (define-key verilog-mp "W" 'verilog-sk-wire)
|
|
9764 (define-key verilog-mp "R" 'verilog-sk-reg)
|
|
9765 (define-key verilog-mp "D" 'verilog-sk-define-signal)
|
|
9766 (setq verilog-template-map verilog-mp))
|
|
9767
|
|
9768 ;;
|
|
9769 ;; Place the templates into Verilog Mode. They may be inserted under any key.
|
|
9770 ;; C-c C-t will be the default. If you use templates a lot, you
|
|
9771 ;; may want to consider moving the binding to another key in your .emacs
|
|
9772 ;; file.
|
|
9773 ;;
|
|
9774 ;(define-key verilog-mode-map "\C-ct" verilog-template-map)
|
|
9775 (define-key verilog-mode-map "\C-c\C-t" verilog-template-map)
|
|
9776
|
|
9777 ;;; ---- statement skeletons ------------------------------------------
|
|
9778
|
|
9779 (define-skeleton verilog-sk-prompt-condition
|
|
9780 "Prompt for the loop condition."
|
|
9781 "[condition]: " str )
|
|
9782
|
|
9783 (define-skeleton verilog-sk-prompt-init
|
|
9784 "Prompt for the loop init statement."
|
|
9785 "[initial statement]: " str )
|
|
9786
|
|
9787 (define-skeleton verilog-sk-prompt-inc
|
|
9788 "Prompt for the loop increment statement."
|
|
9789 "[increment statement]: " str )
|
|
9790
|
|
9791 (define-skeleton verilog-sk-prompt-name
|
|
9792 "Prompt for the name of something."
|
|
9793 "[name]: " str)
|
|
9794
|
|
9795 (define-skeleton verilog-sk-prompt-clock
|
|
9796 "Prompt for the name of something."
|
|
9797 "name and edge of clock(s): " str)
|
|
9798
|
|
9799 (defvar verilog-sk-reset nil)
|
|
9800 (defun verilog-sk-prompt-reset ()
|
|
9801 "Prompt for the name of a state machine reset."
|
|
9802 (setq verilog-sk-reset (read-input "name of reset: " "rst")))
|
|
9803
|
|
9804
|
|
9805 (define-skeleton verilog-sk-prompt-state-selector
|
|
9806 "Prompt for the name of a state machine selector."
|
|
9807 "name of selector (eg {a,b,c,d}): " str )
|
|
9808
|
|
9809 (define-skeleton verilog-sk-prompt-output
|
|
9810 "Prompt for the name of something."
|
|
9811 "output: " str)
|
|
9812
|
|
9813 (define-skeleton verilog-sk-prompt-msb
|
|
9814 "Prompt for least significant bit specification."
|
|
9815 "msb:" str & ?: & (verilog-sk-prompt-lsb) | -1 )
|
|
9816
|
|
9817 (define-skeleton verilog-sk-prompt-lsb
|
|
9818 "Prompt for least significant bit specification."
|
|
9819 "lsb:" str )
|
|
9820
|
|
9821 (defvar verilog-sk-p nil)
|
|
9822 (define-skeleton verilog-sk-prompt-width
|
|
9823 "Prompt for a width specification."
|
|
9824 ()
|
|
9825 (progn
|
|
9826 (setq verilog-sk-p (point))
|
|
9827 (verilog-sk-prompt-msb)
|
|
9828 (if (> (point) verilog-sk-p) "] " " ")))
|
|
9829
|
|
9830 (defun verilog-sk-header ()
|
|
9831 "Insert a descriptive header at the top of the file."
|
|
9832 (interactive "*")
|
|
9833 (save-excursion
|
|
9834 (goto-char (point-min))
|
|
9835 (verilog-sk-header-tmpl)))
|
|
9836
|
|
9837 (define-skeleton verilog-sk-header-tmpl
|
|
9838 "Insert a comment block containing the module title, author, etc."
|
|
9839 "[Description]: "
|
|
9840 "// -*- Mode: Verilog -*-"
|
|
9841 "\n// Filename : " (buffer-name)
|
|
9842 "\n// Description : " str
|
|
9843 "\n// Author : " (user-full-name)
|
|
9844 "\n// Created On : " (current-time-string)
|
|
9845 "\n// Last Modified By: ."
|
|
9846 "\n// Last Modified On: ."
|
|
9847 "\n// Update Count : 0"
|
|
9848 "\n// Status : Unknown, Use with caution!"
|
|
9849 "\n")
|
|
9850
|
|
9851 (define-skeleton verilog-sk-module
|
|
9852 "Insert a module definition."
|
|
9853 ()
|
|
9854 > "module " (verilog-sk-prompt-name) " (/*AUTOARG*/ ) ;" \n
|
|
9855 > _ \n
|
|
9856 > (- verilog-indent-level-behavioral) "endmodule" (progn (electric-verilog-terminate-line) nil))
|
|
9857
|
|
9858 (define-skeleton verilog-sk-primitive
|
|
9859 "Insert a task definition."
|
|
9860 ()
|
|
9861 > "primitive " (verilog-sk-prompt-name) " ( " (verilog-sk-prompt-output) ("input:" ", " str ) " );"\n
|
|
9862 > _ \n
|
|
9863 > (- verilog-indent-level-behavioral) "endprimitive" (progn (electric-verilog-terminate-line) nil))
|
|
9864
|
|
9865 (define-skeleton verilog-sk-task
|
|
9866 "Insert a task definition."
|
|
9867 ()
|
|
9868 > "task " (verilog-sk-prompt-name) & ?; \n
|
|
9869 > _ \n
|
|
9870 > "begin" \n
|
|
9871 > \n
|
|
9872 > (- verilog-indent-level-behavioral) "end" \n
|
|
9873 > (- verilog-indent-level-behavioral) "endtask" (progn (electric-verilog-terminate-line) nil))
|
|
9874
|
|
9875 (define-skeleton verilog-sk-function
|
|
9876 "Insert a function definition."
|
|
9877 ()
|
|
9878 > "function [" (verilog-sk-prompt-width) | -1 (verilog-sk-prompt-name) ?; \n
|
|
9879 > _ \n
|
|
9880 > "begin" \n
|
|
9881 > \n
|
|
9882 > (- verilog-indent-level-behavioral) "end" \n
|
|
9883 > (- verilog-indent-level-behavioral) "endfunction" (progn (electric-verilog-terminate-line) nil))
|
|
9884
|
|
9885 (define-skeleton verilog-sk-always
|
|
9886 "Insert always block. Uses the minibuffer to prompt
|
|
9887 for sensitivity list."
|
|
9888 ()
|
|
9889 > "always @ ( /*AUTOSENSE*/ ) begin\n"
|
|
9890 > _ \n
|
|
9891 > (- verilog-indent-level-behavioral) "end" \n >
|
|
9892 )
|
|
9893
|
|
9894 (define-skeleton verilog-sk-initial
|
|
9895 "Insert an initial block."
|
|
9896 ()
|
|
9897 > "initial begin\n"
|
|
9898 > _ \n
|
|
9899 > (- verilog-indent-level-behavioral) "end" \n > )
|
|
9900
|
|
9901 (define-skeleton verilog-sk-specify
|
|
9902 "Insert specify block. "
|
|
9903 ()
|
|
9904 > "specify\n"
|
|
9905 > _ \n
|
|
9906 > (- verilog-indent-level-behavioral) "endspecify" \n > )
|
|
9907
|
|
9908 (define-skeleton verilog-sk-generate
|
|
9909 "Insert generate block. "
|
|
9910 ()
|
|
9911 > "generate\n"
|
|
9912 > _ \n
|
|
9913 > (- verilog-indent-level-behavioral) "endgenerate" \n > )
|
|
9914
|
|
9915 (define-skeleton verilog-sk-begin
|
|
9916 "Insert begin end block. Uses the minibuffer to prompt for name"
|
|
9917 ()
|
|
9918 > "begin" (verilog-sk-prompt-name) \n
|
|
9919 > _ \n
|
|
9920 > (- verilog-indent-level-behavioral) "end"
|
|
9921 )
|
|
9922
|
|
9923 (define-skeleton verilog-sk-fork
|
|
9924 "Insert an fork join block."
|
|
9925 ()
|
|
9926 > "fork\n"
|
|
9927 > "begin" \n
|
|
9928 > _ \n
|
|
9929 > (- verilog-indent-level-behavioral) "end" \n
|
|
9930 > "begin" \n
|
|
9931 > \n
|
|
9932 > (- verilog-indent-level-behavioral) "end" \n
|
|
9933 > (- verilog-indent-level-behavioral) "join" \n
|
|
9934 > )
|
|
9935
|
|
9936
|
|
9937 (define-skeleton verilog-sk-case
|
|
9938 "Build skeleton case statement, prompting for the selector expression,
|
|
9939 and the case items."
|
|
9940 "[selector expression]: "
|
|
9941 > "case (" str ") " \n
|
|
9942 > ("case selector: " str ": begin" \n > _ \n > (- verilog-indent-level-behavioral) "end" \n )
|
|
9943 resume: > (- verilog-case-indent) "endcase" (progn (electric-verilog-terminate-line) nil))
|
|
9944
|
|
9945 (define-skeleton verilog-sk-casex
|
|
9946 "Build skeleton casex statement, prompting for the selector expression,
|
|
9947 and the case items."
|
|
9948 "[selector expression]: "
|
|
9949 > "casex (" str ") " \n
|
|
9950 > ("case selector: " str ": begin" \n > _ \n > (- verilog-indent-level-behavioral) "end" \n )
|
|
9951 resume: > (- verilog-case-indent) "endcase" (progn (electric-verilog-terminate-line) nil))
|
|
9952
|
|
9953 (define-skeleton verilog-sk-casez
|
|
9954 "Build skeleton casez statement, prompting for the selector expression,
|
|
9955 and the case items."
|
|
9956 "[selector expression]: "
|
|
9957 > "casez (" str ") " \n
|
|
9958 > ("case selector: " str ": begin" \n > _ \n > (- verilog-indent-level-behavioral) "end" \n )
|
|
9959 resume: > (- verilog-case-indent) "endcase" (progn (electric-verilog-terminate-line) nil))
|
|
9960
|
|
9961 (define-skeleton verilog-sk-if
|
|
9962 "Insert a skeleton if statement."
|
|
9963 > "if (" (verilog-sk-prompt-condition) & ")" " begin" \n
|
|
9964 > _ \n
|
|
9965 > (- verilog-indent-level-behavioral) "end " \n )
|
|
9966
|
|
9967 (define-skeleton verilog-sk-else-if
|
|
9968 "Insert a skeleton else if statement."
|
|
9969 > (verilog-indent-line) "else if ("
|
|
9970 (progn (setq verilog-sk-p (point)) nil) (verilog-sk-prompt-condition) (if (> (point) verilog-sk-p) ") " -1 ) & " begin" \n
|
|
9971 > _ \n
|
|
9972 > "end" (progn (electric-verilog-terminate-line) nil))
|
|
9973
|
|
9974 (define-skeleton verilog-sk-datadef
|
|
9975 "Common routine to get data definition"
|
|
9976 ()
|
|
9977 (verilog-sk-prompt-width) | -1 ("name (RET to end):" str ", ") -2 ";" \n)
|
|
9978
|
|
9979 (define-skeleton verilog-sk-input
|
|
9980 "Insert an input definition."
|
|
9981 ()
|
|
9982 > "input [" (verilog-sk-datadef))
|
|
9983
|
|
9984 (define-skeleton verilog-sk-output
|
|
9985 "Insert an output definition."
|
|
9986 ()
|
|
9987 > "output [" (verilog-sk-datadef))
|
|
9988
|
|
9989 (define-skeleton verilog-sk-inout
|
|
9990 "Insert an inout definition."
|
|
9991 ()
|
|
9992 > "inout [" (verilog-sk-datadef))
|
|
9993
|
|
9994 (defvar verilog-sk-signal nil)
|
|
9995 (define-skeleton verilog-sk-def-reg
|
|
9996 "Insert a reg definition."
|
|
9997 ()
|
|
9998 > "reg [" (verilog-sk-prompt-width) | -1 verilog-sk-signal ";" \n (verilog-pretty-declarations) )
|
|
9999
|
|
10000 (defun verilog-sk-define-signal ()
|
|
10001 "Insert a definition of signal under point at top of module."
|
|
10002 (interactive "*")
|
|
10003 (let* (
|
|
10004 (sig-re "[a-zA-Z0-9_]*")
|
|
10005 (v1 (buffer-substring
|
|
10006 (save-excursion
|
|
10007 (skip-chars-backward sig-re)
|
|
10008 (point))
|
|
10009 (save-excursion
|
|
10010 (skip-chars-forward sig-re)
|
|
10011 (point))))
|
|
10012 )
|
|
10013 (if (not (member v1 verilog-keywords))
|
|
10014 (save-excursion
|
|
10015 (setq verilog-sk-signal v1)
|
|
10016 (verilog-beg-of-defun)
|
|
10017 (verilog-end-of-statement)
|
|
10018 (verilog-forward-syntactic-ws)
|
|
10019 (verilog-sk-def-reg)
|
|
10020 (message "signal at point is %s" v1))
|
|
10021 (message "object at point (%s) is a keyword" v1))
|
|
10022 )
|
|
10023 )
|
|
10024
|
|
10025
|
|
10026 (define-skeleton verilog-sk-wire
|
|
10027 "Insert a wire definition."
|
|
10028 ()
|
|
10029 > "wire [" (verilog-sk-datadef))
|
|
10030
|
|
10031 (define-skeleton verilog-sk-reg
|
|
10032 "Insert a reg definition."
|
|
10033 ()
|
|
10034 > "reg [" (verilog-sk-datadef))
|
|
10035
|
|
10036 (define-skeleton verilog-sk-assign
|
|
10037 "Insert a skeleton assign statement."
|
|
10038 ()
|
|
10039 > "assign " (verilog-sk-prompt-name) " = " _ ";" \n)
|
|
10040
|
|
10041 (define-skeleton verilog-sk-while
|
|
10042 "Insert a skeleton while loop statement."
|
|
10043 ()
|
|
10044 > "while (" (verilog-sk-prompt-condition) ") begin" \n
|
|
10045 > _ \n
|
|
10046 > (- verilog-indent-level-behavioral) "end " (progn (electric-verilog-terminate-line) nil))
|
|
10047
|
|
10048 (define-skeleton verilog-sk-repeat
|
|
10049 "Insert a skeleton repeat loop statement."
|
|
10050 ()
|
|
10051 > "repeat (" (verilog-sk-prompt-condition) ") begin" \n
|
|
10052 > _ \n
|
|
10053 > (- verilog-indent-level-behavioral) "end " (progn (electric-verilog-terminate-line) nil))
|
|
10054
|
|
10055 (define-skeleton verilog-sk-for
|
|
10056 "Insert a skeleton while loop statement."
|
|
10057 ()
|
|
10058 > "for ("
|
|
10059 (verilog-sk-prompt-init) "; "
|
|
10060 (verilog-sk-prompt-condition) "; "
|
|
10061 (verilog-sk-prompt-inc)
|
|
10062 ") begin" \n
|
|
10063 > _ \n
|
|
10064 > (- verilog-indent-level-behavioral) "end " (progn (electric-verilog-terminate-line) nil))
|
|
10065
|
|
10066 (define-skeleton verilog-sk-comment
|
|
10067 "Inserts three comment lines, making a display comment."
|
|
10068 ()
|
|
10069 > "/*\n"
|
|
10070 > "* " _ \n
|
|
10071 > "*/")
|
|
10072
|
|
10073 (define-skeleton verilog-sk-state-machine
|
|
10074 "Insert a state machine definition."
|
|
10075 "Name of state variable: "
|
|
10076 '(setq input "state")
|
|
10077 > "// State registers for " str | -23 \n
|
|
10078 '(setq verilog-sk-state str)
|
|
10079 > "reg [" (verilog-sk-prompt-width) | -1 verilog-sk-state ", next_" verilog-sk-state ?; \n
|
|
10080 '(setq input nil)
|
|
10081 > \n
|
|
10082 > "// State FF for " verilog-sk-state \n
|
|
10083 > "always @ ( " (read-string "clock:" "posedge clk") " or " (verilog-sk-prompt-reset) " ) begin" \n
|
|
10084 > "if ( " verilog-sk-reset " ) " verilog-sk-state " = 0; else" \n
|
|
10085 > verilog-sk-state " = next_" verilog-sk-state ?; \n
|
|
10086 > (- verilog-indent-level-behavioral) "end" (progn (electric-verilog-terminate-line) nil)
|
|
10087 > \n
|
|
10088 > "// Next State Logic for " verilog-sk-state \n
|
|
10089 > "always @ ( /*AUTOSENSE*/ ) begin\n"
|
|
10090 > "case (" (verilog-sk-prompt-state-selector) ") " \n
|
|
10091 > ("case selector: " str ": begin" \n > "next_" verilog-sk-state " = " _ ";" \n > (- verilog-indent-level-behavioral) "end" \n )
|
|
10092 resume: > (- verilog-case-indent) "endcase" (progn (electric-verilog-terminate-line) nil)
|
|
10093 > (- verilog-indent-level-behavioral) "end" (progn (electric-verilog-terminate-line) nil))
|
|
10094
|
|
10095 ;; Eliminate compile warning
|
|
10096 (eval-when-compile
|
|
10097 (if (not (boundp 'mode-popup-menu))
|
|
10098 (defvar mode-popup-menu nil "Compatibility with XEmacs.")))
|
|
10099
|
|
10100 ;; ---- add menu 'Statements' in Verilog mode (MH)
|
|
10101 (defun verilog-add-statement-menu ()
|
|
10102 "Add the menu 'Statements' to the menu bar in Verilog mode."
|
|
10103 (if (featurep 'xemacs)
|
|
10104 (progn
|
|
10105 (easy-menu-add verilog-stmt-menu)
|
|
10106 (easy-menu-add verilog-menu)
|
|
10107 (setq mode-popup-menu (cons "Verilog Mode" verilog-stmt-menu)))))
|
|
10108
|
|
10109 (add-hook 'verilog-mode-hook 'verilog-add-statement-menu)
|
|
10110
|
|
10111
|
|
10112
|
|
10113 ;;
|
|
10114 ;; Include file loading with mouse/return event
|
|
10115 ;;
|
|
10116 ;; idea & first impl.: M. Rouat (eldo-mode.el)
|
|
10117 ;; second (emacs/xemacs) impl.: G. Van der Plas (spice-mode.el)
|
|
10118
|
|
10119 (if (featurep 'xemacs)
|
|
10120 (require 'overlay)
|
|
10121 (require 'lucid)) ;; what else can we do ??
|
|
10122
|
|
10123 (defconst verilog-include-file-regexp
|
|
10124 "^`include\\s-+\"\\([^\n\"]*\\)\""
|
|
10125 "Regexp that matches the include file.")
|
|
10126
|
|
10127 (defvar verilog-mode-mouse-map nil
|
|
10128 "Map containing mouse bindings for `verilog-mode'.")
|
|
10129
|
|
10130 (if verilog-mode-mouse-map
|
|
10131 ()
|
|
10132 (let ((map (make-sparse-keymap))) ; as described in info pages, make a map
|
|
10133 (set-keymap-parent map verilog-mode-map)
|
|
10134 ;; mouse button bindings
|
|
10135 (define-key map "\r" 'verilog-load-file-at-point)
|
|
10136 (if (featurep 'xemacs)
|
|
10137 (define-key map 'button2 'verilog-load-file-at-mouse);ffap-at-mouse ?
|
|
10138 (define-key map [mouse-2] 'verilog-load-file-at-mouse))
|
|
10139 (if (featurep 'xemacs)
|
|
10140 (define-key map 'Sh-button2 'mouse-yank) ; you wanna paste don't you ?
|
|
10141 (define-key map [S-mouse-2] 'mouse-yank-at-click))
|
|
10142 (setq verilog-mode-mouse-map map))) ;; copy complete map now
|
|
10143
|
|
10144 ;; create set-extent-keymap procedure when it does not exist
|
|
10145 (eval-and-compile
|
|
10146 (unless (fboundp 'set-extent-keymap)
|
|
10147 (defun set-extent-keymap (extent keymap)
|
|
10148 "fallback version of set-extent-keymap (for emacs 2[01])"
|
|
10149 (set-extent-property extent 'local-map keymap))))
|
|
10150
|
|
10151 (defun verilog-colorize-include-files (beg end old-len)
|
|
10152 "This function colorizes included files when the mouse passes over them.
|
|
10153 Clicking on the middle-mouse button loads them in a buffer (as in dired)."
|
|
10154 (save-excursion
|
|
10155 (save-match-data
|
|
10156 (let (end-point)
|
|
10157 (goto-char end)
|
|
10158 (setq end-point (verilog-get-end-of-line))
|
|
10159 (goto-char beg)
|
|
10160 (beginning-of-line) ; scan entire line !
|
|
10161 ;; delete overlays existing on this line
|
|
10162 (let ((overlays (overlays-in (point) end-point)))
|
|
10163 (while overlays
|
|
10164 (if (and
|
|
10165 (overlay-get (car overlays) 'detachable)
|
|
10166 (overlay-get (car overlays) 'verilog-include-file))
|
|
10167 (delete-overlay (car overlays)))
|
|
10168 (setq overlays (cdr overlays)))) ; let
|
|
10169 ;; make new ones, could reuse deleted one ?
|
|
10170 (while (search-forward-regexp verilog-include-file-regexp end-point t)
|
|
10171 (let (extent)
|
|
10172 (goto-char (match-beginning 1))
|
|
10173 (or (extent-at (point) (buffer-name) 'mouse-face) ;; not yet extended
|
|
10174 (progn
|
|
10175 (setq extent (make-extent (match-beginning 1) (match-end 1)))
|
|
10176 (set-extent-property extent 'start-closed 't)
|
|
10177 (set-extent-property extent 'end-closed 't)
|
|
10178 (set-extent-property extent 'detachable 't)
|
|
10179 (set-extent-property extent 'verilog-include-file 't)
|
|
10180 (set-extent-property extent 'mouse-face 'highlight)
|
|
10181 (set-extent-keymap extent verilog-mode-mouse-map)))))))))
|
|
10182
|
|
10183
|
|
10184 (defun verilog-colorize-include-files-buffer ()
|
|
10185 "Colorize a include file."
|
|
10186 (interactive)
|
|
10187 ;; delete overlays
|
|
10188 (let ((overlays (overlays-in (point-min) (point-max))))
|
|
10189 (while overlays
|
|
10190 (if (and
|
|
10191 (overlay-get (car overlays) 'detachable)
|
|
10192 (overlay-get (car overlays) 'verilog-include-file))
|
|
10193 (delete-overlay (car overlays)))
|
|
10194 (setq overlays (cdr overlays)))) ; let
|
|
10195 ;; remake overlays
|
|
10196 (verilog-colorize-include-files (point-min) (point-max) nil))
|
|
10197
|
|
10198 ;; ffap-at-mouse isn't useful for verilog mode. It uses library paths.
|
|
10199 ;; so define this function to do more or less the same as ffap-at-mouse
|
|
10200 ;; but first resolve filename...
|
|
10201 (defun verilog-load-file-at-mouse (event)
|
|
10202 "Load file under button 2 click's EVENT.
|
|
10203 Files are checked based on `verilog-library-directories'."
|
|
10204 (interactive "@e")
|
|
10205 (save-excursion ;; implement a verilog specific ffap-at-mouse
|
|
10206 (mouse-set-point event)
|
|
10207 (beginning-of-line)
|
|
10208 (if (looking-at verilog-include-file-regexp)
|
|
10209 (if (and (car (verilog-library-filenames
|
|
10210 (match-string 1) (buffer-file-name)))
|
|
10211 (file-readable-p (car (verilog-library-filenames
|
|
10212 (match-string 1) (buffer-file-name)))))
|
|
10213 (find-file (car (verilog-library-filenames
|
|
10214 (match-string 1) (buffer-file-name))))
|
|
10215 (progn
|
|
10216 (message
|
|
10217 "File '%s' isn't readable, use shift-mouse2 to paste in this field"
|
|
10218 (match-string 1))))
|
|
10219 )))
|
|
10220
|
|
10221 ;; ffap isn't useable for verilog mode. It uses library paths.
|
|
10222 ;; so define this function to do more or less the same as ffap
|
|
10223 ;; but first resolve filename...
|
|
10224 (defun verilog-load-file-at-point ()
|
|
10225 "Load file under point.
|
|
10226 Files are checked based on `verilog-library-directories'."
|
|
10227 (interactive)
|
|
10228 (save-excursion ;; implement a verilog specific ffap
|
|
10229 (beginning-of-line)
|
|
10230 (if (looking-at verilog-include-file-regexp)
|
|
10231 (if (and
|
|
10232 (car (verilog-library-filenames
|
|
10233 (match-string 1) (buffer-file-name)))
|
|
10234 (file-readable-p (car (verilog-library-filenames
|
|
10235 (match-string 1) (buffer-file-name)))))
|
|
10236 (find-file (car (verilog-library-filenames
|
|
10237 (match-string 1) (buffer-file-name))))))
|
|
10238 ))
|
|
10239
|
|
10240
|
|
10241 ;;
|
|
10242 ;; Bug reporting
|
|
10243 ;;
|
|
10244
|
|
10245 (defun verilog-faq ()
|
|
10246 "Tell the user their current version, and where to get the FAQ etc."
|
|
10247 (interactive)
|
|
10248 (with-output-to-temp-buffer "*verilog-mode help*"
|
|
10249 (princ (format "You are using verilog-mode %s\n" verilog-mode-version))
|
|
10250 (princ "\n")
|
|
10251 (princ "For new releases, see http://www.verilog.com\n")
|
|
10252 (princ "\n")
|
|
10253 (princ "For frequently asked questions, see http://www.veripool.com/verilog-mode-faq.html\n")
|
|
10254 (princ "\n")
|
|
10255 (princ "To submit a bug, use M-x verilog-submit-bug-report\n")
|
|
10256 (princ "\n")))
|
|
10257
|
|
10258 (defun verilog-submit-bug-report ()
|
|
10259 "Submit via mail a bug report on verilog-mode.el."
|
|
10260 (interactive)
|
|
10261 (let ((reporter-prompt-for-summary-p t))
|
|
10262 (reporter-submit-bug-report
|
|
10263 "mac@verilog.com"
|
|
10264 (concat "verilog-mode v" verilog-mode-version)
|
|
10265 '(
|
|
10266 verilog-align-ifelse
|
|
10267 verilog-auto-endcomments
|
|
10268 verilog-auto-hook
|
|
10269 verilog-auto-indent-on-newline
|
|
10270 verilog-auto-inst-vector
|
|
10271 verilog-auto-inst-template-numbers
|
|
10272 verilog-auto-lineup
|
|
10273 verilog-auto-newline
|
|
10274 verilog-auto-save-policy
|
|
10275 verilog-auto-sense-defines-constant
|
|
10276 verilog-auto-sense-include-inputs
|
|
10277 verilog-before-auto-hook
|
|
10278 verilog-case-indent
|
|
10279 verilog-cexp-indent
|
|
10280 verilog-compiler
|
|
10281 verilog-coverage
|
|
10282 verilog-highlight-translate-off
|
|
10283 verilog-indent-begin-after-if
|
|
10284 verilog-indent-declaration-macros
|
|
10285 verilog-indent-level
|
|
10286 verilog-indent-level-behavioral
|
|
10287 verilog-indent-level-declaration
|
|
10288 verilog-indent-level-directive
|
|
10289 verilog-indent-level-module
|
|
10290 verilog-indent-lists
|
|
10291 verilog-library-flags
|
|
10292 verilog-library-directories
|
|
10293 verilog-library-extensions
|
|
10294 verilog-library-files
|
|
10295 verilog-linter
|
|
10296 verilog-minimum-comment-distance
|
|
10297 verilog-mode-hook
|
|
10298 verilog-simulator
|
|
10299 verilog-tab-always-indent
|
|
10300 verilog-tab-to-comment
|
|
10301 )
|
|
10302 nil nil
|
|
10303 (concat "Hi Mac,
|
|
10304
|
|
10305 I want to report a bug. I've read the `Bugs' section of `Info' on
|
|
10306 Emacs, so I know how to make a clear and unambiguous report. To get
|
|
10307 to that Info section, I typed
|
|
10308
|
|
10309 M-x info RET m " invocation-name " RET m bugs RET
|
|
10310
|
|
10311 Before I go further, I want to say that Verilog mode has changed my life.
|
|
10312 I save so much time, my files are colored nicely, my co workers respect
|
|
10313 my coding ability... until now. I'd really appreciate anything you
|
|
10314 could do to help me out with this minor deficiency in the product.
|
|
10315
|
|
10316 If you have bugs with the AUTO functions, please CC the AUTOAUTHOR Wilson
|
|
10317 Snyder (wsnyder@wsnyder.org) and/or see http://www.veripool.com.
|
|
10318 You may also want to look at the Verilog-Mode FAQ, see
|
|
10319 http://www.veripool.com/verilog-mode-faq.html.
|
|
10320
|
|
10321 To reproduce the bug, start a fresh Emacs via " invocation-name "
|
|
10322 -no-init-file -no-site-file'. In a new buffer, in verilog mode, type
|
|
10323 the code included below.
|
|
10324
|
|
10325 Given those lines, I expected [[Fill in here]] to happen;
|
|
10326 but instead, [[Fill in here]] happens!.
|
|
10327
|
|
10328 == The code: =="))))
|
|
10329
|
|
10330 ;; Local Variables:
|
|
10331 ;; checkdoc-permit-comma-termination-flag:t
|
|
10332 ;; checkdoc-force-docstrings-flag:nil
|
|
10333 ;; End:
|
|
10334
|
|
10335 ;;; verilog-mode.el ends here
|