comparison lisp/progmodes/vhdl-mode.el @ 65491:411b230f06b5

(conf-alist, conf-entry, conf-key, ent-alist): Add defvar.

65490:e3c81c2db803

  "Non-nil if GNU Emacs 21, 22, ... is used.")
(defconst vhdl-emacs-22 (and (<= 22 emacs-major-version) (not vhdl-xemacs))
  "Non-nil if GNU Emacs 22, ... is used.")

(defvar compilation-file-regexp-alist)
(defvar itimer-version)
(defvar lazy-lock-defer-contextually)
(defvar lazy-lock-defer-on-scrolling)
(defvar lazy-lock-defer-on-the-fly)


;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;; Variables
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

  To string        : string a name is mapped to (\"\\1\" inserts the unit name,
                     \"\\2\" inserts the entity name for architectures)
  Case adjustment  : adjust case of inserted unit names

\(*) The regular expression must match the error message starting from the
    beginning of the line (but not necessarily to the end of the line). 

Compile options allows insertion of the library name (see `vhdl-project-alist')
in order to set the compilers library option (e.g. \"vcom -work my_lib\").

For Makefile generation, the built-in function can be used (requires

begin  -- process <label>
  if <reset> = '0' then  -- asynchronous reset (active low)
    <cursor>
  elsif <clock>'event and <clock> = '1' then  -- rising clock edge
    if <enable> = '1' then  -- synchronous load
      
    end if;
  end if;
end process <label>;"
     "e" ""))
  "*List of user models.

  -- waveform generation
  WaveGen_Proc: process
  begin
    -- insert signal assignments here
    
    wait until Clk = '1';
  end process WaveGen_Proc;
"
  "*String or file to be inserted in the testbench statement part.
If the string specifies an existing file name, the contents of the file is

        inputs to this component -> input port created
      - signals that are only outputs from subcomponents are considered as
        outputs from this component -> output port created
      - signals that are inputs to AND outputs from subcomponents are
        considered as internal connections -> internal signal created
 
      Purpose:  With appropriate naming conventions it is possible to
    create higher design levels with only a few mouse clicks or key
    strokes.  A new design level can be created by simply generating a new
    component, placing the required subcomponents from the hierarchy
    browser, and wiring everything automatically.
 
      Note: Automatic wiring only works reliably on templates of new
    components and component instantiations that were created by VHDL mode.
 
      Component declarations can be placed in a components package (option
    `vhdl-use-components-package') which can be automatically generated for
    an entire directory or project (`C-c C-c M-p').  The VHDL'93 direct
    component instantiation is also supported (option
    `vhdl-use-direct-instantiation').

|   generating the configuration.
|
|     Note: Configurations of subcomponents (i.e. hierarchical configuration
|   declarations) are currently not considered when displaying
|   configurations in speedbar.
 
      See the options group `vhdl-compose' for all relevant user options.


  SOURCE FILE COMPILATION:
    The syntax of the current buffer can be analyzed by calling a VHDL

  :group 'speedbar-faces)

(defface vhdl-speedbar-architecture-face
  '((((min-colors 88) (class color) (background light)) (:foreground "Blue1"))
    (((class color) (background light)) (:foreground "Blue"))
    
    (((class color) (background dark)) (:foreground "LightSkyBlue")))
  "Face used for displaying architecture names."
  :group 'speedbar-faces)

(defface vhdl-speedbar-configuration-face

65491:411b230f06b5

  "Non-nil if GNU Emacs 21, 22, ... is used.")
(defconst vhdl-emacs-22 (and (<= 22 emacs-major-version) (not vhdl-xemacs))
  "Non-nil if GNU Emacs 22, ... is used.")

(defvar compilation-file-regexp-alist)
(defvar conf-alist)
(defvar conf-entry)
(defvar conf-key)
(defvar ent-alist)
(defvar itimer-version)
(defvar lazy-lock-defer-contextually)
(defvar lazy-lock-defer-on-scrolling)
(defvar lazy-lock-defer-on-the-fly)

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;; Variables
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

  To string        : string a name is mapped to (\"\\1\" inserts the unit name,
                     \"\\2\" inserts the entity name for architectures)
  Case adjustment  : adjust case of inserted unit names

\(*) The regular expression must match the error message starting from the
    beginning of the line (but not necessarily to the end of the line).

Compile options allows insertion of the library name (see `vhdl-project-alist')
in order to set the compilers library option (e.g. \"vcom -work my_lib\").

For Makefile generation, the built-in function can be used (requires

begin  -- process <label>
  if <reset> = '0' then  -- asynchronous reset (active low)
    <cursor>
  elsif <clock>'event and <clock> = '1' then  -- rising clock edge
    if <enable> = '1' then  -- synchronous load

    end if;
  end if;
end process <label>;"
     "e" ""))
  "*List of user models.

  -- waveform generation
  WaveGen_Proc: process
  begin
    -- insert signal assignments here

    wait until Clk = '1';
  end process WaveGen_Proc;
"
  "*String or file to be inserted in the testbench statement part.
If the string specifies an existing file name, the contents of the file is

        inputs to this component -> input port created
      - signals that are only outputs from subcomponents are considered as
        outputs from this component -> output port created
      - signals that are inputs to AND outputs from subcomponents are
        considered as internal connections -> internal signal created

      Purpose:  With appropriate naming conventions it is possible to
    create higher design levels with only a few mouse clicks or key
    strokes.  A new design level can be created by simply generating a new
    component, placing the required subcomponents from the hierarchy
    browser, and wiring everything automatically.

      Note: Automatic wiring only works reliably on templates of new
    components and component instantiations that were created by VHDL mode.

      Component declarations can be placed in a components package (option
    `vhdl-use-components-package') which can be automatically generated for
    an entire directory or project (`C-c C-c M-p').  The VHDL'93 direct
    component instantiation is also supported (option
    `vhdl-use-direct-instantiation').

|   generating the configuration.
|
|     Note: Configurations of subcomponents (i.e. hierarchical configuration
|   declarations) are currently not considered when displaying
|   configurations in speedbar.

      See the options group `vhdl-compose' for all relevant user options.


  SOURCE FILE COMPILATION:
    The syntax of the current buffer can be analyzed by calling a VHDL

  :group 'speedbar-faces)

(defface vhdl-speedbar-architecture-face
  '((((min-colors 88) (class color) (background light)) (:foreground "Blue1"))
    (((class color) (background light)) (:foreground "Blue"))

    (((class color) (background dark)) (:foreground "LightSkyBlue")))
  "Face used for displaying architecture names."
  :group 'speedbar-faces)

(defface vhdl-speedbar-configuration-face