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*** empty log message ***
author Dave Love <fx@gnu.org>
date Thu, 05 Jun 2003 17:49:22 +0000
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51487:01d68b199093 51488:5de98dce4bd1
1 /*
2 * Copyright 1988, 1989 Hans-J. Boehm, Alan J. Demers
3 * Copyright (c) 1991-1994 by Xerox Corporation. All rights reserved.
4 * Copyright (c) 1996-1999 by Silicon Graphics. All rights reserved.
5 * Copyright (c) 1999 by Hewlett-Packard Company. All rights reserved.
6 *
7 *
8 * THIS MATERIAL IS PROVIDED AS IS, WITH ABSOLUTELY NO WARRANTY EXPRESSED
9 * OR IMPLIED. ANY USE IS AT YOUR OWN RISK.
10 *
11 * Permission is hereby granted to use or copy this program
12 * for any purpose, provided the above notices are retained on all copies.
13 * Permission to modify the code and to distribute modified code is granted,
14 * provided the above notices are retained, and a notice that the code was
15 * modified is included with the above copyright notice.
16 */
17
18 #ifndef GC_LOCKS_H
19 #define GC_LOCKS_H
20
21 /*
22 * Mutual exclusion between allocator/collector routines.
23 * Needed if there is more than one allocator thread.
24 * FASTLOCK() is assumed to try to acquire the lock in a cheap and
25 * dirty way that is acceptable for a few instructions, e.g. by
26 * inhibiting preemption. This is assumed to have succeeded only
27 * if a subsequent call to FASTLOCK_SUCCEEDED() returns TRUE.
28 * FASTUNLOCK() is called whether or not FASTLOCK_SUCCEEDED().
29 * If signals cannot be tolerated with the FASTLOCK held, then
30 * FASTLOCK should disable signals. The code executed under
31 * FASTLOCK is otherwise immune to interruption, provided it is
32 * not restarted.
33 * DCL_LOCK_STATE declares any local variables needed by LOCK and UNLOCK
34 * and/or DISABLE_SIGNALS and ENABLE_SIGNALS and/or FASTLOCK.
35 * (There is currently no equivalent for FASTLOCK.)
36 *
37 * In the PARALLEL_MARK case, we also need to define a number of
38 * other inline finctions here:
39 * GC_bool GC_compare_and_exchange( volatile GC_word *addr,
40 * GC_word old, GC_word new )
41 * GC_word GC_atomic_add( volatile GC_word *addr, GC_word how_much )
42 * void GC_memory_barrier( )
43 *
44 */
45 # ifdef THREADS
46 void GC_noop1 GC_PROTO((word));
47 # ifdef PCR_OBSOLETE /* Faster, but broken with multiple lwp's */
48 # include "th/PCR_Th.h"
49 # include "th/PCR_ThCrSec.h"
50 extern struct PCR_Th_MLRep GC_allocate_ml;
51 # define DCL_LOCK_STATE PCR_sigset_t GC_old_sig_mask
52 # define LOCK() PCR_Th_ML_Acquire(&GC_allocate_ml)
53 # define UNLOCK() PCR_Th_ML_Release(&GC_allocate_ml)
54 # define UNLOCK() PCR_Th_ML_Release(&GC_allocate_ml)
55 # define FASTLOCK() PCR_ThCrSec_EnterSys()
56 /* Here we cheat (a lot): */
57 # define FASTLOCK_SUCCEEDED() (*(int *)(&GC_allocate_ml) == 0)
58 /* TRUE if nobody currently holds the lock */
59 # define FASTUNLOCK() PCR_ThCrSec_ExitSys()
60 # endif
61 # ifdef PCR
62 # include <base/PCR_Base.h>
63 # include <th/PCR_Th.h>
64 extern PCR_Th_ML GC_allocate_ml;
65 # define DCL_LOCK_STATE \
66 PCR_ERes GC_fastLockRes; PCR_sigset_t GC_old_sig_mask
67 # define LOCK() PCR_Th_ML_Acquire(&GC_allocate_ml)
68 # define UNLOCK() PCR_Th_ML_Release(&GC_allocate_ml)
69 # define FASTLOCK() (GC_fastLockRes = PCR_Th_ML_Try(&GC_allocate_ml))
70 # define FASTLOCK_SUCCEEDED() (GC_fastLockRes == PCR_ERes_okay)
71 # define FASTUNLOCK() {\
72 if( FASTLOCK_SUCCEEDED() ) PCR_Th_ML_Release(&GC_allocate_ml); }
73 # endif
74 # ifdef SRC_M3
75 extern GC_word RT0u__inCritical;
76 # define LOCK() RT0u__inCritical++
77 # define UNLOCK() RT0u__inCritical--
78 # endif
79 # ifdef GC_SOLARIS_THREADS
80 # include <thread.h>
81 # include <signal.h>
82 extern mutex_t GC_allocate_ml;
83 # define LOCK() mutex_lock(&GC_allocate_ml);
84 # define UNLOCK() mutex_unlock(&GC_allocate_ml);
85 # endif
86
87 /* Try to define GC_TEST_AND_SET and a matching GC_CLEAR for spin lock */
88 /* acquisition and release. We need this for correct operation of the */
89 /* incremental GC. */
90 # ifdef __GNUC__
91 # if defined(I386)
92 inline static int GC_test_and_set(volatile unsigned int *addr) {
93 int oldval;
94 /* Note: the "xchg" instruction does not need a "lock" prefix */
95 __asm__ __volatile__("xchgl %0, %1"
96 : "=r"(oldval), "=m"(*(addr))
97 : "0"(1), "m"(*(addr)) : "memory");
98 return oldval;
99 }
100 # define GC_TEST_AND_SET_DEFINED
101 # endif
102 # if defined(IA64)
103 inline static int GC_test_and_set(volatile unsigned int *addr) {
104 long oldval, n = 1;
105 __asm__ __volatile__("xchg4 %0=%1,%2"
106 : "=r"(oldval), "=m"(*addr)
107 : "r"(n), "1"(*addr) : "memory");
108 return oldval;
109 }
110 # define GC_TEST_AND_SET_DEFINED
111 /* Should this handle post-increment addressing?? */
112 inline static void GC_clear(volatile unsigned int *addr) {
113 __asm__ __volatile__("st4.rel %0=r0" : "=m" (*addr) : : "memory");
114 }
115 # define GC_CLEAR_DEFINED
116 # endif
117 # ifdef SPARC
118 inline static int GC_test_and_set(volatile unsigned int *addr) {
119 int oldval;
120
121 __asm__ __volatile__("ldstub %1,%0"
122 : "=r"(oldval), "=m"(*addr)
123 : "m"(*addr) : "memory");
124 return oldval;
125 }
126 # define GC_TEST_AND_SET_DEFINED
127 # endif
128 # ifdef M68K
129 /* Contributed by Tony Mantler. I'm not sure how well it was */
130 /* tested. */
131 inline static int GC_test_and_set(volatile unsigned int *addr) {
132 char oldval; /* this must be no longer than 8 bits */
133
134 /* The return value is semi-phony. */
135 /* 'tas' sets bit 7 while the return */
136 /* value pretends bit 0 was set */
137 __asm__ __volatile__(
138 "tas %1@; sne %0; negb %0"
139 : "=d" (oldval)
140 : "a" (addr) : "memory");
141 return oldval;
142 }
143 # define GC_TEST_AND_SET_DEFINED
144 # endif
145 # if defined(POWERPC)
146 inline static int GC_test_and_set(volatile unsigned int *addr) {
147 int oldval;
148 int temp = 1; /* locked value */
149
150 __asm__ __volatile__(
151 "1:\tlwarx %0,0,%3\n" /* load and reserve */
152 "\tcmpwi %0, 0\n" /* if load is */
153 "\tbne 2f\n" /* non-zero, return already set */
154 "\tstwcx. %2,0,%1\n" /* else store conditional */
155 "\tbne- 1b\n" /* retry if lost reservation */
156 "2:\t\n" /* oldval is zero if we set */
157 : "=&r"(oldval), "=p"(addr)
158 : "r"(temp), "1"(addr)
159 : "memory");
160 return oldval;
161 }
162 # define GC_TEST_AND_SET_DEFINED
163 inline static void GC_clear(volatile unsigned int *addr) {
164 __asm__ __volatile__("eieio" : : : "memory");
165 *(addr) = 0;
166 }
167 # define GC_CLEAR_DEFINED
168 # endif
169 # if defined(ALPHA)
170 inline static int GC_test_and_set(volatile unsigned int * addr)
171 {
172 unsigned long oldvalue;
173 unsigned long temp;
174
175 __asm__ __volatile__(
176 "1: ldl_l %0,%1\n"
177 " and %0,%3,%2\n"
178 " bne %2,2f\n"
179 " xor %0,%3,%0\n"
180 " stl_c %0,%1\n"
181 " beq %0,3f\n"
182 " mb\n"
183 "2:\n"
184 ".section .text2,\"ax\"\n"
185 "3: br 1b\n"
186 ".previous"
187 :"=&r" (temp), "=m" (*addr), "=&r" (oldvalue)
188 :"Ir" (1), "m" (*addr)
189 :"memory");
190
191 return oldvalue;
192 }
193 # define GC_TEST_AND_SET_DEFINED
194 inline static void GC_clear(volatile unsigned int *addr) {
195 __asm__ __volatile__("mb" : : : "memory");
196 *(addr) = 0;
197 }
198 # define GC_CLEAR_DEFINED
199 # endif /* ALPHA */
200 # ifdef ARM32
201 inline static int GC_test_and_set(volatile unsigned int *addr) {
202 int oldval;
203 /* SWP on ARM is very similar to XCHG on x86. Doesn't lock the
204 * bus because there are no SMP ARM machines. If/when there are,
205 * this code will likely need to be updated. */
206 /* See linuxthreads/sysdeps/arm/pt-machine.h in glibc-2.1 */
207 __asm__ __volatile__("swp %0, %1, [%2]"
208 : "=r"(oldval)
209 : "r"(1), "r"(addr)
210 : "memory");
211 return oldval;
212 }
213 # define GC_TEST_AND_SET_DEFINED
214 # endif /* ARM32 */
215 # ifdef S390
216 inline static int GC_test_and_set(volatile unsigned int *addr) {
217 int ret;
218 __asm__ __volatile__ (
219 " l %0,0(%2)\n"
220 "0: cs %0,%1,0(%2)\n"
221 " jl 0b"
222 : "=&d" (ret)
223 : "d" (1), "a" (addr)
224 : "cc", "memory");
225 return ret;
226 }
227 # endif
228 # endif /* __GNUC__ */
229 # if (defined(ALPHA) && !defined(__GNUC__))
230 # ifndef OSF1
231 --> We currently assume that if gcc is not used, we are
232 --> running under Tru64.
233 # endif
234 # include <machine/builtins.h>
235 # include <c_asm.h>
236 # define GC_test_and_set(addr) __ATOMIC_EXCH_LONG(addr, 1)
237 # define GC_TEST_AND_SET_DEFINED
238 # define GC_clear(addr) { asm("mb"); *(volatile unsigned *)addr = 0; }
239 # define GC_CLEAR_DEFINED
240 # endif
241 # if defined(MSWIN32)
242 # define GC_test_and_set(addr) InterlockedExchange((LPLONG)addr,1)
243 # define GC_TEST_AND_SET_DEFINED
244 # endif
245 # ifdef MIPS
246 # ifdef LINUX
247 # include <sys/tas.h>
248 # define GC_test_and_set(addr) _test_and_set((int *) addr,1)
249 # define GC_TEST_AND_SET_DEFINED
250 # elif __mips < 3 || !(defined (_ABIN32) || defined(_ABI64)) \
251 || !defined(_COMPILER_VERSION) || _COMPILER_VERSION < 700
252 # ifdef __GNUC__
253 # define GC_test_and_set(addr) _test_and_set(addr,1)
254 # else
255 # define GC_test_and_set(addr) test_and_set(addr,1)
256 # endif
257 # else
258 # define GC_test_and_set(addr) __test_and_set(addr,1)
259 # define GC_clear(addr) __lock_release(addr);
260 # define GC_CLEAR_DEFINED
261 # endif
262 # define GC_TEST_AND_SET_DEFINED
263 # endif /* MIPS */
264 # if 0 /* defined(HP_PA) */
265 /* The official recommendation seems to be to not use ldcw from */
266 /* user mode. Since multithreaded incremental collection doesn't */
267 /* work anyway on HP_PA, this shouldn't be a major loss. */
268
269 /* "set" means 0 and "clear" means 1 here. */
270 # define GC_test_and_set(addr) !GC_test_and_clear(addr);
271 # define GC_TEST_AND_SET_DEFINED
272 # define GC_clear(addr) GC_noop1((word)(addr)); *(volatile unsigned int *)addr = 1;
273 /* The above needs a memory barrier! */
274 # define GC_CLEAR_DEFINED
275 # endif
276 # if defined(GC_TEST_AND_SET_DEFINED) && !defined(GC_CLEAR_DEFINED)
277 # ifdef __GNUC__
278 inline static void GC_clear(volatile unsigned int *addr) {
279 /* Try to discourage gcc from moving anything past this. */
280 __asm__ __volatile__(" " : : : "memory");
281 *(addr) = 0;
282 }
283 # else
284 /* The function call in the following should prevent the */
285 /* compiler from moving assignments to below the UNLOCK. */
286 # define GC_clear(addr) GC_noop1((word)(addr)); \
287 *((volatile unsigned int *)(addr)) = 0;
288 # endif
289 # define GC_CLEAR_DEFINED
290 # endif /* !GC_CLEAR_DEFINED */
291
292 # if !defined(GC_TEST_AND_SET_DEFINED)
293 # define USE_PTHREAD_LOCKS
294 # endif
295
296 # if defined(GC_PTHREADS) && !defined(GC_SOLARIS_THREADS) \
297 && !defined(GC_IRIX_THREADS) && !defined(GC_WIN32_THREADS)
298 # define NO_THREAD (pthread_t)(-1)
299 # include <pthread.h>
300 # if defined(PARALLEL_MARK)
301 /* We need compare-and-swap to update mark bits, where it's */
302 /* performance critical. If USE_MARK_BYTES is defined, it is */
303 /* no longer needed for this purpose. However we use it in */
304 /* either case to implement atomic fetch-and-add, though that's */
305 /* less performance critical, and could perhaps be done with */
306 /* a lock. */
307 # if defined(GENERIC_COMPARE_AND_SWAP)
308 /* Probably not useful, except for debugging. */
309 /* We do use GENERIC_COMPARE_AND_SWAP on PA_RISC, but we */
310 /* minimize its use. */
311 extern pthread_mutex_t GC_compare_and_swap_lock;
312
313 /* Note that if GC_word updates are not atomic, a concurrent */
314 /* reader should acquire GC_compare_and_swap_lock. On */
315 /* currently supported platforms, such updates are atomic. */
316 extern GC_bool GC_compare_and_exchange(volatile GC_word *addr,
317 GC_word old, GC_word new_val);
318 # endif /* GENERIC_COMPARE_AND_SWAP */
319 # if defined(I386)
320 # if !defined(GENERIC_COMPARE_AND_SWAP)
321 /* Returns TRUE if the comparison succeeded. */
322 inline static GC_bool GC_compare_and_exchange(volatile GC_word *addr,
323 GC_word old,
324 GC_word new_val)
325 {
326 char result;
327 __asm__ __volatile__("lock; cmpxchgl %2, %0; setz %1"
328 : "=m"(*(addr)), "=r"(result)
329 : "r" (new_val), "0"(*(addr)), "a"(old) : "memory");
330 return (GC_bool) result;
331 }
332 # endif /* !GENERIC_COMPARE_AND_SWAP */
333 inline static void GC_memory_barrier()
334 {
335 /* We believe the processor ensures at least processor */
336 /* consistent ordering. Thus a compiler barrier */
337 /* should suffice. */
338 __asm__ __volatile__("" : : : "memory");
339 }
340 # endif /* I386 */
341 # if defined(IA64)
342 # if !defined(GENERIC_COMPARE_AND_SWAP)
343 inline static GC_bool GC_compare_and_exchange(volatile GC_word *addr,
344 GC_word old, GC_word new_val)
345 {
346 unsigned long oldval;
347 __asm__ __volatile__("mov ar.ccv=%4 ;; cmpxchg8.rel %0=%1,%2,ar.ccv"
348 : "=r"(oldval), "=m"(*addr)
349 : "r"(new_val), "1"(*addr), "r"(old) : "memory");
350 return (oldval == old);
351 }
352 # endif /* !GENERIC_COMPARE_AND_SWAP */
353 # if 0
354 /* Shouldn't be needed; we use volatile stores instead. */
355 inline static void GC_memory_barrier()
356 {
357 __asm__ __volatile__("mf" : : : "memory");
358 }
359 # endif /* 0 */
360 # endif /* IA64 */
361 # if defined(ALPHA)
362 # if !defined(GENERIC_COMPARE_AND_SWAP)
363 # if defined(__GNUC__)
364 inline static GC_bool GC_compare_and_exchange(volatile GC_word *addr,
365 GC_word old, GC_word new_val)
366 {
367 unsigned long was_equal;
368 unsigned long temp;
369
370 __asm__ __volatile__(
371 "1: ldq_l %0,%1\n"
372 " cmpeq %0,%4,%2\n"
373 " mov %3,%0\n"
374 " beq %2,2f\n"
375 " stq_c %0,%1\n"
376 " beq %0,1b\n"
377 "2:\n"
378 " mb\n"
379 :"=&r" (temp), "=m" (*addr), "=&r" (was_equal)
380 : "r" (new_val), "Ir" (old)
381 :"memory");
382 return was_equal;
383 }
384 # else /* !__GNUC__ */
385 inline static GC_bool GC_compare_and_exchange(volatile GC_word *addr,
386 GC_word old, GC_word new_val)
387 {
388 return __CMP_STORE_QUAD(addr, old, new_val, addr);
389 }
390 # endif /* !__GNUC__ */
391 # endif /* !GENERIC_COMPARE_AND_SWAP */
392 # ifdef __GNUC__
393 inline static void GC_memory_barrier()
394 {
395 __asm__ __volatile__("mb" : : : "memory");
396 }
397 # else
398 # define GC_memory_barrier() asm("mb")
399 # endif /* !__GNUC__ */
400 # endif /* ALPHA */
401 # if defined(S390)
402 # if !defined(GENERIC_COMPARE_AND_SWAP)
403 inline static GC_bool GC_compare_and_exchange(volatile C_word *addr,
404 GC_word old, GC_word new_val)
405 {
406 int retval;
407 __asm__ __volatile__ (
408 # ifndef __s390x__
409 " cs %1,%2,0(%3)\n"
410 # else
411 " csg %1,%2,0(%3)\n"
412 # endif
413 " ipm %0\n"
414 " srl %0,28\n"
415 : "=&d" (retval), "+d" (old)
416 : "d" (new_val), "a" (addr)
417 : "cc", "memory");
418 return retval == 0;
419 }
420 # endif
421 # endif
422 # if !defined(GENERIC_COMPARE_AND_SWAP)
423 /* Returns the original value of *addr. */
424 inline static GC_word GC_atomic_add(volatile GC_word *addr,
425 GC_word how_much)
426 {
427 GC_word old;
428 do {
429 old = *addr;
430 } while (!GC_compare_and_exchange(addr, old, old+how_much));
431 return old;
432 }
433 # else /* GENERIC_COMPARE_AND_SWAP */
434 /* So long as a GC_word can be atomically updated, it should */
435 /* be OK to read *addr without a lock. */
436 extern GC_word GC_atomic_add(volatile GC_word *addr, GC_word how_much);
437 # endif /* GENERIC_COMPARE_AND_SWAP */
438
439 # endif /* PARALLEL_MARK */
440
441 # if !defined(THREAD_LOCAL_ALLOC) && !defined(USE_PTHREAD_LOCKS)
442 /* In the THREAD_LOCAL_ALLOC case, the allocation lock tends to */
443 /* be held for long periods, if it is held at all. Thus spinning */
444 /* and sleeping for fixed periods are likely to result in */
445 /* significant wasted time. We thus rely mostly on queued locks. */
446 # define USE_SPIN_LOCK
447 extern volatile unsigned int GC_allocate_lock;
448 extern void GC_lock(void);
449 /* Allocation lock holder. Only set if acquired by client through */
450 /* GC_call_with_alloc_lock. */
451 # ifdef GC_ASSERTIONS
452 # define LOCK() \
453 { if (GC_test_and_set(&GC_allocate_lock)) GC_lock(); \
454 SET_LOCK_HOLDER(); }
455 # define UNLOCK() \
456 { GC_ASSERT(I_HOLD_LOCK()); UNSET_LOCK_HOLDER(); \
457 GC_clear(&GC_allocate_lock); }
458 # else
459 # define LOCK() \
460 { if (GC_test_and_set(&GC_allocate_lock)) GC_lock(); }
461 # define UNLOCK() \
462 GC_clear(&GC_allocate_lock)
463 # endif /* !GC_ASSERTIONS */
464 # if 0
465 /* Another alternative for OSF1 might be: */
466 # include <sys/mman.h>
467 extern msemaphore GC_allocate_semaphore;
468 # define LOCK() { if (msem_lock(&GC_allocate_semaphore, MSEM_IF_NOWAIT) \
469 != 0) GC_lock(); else GC_allocate_lock = 1; }
470 /* The following is INCORRECT, since the memory model is too weak. */
471 /* Is this true? Presumably msem_unlock has the right semantics? */
472 /* - HB */
473 # define UNLOCK() { GC_allocate_lock = 0; \
474 msem_unlock(&GC_allocate_semaphore, 0); }
475 # endif /* 0 */
476 # else /* THREAD_LOCAL_ALLOC || USE_PTHREAD_LOCKS */
477 # ifndef USE_PTHREAD_LOCKS
478 # define USE_PTHREAD_LOCKS
479 # endif
480 # endif /* THREAD_LOCAL_ALLOC */
481 # ifdef USE_PTHREAD_LOCKS
482 # include <pthread.h>
483 extern pthread_mutex_t GC_allocate_ml;
484 # ifdef GC_ASSERTIONS
485 # define LOCK() \
486 { GC_lock(); \
487 SET_LOCK_HOLDER(); }
488 # define UNLOCK() \
489 { GC_ASSERT(I_HOLD_LOCK()); UNSET_LOCK_HOLDER(); \
490 pthread_mutex_unlock(&GC_allocate_ml); }
491 # else /* !GC_ASSERTIONS */
492 # define LOCK() \
493 { if (0 != pthread_mutex_trylock(&GC_allocate_ml)) GC_lock(); }
494 # define UNLOCK() pthread_mutex_unlock(&GC_allocate_ml)
495 # endif /* !GC_ASSERTIONS */
496 # endif /* USE_PTHREAD_LOCKS */
497 # define SET_LOCK_HOLDER() GC_lock_holder = pthread_self()
498 # define UNSET_LOCK_HOLDER() GC_lock_holder = NO_THREAD
499 # define I_HOLD_LOCK() (pthread_equal(GC_lock_holder, pthread_self()))
500 extern VOLATILE GC_bool GC_collecting;
501 # define ENTER_GC() GC_collecting = 1;
502 # define EXIT_GC() GC_collecting = 0;
503 extern void GC_lock(void);
504 extern pthread_t GC_lock_holder;
505 # ifdef GC_ASSERTIONS
506 extern pthread_t GC_mark_lock_holder;
507 # endif
508 # endif /* GC_PTHREADS with linux_threads.c implementation */
509 # if defined(GC_IRIX_THREADS)
510 # include <pthread.h>
511 /* This probably should never be included, but I can't test */
512 /* on Irix anymore. */
513 # include <mutex.h>
514
515 extern unsigned long GC_allocate_lock;
516 /* This is not a mutex because mutexes that obey the (optional) */
517 /* POSIX scheduling rules are subject to convoys in high contention */
518 /* applications. This is basically a spin lock. */
519 extern pthread_t GC_lock_holder;
520 extern void GC_lock(void);
521 /* Allocation lock holder. Only set if acquired by client through */
522 /* GC_call_with_alloc_lock. */
523 # define SET_LOCK_HOLDER() GC_lock_holder = pthread_self()
524 # define NO_THREAD (pthread_t)(-1)
525 # define UNSET_LOCK_HOLDER() GC_lock_holder = NO_THREAD
526 # define I_HOLD_LOCK() (pthread_equal(GC_lock_holder, pthread_self()))
527 # define LOCK() { if (GC_test_and_set(&GC_allocate_lock)) GC_lock(); }
528 # define UNLOCK() GC_clear(&GC_allocate_lock);
529 extern VOLATILE GC_bool GC_collecting;
530 # define ENTER_GC() \
531 { \
532 GC_collecting = 1; \
533 }
534 # define EXIT_GC() GC_collecting = 0;
535 # endif /* GC_IRIX_THREADS */
536 # if defined(GC_WIN32_THREADS)
537 # if defined(GC_PTHREADS)
538 # include <pthread.h>
539 extern pthread_mutex_t GC_allocate_ml;
540 # define LOCK() pthread_mutex_lock(&GC_allocate_ml)
541 # define UNLOCK() pthread_mutex_unlock(&GC_allocate_ml)
542 # else
543 # include <windows.h>
544 GC_API CRITICAL_SECTION GC_allocate_ml;
545 # define LOCK() EnterCriticalSection(&GC_allocate_ml);
546 # define UNLOCK() LeaveCriticalSection(&GC_allocate_ml);
547 # endif
548 # endif
549 # ifndef SET_LOCK_HOLDER
550 # define SET_LOCK_HOLDER()
551 # define UNSET_LOCK_HOLDER()
552 # define I_HOLD_LOCK() FALSE
553 /* Used on platforms were locks can be reacquired, */
554 /* so it doesn't matter if we lie. */
555 # endif
556 # else /* !THREADS */
557 # define LOCK()
558 # define UNLOCK()
559 # endif /* !THREADS */
560 # ifndef SET_LOCK_HOLDER
561 # define SET_LOCK_HOLDER()
562 # define UNSET_LOCK_HOLDER()
563 # define I_HOLD_LOCK() FALSE
564 /* Used on platforms were locks can be reacquired, */
565 /* so it doesn't matter if we lie. */
566 # endif
567 # ifndef ENTER_GC
568 # define ENTER_GC()
569 # define EXIT_GC()
570 # endif
571
572 # ifndef DCL_LOCK_STATE
573 # define DCL_LOCK_STATE
574 # endif
575 # ifndef FASTLOCK
576 # define FASTLOCK() LOCK()
577 # define FASTLOCK_SUCCEEDED() TRUE
578 # define FASTUNLOCK() UNLOCK()
579 # endif
580
581 #endif /* GC_LOCKS_H */