comparison lisp/progmodes/verilog-mode.el @ 80171:97019d686b43

* progmodes/verilog-mode.el (verilog-xemacs-menu): Remove XEmacs conditional. (verilog-font-grouping-keywords-face): Make the begin..end keywords standout more than other verilog keywords. (verilog-type-font-keywords): Move the begin..end out of this list to facilitate making them to (potentially) stand out more. (verilog-backward-token): Fix indent of bare always{_*}?, initial, function & task blocks. (verilog-behavioral-block-beg-re): Fix indent of bare always{_*}?, initial, function & task blocks. (verilog-forward-sexp): Handle the new "disable fork" statement of IEEE-1800 Verilog. (verilog-beg-block-re-ordered): Handle the new "disable fork" statement of IEEE-1800 Verilog. (verilog-calc-1): Handle the new "disable fork" statement of IEEE-1800 Verilog. (verilog-disable-fork-re): Add const to help handle the new "disable fork" statement of IEEE-1800 Verilog. (verilog-declaration-core-re): Add port directions by themselves, with no qualification, as base item of a declaration. (verilog-pretty-declarations): Add new flag to ask it to refrain from printing to the message buffer. (verilog-pretty-expr): Add a QUIET flag to ask it to refrain from printing to the message buffer. Improve handling of the many types of expression line up. (verilog-just-one-space): Remove printing of an empty message. (verilog-get-lineup-indent): Rework to support the better handling of expression lineup for verilog-pretty-expr. (verilog-auto-wire): Pass the quiet flag to verilog-pretty-expr.

80170:3e4f6980296d

;; (This section is required to appease checkdoc.)

;;; Code:

;; This variable will always hold the version number of the mode
(defconst verilog-mode-version "389"
  "Version of this Verilog mode.")
(defconst verilog-mode-release-date "2008-02-01-GNU"
  "Release date of this Verilog mode.")
(defconst verilog-mode-release-emacs t
  "If non-nil, this version of Verilog mode was released with Emacs itself.")

(defun verilog-version ()

	(verilog-set-compile-command))
      :style radio
      :selected (equal verilog-tool `verilog-compiler)]
     )
    ("Move"
     ,(if (featurep 'xemacs)
	  (progn
	    ["Beginning of function"		verilog-beg-of-defun t]
	    ["End of function"			verilog-end-of-defun t]
	    ["Mark function"			verilog-mark-defun t])
	["Beginning of function"		beginning-of-defun t]
	["End of function"			end-of-defun t]
	["Mark function"			mark-defun t])

     ["Goto function/module"		verilog-goto-defun t]
     ["Move to beginning of block"	electric-verilog-backward-sexp t]
     ["Move to end of block"		electric-verilog-forward-sexp t]
     )
    ("Comments"

;; verilog-forward-sexp and verilog-calc-indent

(defconst verilog-beg-block-re-ordered
  ( concat "\\<"
	   "\\(begin\\)"		;1
	   "\\|\\(randcase\\|\\(unique\\s-+\\|priority\\s-+\\)?case[xz]?\\)" ; 2
;;	   "\\|\\(randcase\\|case[xz]?\\)" ; 2
	   "\\|\\(fork\\)"		;3
	   "\\|\\(class\\)"		;4
	   "\\|\\(table\\)"		;5
	   "\\|\\(specify\\)"		;6
	   "\\|\\(function\\)"		;7
	   "\\|\\(task\\)"		;8
	   "\\|\\(generate\\)"		;9
	   "\\|\\(covergroup\\)"	;10
	   "\\|\\(property\\)"		;11
	   "\\|\\(\\(rand\\)?sequence\\)"  ;12
	   "\\|\\(clocking\\)"          ;13
	   "\\>"))

(defconst verilog-end-block-ordered-rry
  [ "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)\\|\\(\\<endcase\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)"
    "\\(\\<randcase\\>\\|\\<case[xz]?\\>\\)\\|\\(\\<endcase\\>\\)"

  (eval-when-compile (verilog-regexp-words `("endmodule" "endclass" "endprogram" "endinterface" "endpackage" "endprimitive" "endconfig"))))
(defconst verilog-zero-indent-re
  (concat verilog-defun-re "\\|" verilog-end-defun-re))

(defconst verilog-behavioral-block-beg-re
  (concat "\\(\\<initial\\>\\|\\<final\\>\\|\\<always\\>\\|\\<always_comb\\>\\|\\<always_ff\\>\\|"
	  "\\<always_latch\\>\\|\\<function\\>\\|\\<task\\>\\)"))

(defconst verilog-indent-re
  (eval-when-compile
    (verilog-regexp-words
     `(

  (eval-when-compile
    (verilog-regexp-words
     `(
       "endmodule" "endprimitive" "endinterface" "endpackage" "endprogram" "endclass"
       ))))
(defconst verilog-extended-case-re "\\(unique\\s-+\\|priority\\s-+\\)?case[xz]?")
(defconst verilog-extended-complete-re
  (concat "\\(\\<extern\\s-+\\|\\<virtual\\s-+\\|\\<protected\\s-+\\)*\\(\\<function\\>\\|\\<task\\>\\)"
	  "\\|\\(\\<typedef\\>\\s-+\\)*\\(\\<struct\\>\\|\\<union\\>\\|\\<class\\>\\)"
	  "\\|" verilog-extended-case-re ))

     (:foreground "orange1" :bold t ))
    (t (:italic t)))
  "Font lock mode face used to highlight AMS keywords."
  :group 'font-lock-highlighting-faces)

(let* ((verilog-type-font-keywords
	(eval-when-compile
	  (verilog-regexp-opt
	   '(
	     "and" "bit" "buf" "bufif0" "bufif1" "cmos" "defparam"

       (verilog-font-keywords
	(eval-when-compile
	  (verilog-regexp-opt
	   '(
	     "assign" "begin" "case" "casex" "casez" "randcase" "deassign"
	     "default" "disable" "else" "end" "endcase" "endfunction"
	     "endgenerate" "endinterface" "endmodule" "endprimitive"
	     "endspecify" "endtable" "endtask" "final" "for" "force" "return" "break"
	     "continue" "forever" "fork" "function" "generate" "if" "iff" "initial"
	     "interface" "join" "join_any" "join_none" "macromodule" "module" "negedge"
	     "package" "endpackage" "always" "always_comb" "always_ff"
	     "always_latch" "posedge" "primitive" "priority" "release"
	     "repeat" "specify" "table" "task" "unique" "wait" "while"
	     "class" "program" "endclass" "endprogram"
	     ) nil  ))))

  (setq verilog-font-lock-keywords
	(list
	 ;; Fontify all builtin keywords
	 (concat "\\<\\(" verilog-font-keywords "\\|"
		       ;; And user/system tasks and functions
		       "\\$[a-zA-Z][a-zA-Z0-9_\\$]*"
		       "\\)\\>")
	 ;; Fontify all types
	 (cons (concat "\\<\\(" verilog-type-font-keywords "\\)\\>")
	       'font-lock-type-face)
	 ;; Fontify IEEE-P1800 keywords appropriately
	 (if verilog-highlight-p1800-keywords
	     (cons (concat "\\<\\(" verilog-p1800-keywords "\\)\\>")
		   'verilog-font-lock-p1800-face)

    (if (not (looking-at "\\<"))
	(forward-word -1))
    (cond
     ((verilog-skip-forward-comment-or-string)
      (verilog-forward-syntactic-ws))
     ((looking-at verilog-beg-block-re-ordered);; begin|case|fork|class|table|specify|function|task|generate|covergroup|property|sequence|clocking
      (cond
       ((match-end 1) ; end
	;; Search forward for matching begin
	(setq reg "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)" ))
       ((match-end 2) ; endcase
	;; Search forward for matching case
	(setq reg "\\(\\<randcase\\>\\|\\(\\<unique\\>\\s-+\\|\\<priority\\>\\s-+\\)?\\<case[xz]?\\>[^:]\\)\\|\\(\\<endcase\\>\\)" ))
       ((match-end 3) ; join
	;; Search forward for matching fork
	(setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" ))
       ((match-end 4) ; endclass
	;; Search forward for matching class
	(setq reg "\\(\\<class\\>\\)\\|\\(\\<endclass\\>\\)" ))
       ((match-end 5) ; endtable
	;; Search forward for matching table
	(setq reg "\\(\\<table\\>\\)\\|\\(\\<endtable\\>\\)" ))
       ((match-end 6) ; endspecify
	;; Search forward for matching specify
	(setq reg "\\(\\<specify\\>\\)\\|\\(\\<endspecify\\>\\)" ))
       ((match-end 7) ; endfunction
	;; Search forward for matching function
	(setq reg "\\(\\<function\\>\\)\\|\\(\\<endfunction\\>\\)" ))
       ((match-end 8) ; endtask
	;; Search forward for matching task
	(setq reg "\\(\\<task\\>\\)\\|\\(\\<endtask\\>\\)" ))
       ((match-end 9) ; endgenerate
	;; Search forward for matching generate
	(setq reg "\\(\\<generate\\>\\)\\|\\(\\<endgenerate\\>\\)" ))
       ((match-end 10) ; endgroup
	;; Search forward for matching covergroup
	(setq reg "\\(\\<covergroup\\>\\)\\|\\(\\<endgroup\\>\\)" ))
       ((match-end 11) ; endproperty
	;; Search forward for matching property
	(setq reg "\\(\\<property\\>\\)\\|\\(\\<endproperty\\>\\)" ))
       ((match-end 12) ; endsequence
	;; Search forward for matching sequence
	(setq reg "\\(\\<\\(rand\\)?sequence\\>\\)\\|\\(\\<endsequence\\>\\)" )
	(setq md 3)) ; 3 to get to endsequence in the reg above
       ((match-end 13) ; endclocking
	;; Search forward for matching clocking
	(setq reg "\\(\\<clocking\\>\\)\\|\\(\\<endclocking\\>\\)" )))
      (if (forward-word 1)
	  (catch 'skip
	    (let ((nest 1))
	      (while (verilog-re-search-forward reg nil 'move)
		(cond
		 ((match-end md) ; the closer in reg, so we are climbing out

	    (verilog-beg-of-statement)
	    (if (looking-at verilog-extended-case-re)
		(throw 'nesting 'case)
	      (goto-char here)))
	  (throw 'nesting 'case))

	 ;; need to consider typedef struct here...
	 ((looking-at "\\<class\\|struct\\|function\\|task\\|property\\>")
					; *sigh* These words have an optional prefix:
					; extern {virtual|protected}? function a();

   (;-- any of begin|initial|while are complete statements; 'begin : foo' is also complete
    t
    (forward-word -1)
    (cond
     ((looking-at "\\<else\\>")
      t)
     ((looking-at verilog-indent-re)
      nil)
     (t
      (let

80171:97019d686b43

;; (This section is required to appease checkdoc.)

;;; Code:

;; This variable will always hold the version number of the mode
(defconst verilog-mode-version "399"
  "Version of this Verilog mode.")
(defconst verilog-mode-release-date "2008-02-19-GNU"
  "Release date of this Verilog mode.")
(defconst verilog-mode-release-emacs t
  "If non-nil, this version of Verilog mode was released with Emacs itself.")

(defun verilog-version ()

	(verilog-set-compile-command))
      :style radio
      :selected (equal verilog-tool `verilog-compiler)]
     )
    ("Move"
     ["Beginning of function"           verilog-beg-of-defun t]
     ["End of function"                 verilog-end-of-defun t]
     ["Mark function"                   verilog-mark-defun t]
     ["Goto function/module"		verilog-goto-defun t]
     ["Move to beginning of block"	electric-verilog-backward-sexp t]
     ["Move to end of block"		electric-verilog-forward-sexp t]
     )
    ("Comments"

;; verilog-forward-sexp and verilog-calc-indent

(defconst verilog-beg-block-re-ordered
  ( concat "\\<"
	   "\\(begin\\)"		;1
	   "\\|\\(randcase\\|\\(unique\\s-+\\|priority\\s-+\\)?case[xz]?\\)" ; 2,3
	   "\\|\\(\\(disable\\s-+\\)?fork\\)" ;4
	   "\\|\\(class\\)"		;5
	   "\\|\\(table\\)"		;6
	   "\\|\\(specify\\)"		;7
	   "\\|\\(function\\)"		;8
	   "\\|\\(task\\)"		;9
	   "\\|\\(generate\\)"		;10
	   "\\|\\(covergroup\\)"	;11
	   "\\|\\(property\\)"		;12
	   "\\|\\(\\(rand\\)?sequence\\)" ;13
	   "\\|\\(clocking\\)"          ;14
	   "\\>"))

(defconst verilog-end-block-ordered-rry
  [ "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)\\|\\(\\<endcase\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)"
    "\\(\\<randcase\\>\\|\\<case[xz]?\\>\\)\\|\\(\\<endcase\\>\\)"

  (eval-when-compile (verilog-regexp-words `("endmodule" "endclass" "endprogram" "endinterface" "endpackage" "endprimitive" "endconfig"))))
(defconst verilog-zero-indent-re
  (concat verilog-defun-re "\\|" verilog-end-defun-re))

(defconst verilog-behavioral-block-beg-re
  (eval-when-compile (verilog-regexp-words `("initial" "final" "always" "always_comb" "always_latch" "always_ff"
					     "function" "task"))))

(defconst verilog-indent-re
  (eval-when-compile
    (verilog-regexp-words
     `(

  (eval-when-compile
    (verilog-regexp-words
     `(
       "endmodule" "endprimitive" "endinterface" "endpackage" "endprogram" "endclass"
       ))))
(defconst verilog-disable-fork-re "disable\\s-+fork")
(defconst verilog-extended-case-re "\\(unique\\s-+\\|priority\\s-+\\)?case[xz]?")
(defconst verilog-extended-complete-re
  (concat "\\(\\<extern\\s-+\\|\\<virtual\\s-+\\|\\<protected\\s-+\\)*\\(\\<function\\>\\|\\<task\\>\\)"
	  "\\|\\(\\<typedef\\>\\s-+\\)*\\(\\<struct\\>\\|\\<union\\>\\|\\<class\\>\\)"
	  "\\|" verilog-extended-case-re ))

     (:foreground "orange1" :bold t ))
    (t (:italic t)))
  "Font lock mode face used to highlight AMS keywords."
  :group 'font-lock-highlighting-faces)

(defvar verilog-font-grouping-keywords-face
  'verilog-font-lock-grouping-keywords-face
  "Font to use for Verilog Grouping Keywords (such as begin..end).")
(defface verilog-font-lock-grouping-keywords-face
  '((((class color)
      (background light))
     (:foreground "red4" :bold t ))
    (((class color)
      (background dark))
     (:foreground "red4" :bold t ))
    (t (:italic t)))
  "Font lock mode face used to highlight verilog grouping keywords."
  :group 'font-lock-highlighting-faces)

(let* ((verilog-type-font-keywords
	(eval-when-compile
	  (verilog-regexp-opt
	   '(
	     "and" "bit" "buf" "bufif0" "bufif1" "cmos" "defparam"

       (verilog-font-keywords
	(eval-when-compile
	  (verilog-regexp-opt
	   '(
	     "assign" "case" "casex" "casez" "randcase" "deassign"
	     "default" "disable" "else" "endcase" "endfunction"
	     "endgenerate" "endinterface" "endmodule" "endprimitive"
	     "endspecify" "endtable" "endtask" "final" "for" "force" "return" "break"
	     "continue" "forever" "fork" "function" "generate" "if" "iff" "initial"
	     "interface" "join" "join_any" "join_none" "macromodule" "module" "negedge"
	     "package" "endpackage" "always" "always_comb" "always_ff"
	     "always_latch" "posedge" "primitive" "priority" "release"
	     "repeat" "specify" "table" "task" "unique" "wait" "while"
	     "class" "program" "endclass" "endprogram"
	     ) nil  )))

       (verilog-font-grouping-keywords
	(eval-when-compile
	  (verilog-regexp-opt
	   '( "begin" "end" ) nil  ))))

  (setq verilog-font-lock-keywords
	(list
	 ;; Fontify all builtin keywords
	 (concat "\\<\\(" verilog-font-keywords "\\|"
		       ;; And user/system tasks and functions
		       "\\$[a-zA-Z][a-zA-Z0-9_\\$]*"
		       "\\)\\>")
	 ;; Fontify all types
	 (cons (concat "\\(\\<" verilog-font-grouping-keywords "\\)\\>") 
	       'verilog-font-lock-ams-face)
	 (cons (concat "\\<\\(" verilog-type-font-keywords "\\)\\>") 
	       'font-lock-type-face)
	 ;; Fontify IEEE-P1800 keywords appropriately
	 (if verilog-highlight-p1800-keywords
	     (cons (concat "\\<\\(" verilog-p1800-keywords "\\)\\>")
		   'verilog-font-lock-p1800-face)

    (if (not (looking-at "\\<"))
	(forward-word -1))
    (cond
     ((verilog-skip-forward-comment-or-string)
      (verilog-forward-syntactic-ws))
     ((looking-at verilog-beg-block-re-ordered) ;; begin|(case)|xx|(fork)|class|table|specify|function|task|generate|covergroup|property|sequence|clocking
      (cond
       ((match-end 1) ; end
	;; Search forward for matching begin
	(setq reg "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)" ))
       ((match-end 2) ; endcase
	;; Search forward for matching case
	(setq reg "\\(\\<randcase\\>\\|\\(\\<unique\\>\\s-+\\|\\<priority\\>\\s-+\\)?\\<case[xz]?\\>[^:]\\)\\|\\(\\<endcase\\>\\)" )
	(setq md 3) ;; ender is third item in regexp
	)
       ((match-end 4) ; join
	;; might be "disable fork"
	(if (or 
	     (looking-at verilog-disable-fork-re)
	     (and (looking-at "fork")
		  (progn
		    (forward-word -1)
		    (looking-at verilog-disable-fork-re))))
	    (progn
	      (goto-char (match-end 0))
	      (forward-word)
	      (setq reg nil))
	  (progn
	    ;; Search forward for matching fork
	    (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" ))))
       ((match-end 5) ; endclass
	;; Search forward for matching class
	(setq reg "\\(\\<class\\>\\)\\|\\(\\<endclass\\>\\)" ))
       ((match-end 6) ; endtable
	;; Search forward for matching table
	(setq reg "\\(\\<table\\>\\)\\|\\(\\<endtable\\>\\)" ))
       ((match-end 7) ; endspecify
	;; Search forward for matching specify
	(setq reg "\\(\\<specify\\>\\)\\|\\(\\<endspecify\\>\\)" ))
       ((match-end 8) ; endfunction
	;; Search forward for matching function
	(setq reg "\\(\\<function\\>\\)\\|\\(\\<endfunction\\>\\)" ))
       ((match-end 9) ; endtask
	;; Search forward for matching task
	(setq reg "\\(\\<task\\>\\)\\|\\(\\<endtask\\>\\)" ))
       ((match-end 10) ; endgenerate
	;; Search forward for matching generate
	(setq reg "\\(\\<generate\\>\\)\\|\\(\\<endgenerate\\>\\)" ))
       ((match-end 11) ; endgroup
	;; Search forward for matching covergroup
	(setq reg "\\(\\<covergroup\\>\\)\\|\\(\\<endgroup\\>\\)" ))
       ((match-end 12) ; endproperty
	;; Search forward for matching property
	(setq reg "\\(\\<property\\>\\)\\|\\(\\<endproperty\\>\\)" ))
       ((match-end 13) ; endsequence
	;; Search forward for matching sequence
	(setq reg "\\(\\<\\(rand\\)?sequence\\>\\)\\|\\(\\<endsequence\\>\\)" )
	(setq md 3)) ; 3 to get to endsequence in the reg above
       ((match-end 14) ; endclocking
	;; Search forward for matching clocking
	(setq reg "\\(\\<clocking\\>\\)\\|\\(\\<endclocking\\>\\)" )))
      (if (and reg
	       (forward-word 1))
	  (catch 'skip
	    (let ((nest 1))
	      (while (verilog-re-search-forward reg nil 'move)
		(cond
		 ((match-end md) ; the closer in reg, so we are climbing out

	    (verilog-beg-of-statement)
	    (if (looking-at verilog-extended-case-re)
		(throw 'nesting 'case)
	      (goto-char here)))
	  (throw 'nesting 'case))
	 
	 ((match-end 4)  ; *sigh* could be "disable fork"
	  (let ((here (point)))
	    (verilog-beg-of-statement)
	    (if (looking-at verilog-disable-fork-re)
		t ; is disable fork, this is a normal statement
	      (progn ; or is fork, starts a new block
		(goto-char here)
		(throw 'nesting 'block)))))


	 ;; need to consider typedef struct here...
	 ((looking-at "\\<class\\|struct\\|function\\|task\\|property\\>")
					; *sigh* These words have an optional prefix:
					; extern {virtual|protected}? function a();

   (;-- any of begin|initial|while are complete statements; 'begin : foo' is also complete
    t
    (forward-word -1)
    (cond
     ((looking-at "\\<else\\>")
      t)
     ((looking-at verilog-behavioral-block-beg-re)
      t)
     ((looking-at verilog-indent-re)
      nil)
     (t
      (let