comparison lisp/progmodes/verilog-mode.el @ 93340:971b85f6050d

* progmodes/verilog-mode.el (verilog-auto-inout-module): Add optional regular expression to AUTOINOUTMODULE. (verilog-inject-auto, verilog-auto-arg, verilog-auto-inst) (verilog-auto-inst-param, verilog-auto-reg) (verilog-auto-reg-input, verilog-auto-wire, verilog-auto-output) (verilog-auto-output-every, verilog-auto-input) (verilog-auto-inout, verilog-auto-sense, verilog-auto-tieoff) (verilog-auto-unused, verilog-auto): Update documentation to use more obvious instance module names versus cell names.

93339:ed66b85b0c05

component library to determine connectivity of the design.

One work around for this problem is to manually create // Inputs and //
Outputs comments above subcell signals, for example:

	module1 instance1x (
	    // Outputs
	    .out (out),
	    // Inputs
	    .in  (in));"
  (save-excursion

Argument lists will not be deleted, /*AUTOARG*/ will only be inserted to
support adding new ports.  You may wish to delete older ports yourself.

For example:

	module ex_inject (i, o);
	  input i;
	  input j;
	  output o;
	  always @ (i or j)
	     o = i | j;
	  cell cell (.foobar(baz),
		     .j(j));
	endmodule

Typing \\[verilog-inject-auto] will make this into:

	module ex_inject (i, o/*AUTOARG*/
	  // Inputs
	  j);
	  input i;
	  output o;
	  always @ (/*AS*/i or j)
	     o = i | j;
	  cell cell (.foobar(baz),
		     /*AUTOINST*/
		     // Outputs
		     .j(j));
	endmodule"
  (interactive)
  (verilog-auto t))

(defun verilog-inject-arg ()

  Typedefs must match `verilog-typedef-regexp', which is disabled by default.

For example:

	module ex_arg (/*AUTOARG*/);
	  input i;
	  output o;
	endmodule

Typing \\[verilog-auto] will make this into:

	module ex_arg (/*AUTOARG*/
	  // Outputs
	  o,
	  // Inputs
	  i
	);

  Typedefs must match `verilog-typedef-regexp', which is disabled by default.

  SystemVerilog multidimensional input/output has only experimental support.

For example, first take the submodule inst.v:

	module inst (o,i)
	   output [31:0] o;
	   input i;
	   wire [31:0] o = {32{i}};
	endmodule

This is then used in a upper level module:

	module ex_inst (o,i)
	   output o;
	   input i;
	   inst inst (/*AUTOINST*/);
	endmodule

Typing \\[verilog-auto] will make this into:

	module ex_inst (o,i)
	   output o;
	   input i;
	   inst inst (/*AUTOINST*/
		      // Outputs
		      .ov			(ov[31:0]),
		      // Inputs
		      .i			(i));
	endmodule

Where the list of inputs and outputs came from the inst module.

Exceptions:

  is restricted to simple connections just like you normally make.  Also note
  that any signals before the AUTOINST will only be picked up by AUTOWIRE if
  you have the appropriate // Input or // Output comment, and exactly the
  same line formatting as AUTOINST itself uses.

	inst inst (// Inputs
		   .i		(my_i_dont_mess_with_it),
		   /*AUTOINST*/
		   // Outputs
		   .ov		(ov[31:0]));


Templates:

  For multiple instantiations based upon a single template, create a
  commented out template:

	/* instantiating_module_name AUTO_TEMPLATE (
		.sig3	(sigz[]),
		);
	*/

  Templates go ABOVE the instantiation(s).  When an instantiation is

  debugging is completed though, it will result in lots of extra differences
  and merge conflicts.

  For example:

	/* psm_mas AUTO_TEMPLATE (
		.ptl_bus	(ptl_busnew[]),
		);
	*/
	psm_mas ms2m (/*AUTOINST*/);

  Typing \\[verilog-auto] will make this into:

	psm_mas ms2m (/*AUTOINST*/
	    // Outputs
	    .NotInTemplate	(NotInTemplate),
	    .ptl_bus		(ptl_busnew[3:0]),  // Templated
	    ....

@ Templates:

  It is common to instantiate a cell multiple times, so templates make it
  trivial to substitute part of the cell name into the connection name.

	/* cell_type AUTO_TEMPLATE <optional \"REGEXP\"> (
		.sig1	(sigx[@]),
		.sig2	(sigy[@\"(% (+ 1 @) 4)\"]),
		);
	*/

  \"\\(test\\([a-z]+\\)_\\([0-9]+\\)\\)\" would replace @ with the entire
  match.

  For example:

	/* psm_mas AUTO_TEMPLATE (
		.ptl_mapvalidx		(ptl_mapvalid[@]),
		.ptl_mapvalidp1x	(ptl_mapvalid[@\"(% (+ 1 @) 4)\"]),
		);
	*/
	psm_mas ms2m (/*AUTOINST*/);

  Typing \\[verilog-auto] will make this into:

	psm_mas ms2m (/*AUTOINST*/
	    // Outputs
	    .ptl_mapvalidx		(ptl_mapvalid[2]),
	    .ptl_mapvalidp1x		(ptl_mapvalid[3]));

  Note the @ character was replaced with the 2 from \"ms2m\".

  Alternatively, using a regular expression for @:

	/* psm_mas AUTO_TEMPLATE \"_\\([a-z]+\\)\" (
		.ptl_mapvalidx		(@_ptl_mapvalid),
		.ptl_mapvalidp1x	(ptl_mapvalid_@),
		);
	*/
	psm_mas ms2_FOO (/*AUTOINST*/);
	psm_mas ms2_BAR (/*AUTOINST*/);

  Typing \\[verilog-auto] will make this into:

	psm_mas ms2_FOO (/*AUTOINST*/
	    // Outputs
	    .ptl_mapvalidx		(FOO_ptl_mapvalid),
	    .ptl_mapvalidp1x		(ptl_mapvalid_FOO));
	psm_mas ms2_BAR (/*AUTOINST*/
	    // Outputs
	    .ptl_mapvalidx		(BAR_ptl_mapvalid),
	    .ptl_mapvalidp1x		(ptl_mapvalid_BAR));



	vl-name        Name portion of the input/output port.
	vl-bits        Bus bits portion of the input/output port ('[2:0]').
	vl-width       Width of the input/output port ('3' for [2:0]).
                       May be a (...) expression if bits isn't a constant.
	vl-dir         Direction of the pin input/output/inout.
	vl-cell-type   Module name/type of the cell ('psm_mas').
	vl-cell-name   Instance name of the cell ('ms2m').

  Normal Lisp variables may be used in expressions.  See
  `verilog-read-defines' which can set vh-{definename} variables for use
  here.  Also, any comments of the form:

automatically derived from the module header of the instantiated netlist.

See \\[verilog-auto-inst] for limitations, and templates to customize the
output.

For example, first take the submodule inst.v:

	module inst (o,i)
	   parameter PAR;
	endmodule

This is then used in a upper level module:

	module ex_inst (o,i)
	   parameter PAR;
	   inst #(/*AUTOINSTPARAM*/)
		inst (/*AUTOINST*/);
	endmodule

Typing \\[verilog-auto] will make this into:

	module ex_inst (o,i)
	   output o;
	   input i;
	   inst (/*AUTOINSTPARAM*/
		 // Parameters
		 .PAR			(PAR));
		inst (/*AUTOINST*/);
	endmodule

Where the list of parameter connections come from the inst module.

Templates:

  This does NOT work on memories, declare those yourself.

An example:

	module ex_reg (o,i)
	   output o;
	   input i;
	   /*AUTOREG*/
	   always o = i;
	endmodule

Typing \\[verilog-auto] will make this into:

	module ex_reg (o,i)
	   output o;
	   input i;
	   /*AUTOREG*/
	   // Beginning of automatic regs (for this module's undeclared outputs)
	   reg			o;
	   // End of automatics
	   always o = i;
	endmodule"
  (save-excursion
    ;; Point must be at insertion point.

  This does NOT work on memories, declare those yourself.

An example (see `verilog-auto-inst' for what else is going on here):

	module ex_reg_input (o,i)
	   output o;
	   input i;
	   /*AUTOREGINPUT*/
           inst inst (/*AUTOINST*/);
	endmodule

Typing \\[verilog-auto] will make this into:

	module ex_reg_input (o,i)
	   output o;
	   input i;
	   /*AUTOREGINPUT*/
	   // Beginning of automatic reg inputs (for undeclared ...
	   reg [31:0]		iv;		// From inst of inst.v
	   // End of automatics
	   inst inst (/*AUTOINST*/
		      // Outputs
		      .o			(o[31:0]),
		      // Inputs
		      .iv			(iv));
	endmodule"
  (save-excursion
    ;; Point must be at insertion point.
    (let* ((indent-pt (current-indentation))
	   (modi (verilog-modi-current))

  non-numeric or non-sequential bus subscripts.  If Verilog mode
  mis-guessed, you'll have to declare them yourself.

An example (see `verilog-auto-inst' for what else is going on here):

	module ex_wire (o,i)
	   output o;
	   input i;
	   /*AUTOWIRE*/
           inst inst (/*AUTOINST*/);
	endmodule

Typing \\[verilog-auto] will make this into:

	module ex_wire (o,i)
	   output o;
	   input i;
	   /*AUTOWIRE*/
	   // Beginning of automatic wires
	   wire [31:0]		ov;	// From inst of inst.v
	   // End of automatics
	   inst inst (/*AUTOINST*/
		      // Outputs
		      .ov	(ov[31:0]),
		      // Inputs
		      .i	(i));
	   wire o = | ov;
	endmodule"
  (save-excursion
    ;; Point must be at insertion point.
    (let* ((indent-pt (current-indentation))

  Signals matching `verilog-auto-output-ignore-regexp' are not included.

An example (see `verilog-auto-inst' for what else is going on here):

	module ex_output (ov,i)
	   input i;
	   /*AUTOOUTPUT*/
	   inst inst (/*AUTOINST*/);
	endmodule

Typing \\[verilog-auto] will make this into:

	module ex_output (ov,i)
	   input i;
	   /*AUTOOUTPUT*/
	   // Beginning of automatic outputs (from unused autoinst outputs)
	   output [31:0]	ov;			// From inst of inst.v
	   // End of automatics
	   inst inst (/*AUTOINST*/
		      // Outputs
		      .ov			(ov[31:0]),
		      // Inputs
		      .i			(i));
	endmodule

You may also provide an optional regular expression, in which case only
signals matching the regular expression will be included.  For example the
same expansion will result from only extracting outputs starting with ov:

useful to get Synopsys to preserve every signal in the design, since it
won't optimize away the outputs.

An example:

	module ex_output_every (o,i,tempa,tempb)
	   output o;
	   input i;
	   /*AUTOOUTPUTEVERY*/
	   wire tempa = i;
	   wire tempb = tempa;
	   wire o = tempb;
	endmodule

Typing \\[verilog-auto] will make this into:

	module ex_output_every (o,i,tempa,tempb)
	   output o;
	   input i;
	   /*AUTOOUTPUTEVERY*/
	   // Beginning of automatic outputs (every signal)
	   output		tempb;
	   output		tempa;
	   // End of automatics
	   wire tempa = i;
	   wire tempb = tempa;
	   wire o = tempb;
	endmodule"

  Signals matching `verilog-auto-input-ignore-regexp' are not included.

An example (see `verilog-auto-inst' for what else is going on here):

	module ex_input (ov,i)
	   output [31:0] ov;
	   /*AUTOINPUT*/
	   inst inst (/*AUTOINST*/);
	endmodule

Typing \\[verilog-auto] will make this into:

	module ex_input (ov,i)
	   output [31:0] ov;
	   /*AUTOINPUT*/
	   // Beginning of automatic inputs (from unused autoinst inputs)
	   input		i;			// From inst of inst.v
	   // End of automatics
	   inst inst (/*AUTOINST*/
		      // Outputs
		      .ov			(ov[31:0]),
		      // Inputs
		      .i			(i));
	endmodule

You may also provide an optional regular expression, in which case only
signals matching the regular expression will be included.  For example the
same expansion will result from only extracting inputs starting with i:

  Signals matching `verilog-auto-inout-ignore-regexp' are not included.

An example (see `verilog-auto-inst' for what else is going on here):

	module ex_inout (ov,i)
	   input i;
	   /*AUTOINOUT*/
	   inst inst (/*AUTOINST*/);
	endmodule

Typing \\[verilog-auto] will make this into:

	module ex_inout (ov,i)
	   input i;
	   /*AUTOINOUT*/
	   // Beginning of automatic inouts (from unused autoinst inouts)
	   inout [31:0]	ov;			// From inst of inst.v
	   // End of automatics
	   inst inst (/*AUTOINST*/
		      // Inouts
		      .ov			(ov[31:0]),
		      // Inputs
		      .i			(i));
	endmodule

You may also provide an optional regular expression, in which case only
signals matching the regular expression will be included.  For example the
same expansion will result from only extracting inouts starting with i:

  though they will appear to be in the same order to a AUTOINST
  instantiating either module.

An example:

	module ex_shell (/*AUTOARG*/)
	   /*AUTOINOUTMODULE(\"ex_main\")*/
	endmodule

	module ex_main (i,o,io)
          input i;
          output o;
          inout io;
        endmodule

Typing \\[verilog-auto] will make this into:

	module ex_shell (/*AUTOARG*/i,o,io)
	   /*AUTOINOUTMODULE(\"ex_main\")*/
           // Beginning of automatic in/out/inouts (from specific module)
           input i;
           output o;
           inout io;
	   // End of automatics
	endmodule"
  (save-excursion
    (let* ((submod (car (verilog-read-auto-params 1))) submodi)
      ;; Lookup position, etc of co-module
      ;; Note this may raise an error
      (when (setq submodi (verilog-modi-lookup submod t))
	(let* ((indent-pt (current-indentation))
	       (v2k  (verilog-in-paren))

			     (append (verilog-modi-get-outputs modi))))
	       (sig-list-io (verilog-signals-not-in
			     (verilog-modi-get-inouts submodi)
			     (append (verilog-modi-get-inouts modi)))))
	  (forward-line 1)
	  (when v2k (verilog-repair-open-comma))
	  (when (or sig-list-i sig-list-o sig-list-io)
	    (verilog-insert-indent "// Beginning of automatic in/out/inouts (from specific module)\n")
	    ;; Don't sort them so a upper AUTOINST will match the main module
	    (verilog-insert-definition sig-list-o  "output" indent-pt v2k t)

  the /*AUTOSENSE*/ comment will prevent it from being deleted when the
  autos are updated (or added if it occurs there already).

An example:

	   always @ (/*AUTOSENSE*/) begin
	      /* AUTO_CONSTANT (`constant) */
	      outin = ina | inb | `constant;
	      out = outin;
	   end

Typing \\[verilog-auto] will make this into:

	   always @ (/*AUTOSENSE*/ina or inb) begin
	      /* AUTO_CONSTANT (`constant) */
	      outin = ina | inb | `constant;
	      out = outin;
	   end"
  (save-excursion
    ;; Find beginning

Signals that match `verilog-active-low-regexp' will be deasserted by tieing
them to a one.

An example of making a stub for another module:

    module FooStub (/*AUTOINST*/);
	/*AUTOINOUTMODULE(\"Foo\")*/
        /*AUTOTIEOFF*/
        // verilator lint_off UNUSED
        wire _unused_ok = &{1'b0,
                            /*AUTOUNUSED*/

        // verilator lint_on  UNUSED
    endmodule

Typing \\[verilog-auto] will make this into:

    module FooStub (/*AUTOINST*/...);
	/*AUTOINOUTMODULE(\"Foo\")*/
        // Beginning of autotieoff
        output [2:0] foo;
        // End of automatics

You can add signals you do not want included in AUTOUNUSED with
`verilog-auto-unused-ignore-regexp'.

An example of making a stub for another module:

    module FooStub (/*AUTOINST*/);
	/*AUTOINOUTMODULE(\"Foo\")*/
        /*AUTOTIEOFF*/
        // verilator lint_off UNUSED
        wire _unused_ok = &{1'b0,
                            /*AUTOUNUSED*/
                            1'b0};

The hooks `verilog-before-auto-hook' and `verilog-auto-hook' are
called before and after this function, respectively.

For example:
	module (/*AUTOARG*/)
	/*AUTOINPUT*/
	/*AUTOOUTPUT*/
	/*AUTOWIRE*/
	/*AUTOREG*/
	somesub sub #(/*AUTOINSTPARAM*/) (/*AUTOINST*/);

You can also update the AUTOs from the shell using:
	emacs --batch  <filenames.v>  -f verilog-batch-auto
Or fix indentation with:
	emacs --batch  <filenames.v>  -f verilog-batch-indent

93340:971b85f6050d

component library to determine connectivity of the design.

One work around for this problem is to manually create // Inputs and //
Outputs comments above subcell signals, for example:

	module ModuleName (
	    // Outputs
	    .out (out),
	    // Inputs
	    .in  (in));"
  (save-excursion

Argument lists will not be deleted, /*AUTOARG*/ will only be inserted to
support adding new ports.  You may wish to delete older ports yourself.

For example:

	module ExampInject (i, o);
	  input i;
	  input j;
	  output o;
	  always @ (i or j)
	     o = i | j;
	  InstModule instName
            (.foobar(baz),
	     j(j));
	endmodule

Typing \\[verilog-inject-auto] will make this into:

	module ExampInject (i, o/*AUTOARG*/
	  // Inputs
	  j);
	  input i;
	  output o;
	  always @ (/*AS*/i or j)
	     o = i | j;
	  InstModule instName
            (.foobar(baz),
	     /*AUTOINST*/
	     // Outputs
	     j(j));
	endmodule"
  (interactive)
  (verilog-auto t))

(defun verilog-inject-arg ()

  Typedefs must match `verilog-typedef-regexp', which is disabled by default.

For example:

	module ExampArg (/*AUTOARG*/);
	  input i;
	  output o;
	endmodule

Typing \\[verilog-auto] will make this into:

	module ExampArg (/*AUTOARG*/
	  // Outputs
	  o,
	  // Inputs
	  i
	);

  Typedefs must match `verilog-typedef-regexp', which is disabled by default.

  SystemVerilog multidimensional input/output has only experimental support.

For example, first take the submodule InstModule.v:

	module InstModule (o,i)
	   output [31:0] o;
	   input i;
	   wire [31:0] o = {32{i}};
	endmodule

This is then used in a upper level module:

	module ExampInst (o,i)
	   output o;
	   input i;
	   InstModule instName
	     (/*AUTOINST*/);
	endmodule

Typing \\[verilog-auto] will make this into:

	module ExampInst (o,i)
	   output o;
	   input i;
	   InstModule instName
	     (/*AUTOINST*/
	      // Outputs
	      .ov	(ov[31:0]),
	      // Inputs
	      .i	(i));
	endmodule

Where the list of inputs and outputs came from the inst module.

Exceptions:

  is restricted to simple connections just like you normally make.  Also note
  that any signals before the AUTOINST will only be picked up by AUTOWIRE if
  you have the appropriate // Input or // Output comment, and exactly the
  same line formatting as AUTOINST itself uses.

	InstModule instName
          (// Inputs
	   .i		(my_i_dont_mess_with_it),
	   /*AUTOINST*/
	   // Outputs
	   .ov		(ov[31:0]));


Templates:

  For multiple instantiations based upon a single template, create a
  commented out template:

	/* InstModule AUTO_TEMPLATE (
		.sig3	(sigz[]),
		);
	*/

  Templates go ABOVE the instantiation(s).  When an instantiation is

  debugging is completed though, it will result in lots of extra differences
  and merge conflicts.

  For example:

	/* InstModule AUTO_TEMPLATE (
		.ptl_bus	(ptl_busnew[]),
		);
	*/
	InstModule ms2m (/*AUTOINST*/);

  Typing \\[verilog-auto] will make this into:

	InstModule ms2m (/*AUTOINST*/
	    // Outputs
	    .NotInTemplate	(NotInTemplate),
	    .ptl_bus		(ptl_busnew[3:0]),  // Templated
	    ....

@ Templates:

  It is common to instantiate a cell multiple times, so templates make it
  trivial to substitute part of the cell name into the connection name.

	/* InstName AUTO_TEMPLATE <optional \"REGEXP\"> (
		.sig1	(sigx[@]),
		.sig2	(sigy[@\"(% (+ 1 @) 4)\"]),
		);
	*/

  \"\\(test\\([a-z]+\\)_\\([0-9]+\\)\\)\" would replace @ with the entire
  match.

  For example:

	/* InstModule AUTO_TEMPLATE (
		.ptl_mapvalidx		(ptl_mapvalid[@]),
		.ptl_mapvalidp1x	(ptl_mapvalid[@\"(% (+ 1 @) 4)\"]),
		);
	*/
	InstModule ms2m (/*AUTOINST*/);

  Typing \\[verilog-auto] will make this into:

	InstModule ms2m (/*AUTOINST*/
	    // Outputs
	    .ptl_mapvalidx		(ptl_mapvalid[2]),
	    .ptl_mapvalidp1x		(ptl_mapvalid[3]));

  Note the @ character was replaced with the 2 from \"ms2m\".

  Alternatively, using a regular expression for @:

	/* InstModule AUTO_TEMPLATE \"_\\([a-z]+\\)\" (
		.ptl_mapvalidx		(@_ptl_mapvalid),
		.ptl_mapvalidp1x	(ptl_mapvalid_@),
		);
	*/
	InstModule ms2_FOO (/*AUTOINST*/);
	InstModule ms2_BAR (/*AUTOINST*/);

  Typing \\[verilog-auto] will make this into:

	InstModule ms2_FOO (/*AUTOINST*/
	    // Outputs
	    .ptl_mapvalidx		(FOO_ptl_mapvalid),
	    .ptl_mapvalidp1x		(ptl_mapvalid_FOO));
	InstModule ms2_BAR (/*AUTOINST*/
	    // Outputs
	    .ptl_mapvalidx		(BAR_ptl_mapvalid),
	    .ptl_mapvalidp1x		(ptl_mapvalid_BAR));



	vl-name        Name portion of the input/output port.
	vl-bits        Bus bits portion of the input/output port ('[2:0]').
	vl-width       Width of the input/output port ('3' for [2:0]).
                       May be a (...) expression if bits isn't a constant.
	vl-dir         Direction of the pin input/output/inout.
	vl-cell-type   Module name/type of the cell ('InstModule').
	vl-cell-name   Instance name of the cell ('instName').

  Normal Lisp variables may be used in expressions.  See
  `verilog-read-defines' which can set vh-{definename} variables for use
  here.  Also, any comments of the form:

automatically derived from the module header of the instantiated netlist.

See \\[verilog-auto-inst] for limitations, and templates to customize the
output.

For example, first take the submodule InstModule.v:

	module InstModule (o,i)
	   parameter PAR;
	endmodule

This is then used in a upper level module:

	module ExampInst (o,i)
	   parameter PAR;
	   InstModule #(/*AUTOINSTPARAM*/)
		instName (/*AUTOINST*/);
	endmodule

Typing \\[verilog-auto] will make this into:

	module ExampInst (o,i)
	   output o;
	   input i;
	   InstModule #(/*AUTOINSTPARAM*/
		        // Parameters
		        .PAR	(PAR));
		instName (/*AUTOINST*/);
	endmodule

Where the list of parameter connections come from the inst module.

Templates:

  This does NOT work on memories, declare those yourself.

An example:

	module ExampReg (o,i)
	   output o;
	   input i;
	   /*AUTOREG*/
	   always o = i;
	endmodule

Typing \\[verilog-auto] will make this into:

	module ExampReg (o,i)
	   output o;
	   input i;
	   /*AUTOREG*/
	   // Beginning of automatic regs (for this module's undeclared outputs)
	   reg		o;
	   // End of automatics
	   always o = i;
	endmodule"
  (save-excursion
    ;; Point must be at insertion point.

  This does NOT work on memories, declare those yourself.

An example (see `verilog-auto-inst' for what else is going on here):

	module ExampRegInput (o,i)
	   output o;
	   input i;
	   /*AUTOREGINPUT*/
           InstModule instName
             (/*AUTOINST*/);
	endmodule

Typing \\[verilog-auto] will make this into:

	module ExampRegInput (o,i)
	   output o;
	   input i;
	   /*AUTOREGINPUT*/
	   // Beginning of automatic reg inputs (for undeclared ...
	   reg [31:0]		iv;	// From inst of inst.v
	   // End of automatics
	   InstModule instName
             (/*AUTOINST*/
	      // Outputs
	      .o		(o[31:0]),
	      // Inputs
	      .iv		(iv));
	endmodule"
  (save-excursion
    ;; Point must be at insertion point.
    (let* ((indent-pt (current-indentation))
	   (modi (verilog-modi-current))

  non-numeric or non-sequential bus subscripts.  If Verilog mode
  mis-guessed, you'll have to declare them yourself.

An example (see `verilog-auto-inst' for what else is going on here):

	module ExampWire (o,i)
	   output o;
	   input i;
	   /*AUTOWIRE*/
           InstModule instName
	     (/*AUTOINST*/);
	endmodule

Typing \\[verilog-auto] will make this into:

	module ExampWire (o,i)
	   output o;
	   input i;
	   /*AUTOWIRE*/
	   // Beginning of automatic wires
	   wire [31:0]		ov;	// From inst of inst.v
	   // End of automatics
	   InstModule instName
	     (/*AUTOINST*/
	      // Outputs
	      .ov	(ov[31:0]),
	      // Inputs
	      .i	(i));
	   wire o = | ov;
	endmodule"
  (save-excursion
    ;; Point must be at insertion point.
    (let* ((indent-pt (current-indentation))

  Signals matching `verilog-auto-output-ignore-regexp' are not included.

An example (see `verilog-auto-inst' for what else is going on here):

	module ExampOutput (ov,i)
	   input i;
	   /*AUTOOUTPUT*/
	   InstModule instName
	     (/*AUTOINST*/);
	endmodule

Typing \\[verilog-auto] will make this into:

	module ExampOutput (ov,i)
	   input i;
	   /*AUTOOUTPUT*/
	   // Beginning of automatic outputs (from unused autoinst outputs)
	   output [31:0]	ov;	// From inst of inst.v
	   // End of automatics
	   InstModule instName
	     (/*AUTOINST*/
	      // Outputs
	      .ov	(ov[31:0]),
	      // Inputs
	      .i	(i));
	endmodule

You may also provide an optional regular expression, in which case only
signals matching the regular expression will be included.  For example the
same expansion will result from only extracting outputs starting with ov:

useful to get Synopsys to preserve every signal in the design, since it
won't optimize away the outputs.

An example:

	module ExampOutputEvery (o,i,tempa,tempb)
	   output o;
	   input i;
	   /*AUTOOUTPUTEVERY*/
	   wire tempa = i;
	   wire tempb = tempa;
	   wire o = tempb;
	endmodule

Typing \\[verilog-auto] will make this into:

	module ExampOutputEvery (o,i,tempa,tempb)
	   output o;
	   input i;
	   /*AUTOOUTPUTEVERY*/
	   // Beginning of automatic outputs (every signal)
	   output	tempb;
	   output	tempa;
	   // End of automatics
	   wire tempa = i;
	   wire tempb = tempa;
	   wire o = tempb;
	endmodule"

  Signals matching `verilog-auto-input-ignore-regexp' are not included.

An example (see `verilog-auto-inst' for what else is going on here):

	module ExampInput (ov,i)
	   output [31:0] ov;
	   /*AUTOINPUT*/
	   InstModule instName
	     (/*AUTOINST*/);
	endmodule

Typing \\[verilog-auto] will make this into:

	module ExampInput (ov,i)
	   output [31:0] ov;
	   /*AUTOINPUT*/
	   // Beginning of automatic inputs (from unused autoinst inputs)
	   input	i;	// From inst of inst.v
	   // End of automatics
	   InstModule instName
	     (/*AUTOINST*/
	      // Outputs
	      .ov	(ov[31:0]),
	      // Inputs
	      .i	(i));
	endmodule

You may also provide an optional regular expression, in which case only
signals matching the regular expression will be included.  For example the
same expansion will result from only extracting inputs starting with i:

  Signals matching `verilog-auto-inout-ignore-regexp' are not included.

An example (see `verilog-auto-inst' for what else is going on here):

	module ExampInout (ov,i)
	   input i;
	   /*AUTOINOUT*/
	   InstModule instName
	     (/*AUTOINST*/);
	endmodule

Typing \\[verilog-auto] will make this into:

	module ExampInout (ov,i)
	   input i;
	   /*AUTOINOUT*/
	   // Beginning of automatic inouts (from unused autoinst inouts)
	   inout [31:0]	ov;	// From inst of inst.v
	   // End of automatics
	   InstModule instName
	     (/*AUTOINST*/
	      // Inouts
	      .ov	(ov[31:0]),
	      // Inputs
	      .i	(i));
	endmodule

You may also provide an optional regular expression, in which case only
signals matching the regular expression will be included.  For example the
same expansion will result from only extracting inouts starting with i:

  though they will appear to be in the same order to a AUTOINST
  instantiating either module.

An example:

	module ExampShell (/*AUTOARG*/)
	   /*AUTOINOUTMODULE(\"ExampMain\")*/
	endmodule

	module ExampMain (i,o,io)
          input i;
          output o;
          inout io;
        endmodule

Typing \\[verilog-auto] will make this into:

	module ExampShell (/*AUTOARG*/i,o,io)
	   /*AUTOINOUTMODULE(\"ExampMain\")*/
           // Beginning of automatic in/out/inouts (from specific module)
           input i;
           output o;
           inout io;
	   // End of automatics
	endmodule

You may also provide an optional regular expression, in which case only
signals matching the regular expression will be included.  For example the
same expansion will result from only extracting signals starting with i:

	   /*AUTOINOUTMODULE(\"ExampMain\",\"^i\")*/"
  (save-excursion
    (let* ((params (verilog-read-auto-params 1 2))
	   (submod (nth 0 params))
	   (regexp (nth 1 params))
	   submodi)
      ;; Lookup position, etc of co-module
      ;; Note this may raise an error
      (when (setq submodi (verilog-modi-lookup submod t))
	(let* ((indent-pt (current-indentation))
	       (v2k  (verilog-in-paren))

			     (append (verilog-modi-get-outputs modi))))
	       (sig-list-io (verilog-signals-not-in
			     (verilog-modi-get-inouts submodi)
			     (append (verilog-modi-get-inouts modi)))))
	  (forward-line 1)
	  (when regexp
	    (setq sig-list-i  (verilog-signals-matching-regexp
			       sig-list-i regexp)
		  sig-list-o  (verilog-signals-matching-regexp
			       sig-list-o regexp)
		  sig-list-io (verilog-signals-matching-regexp
			       sig-list-io regexp)))
	  (when v2k (verilog-repair-open-comma))
	  (when (or sig-list-i sig-list-o sig-list-io)
	    (verilog-insert-indent "// Beginning of automatic in/out/inouts (from specific module)\n")
	    ;; Don't sort them so a upper AUTOINST will match the main module
	    (verilog-insert-definition sig-list-o  "output" indent-pt v2k t)

  the /*AUTOSENSE*/ comment will prevent it from being deleted when the
  autos are updated (or added if it occurs there already).

An example:

	   always @ (/*AS*/) begin
	      /* AUTO_CONSTANT (`constant) */
	      outin = ina | inb | `constant;
	      out = outin;
	   end

Typing \\[verilog-auto] will make this into:

	   always @ (/*AS*/ina or inb) begin
	      /* AUTO_CONSTANT (`constant) */
	      outin = ina | inb | `constant;
	      out = outin;
	   end

Note in Verilog 2001, you can often get the same result from the new @*
operator.  (This was added to the language in part due to AUTOSENSE!)

	   always @* begin
	      outin = ina | inb | `constant;
	      out = outin;
	   end"
  (save-excursion
    ;; Find beginning

Signals that match `verilog-active-low-regexp' will be deasserted by tieing
them to a one.

An example of making a stub for another module:

    module ExampStub (/*AUTOINST*/);
	/*AUTOINOUTMODULE(\"Foo\")*/
        /*AUTOTIEOFF*/
        // verilator lint_off UNUSED
        wire _unused_ok = &{1'b0,
                            /*AUTOUNUSED*/

        // verilator lint_on  UNUSED
    endmodule

Typing \\[verilog-auto] will make this into:

    module ExampStub (/*AUTOINST*/...);
	/*AUTOINOUTMODULE(\"Foo\")*/
        // Beginning of autotieoff
        output [2:0] foo;
        // End of automatics

You can add signals you do not want included in AUTOUNUSED with
`verilog-auto-unused-ignore-regexp'.

An example of making a stub for another module:

    module ExampStub (/*AUTOINST*/);
	/*AUTOINOUTMODULE(\"Examp\")*/
        /*AUTOTIEOFF*/
        // verilator lint_off UNUSED
        wire _unused_ok = &{1'b0,
                            /*AUTOUNUSED*/
                            1'b0};

The hooks `verilog-before-auto-hook' and `verilog-auto-hook' are
called before and after this function, respectively.

For example:
	module ModuleName (/*AUTOARG*/)
	/*AUTOINPUT*/
	/*AUTOOUTPUT*/
	/*AUTOWIRE*/
	/*AUTOREG*/
	InstMod instName #(/*AUTOINSTPARAM*/) (/*AUTOINST*/);

You can also update the AUTOs from the shell using:
	emacs --batch  <filenames.v>  -f verilog-batch-auto
Or fix indentation with:
	emacs --batch  <filenames.v>  -f verilog-batch-indent