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(verilog-read-decls): Fix AUTOINPUT/AUTOOUTPUT mis-including genvars.
author Dan Nicolaescu <dann@ics.uci.edu>
date Wed, 19 Mar 2008 03:43:11 +0000
parents 4318dfaeb2cb
children f991f10f15ec
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80341:25f843ea0096 80342:b7bed0a77336