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* progmodes/verilog-mode.el (verilog-auto-inout-module): Add optional regular expression to AUTOINOUTMODULE. (verilog-inject-auto, verilog-auto-arg, verilog-auto-inst) (verilog-auto-inst-param, verilog-auto-reg) (verilog-auto-reg-input, verilog-auto-wire, verilog-auto-output) (verilog-auto-output-every, verilog-auto-input) (verilog-auto-inout, verilog-auto-sense, verilog-auto-tieoff) (verilog-auto-unused, verilog-auto): Update documentation to use more obvious instance module names versus cell names.
author Dan Nicolaescu <dann@ics.uci.edu>
date Fri, 28 Mar 2008 15:47:25 +0000
parents 9bd8a8e2f2bc
children 1183cf6a4bb8
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The file SKK-JISYO.L is a verbatim copy of that distributed with SKK
Ver.8.6.  The author of SKK is Masahiko Sato
<masahiko@sato.riec.tohoku.ac.jp>.  SKK is free software distributed
under the terms of the GNU General Public License.