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(verilog-read-decls): Fix AUTOINPUT/AUTOOUTPUT mis-including genvars.
author Dan Nicolaescu <dann@ics.uci.edu>
date Wed, 19 Mar 2008 03:43:11 +0000
parents 89a7350a486f
children
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source ^subdirs\.el$

# arch-tag: 01b87183-9d94-4b6b-93cb-fece25c4eec9