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* progmodes/verilog-mode.el (verilog-mode-map): Fix typo.
author Dan Nicolaescu <dann@ics.uci.edu>
date Sat, 08 Dec 2007 19:59:24 +0000
parents 695cf19ef79e
children 375f2633d815
line wrap: on
line source

#include "bsd4-3.h"

/* Inhibit using -X, which is the default.  */
#define LD_SWITCH_SYSTEM

/* arch-tag: 08941c4f-d0b6-4ad6-b7e3-7e7fe76c0e94
   (do not change this comment) */