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(verilog-mode): Avoid circular use of syntax-ppss.
author Stefan Monnier <monnier@iro.umontreal.ca>
date Thu, 12 Feb 2009 05:34:26 +0000
parents ff8710d1c6c7
children 8476a21754a6
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*.aux
*.fn
*.fns
*.cps
*.cp
*.kys
*.ky
*.toc
*.pgs
*.pg
*.log
*.vrs
*.vr
*.dvi
*.ps
*.tp
*.tps
*.tmp
*.txt
Makefile
makefile