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(verilog-mode): Avoid circular use of syntax-ppss.
author Stefan Monnier <monnier@iro.umontreal.ca>
date Thu, 12 Feb 2009 05:34:26 +0000
parents a7180fd488bb
children 762408a9ef5d
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*.elc

# arch-tag: 652dce56-7a2f-46ff-8699-c3289ccdc165