# HG changeset patch # User Dan Nicolaescu # Date 1203570931 0 # Node ID 97019d686b43cedb450da3779b7e70be2c7f493f # Parent 3e4f6980296da30eb8231e9c3d335ba17196822d * progmodes/verilog-mode.el (verilog-xemacs-menu): Remove XEmacs conditional. (verilog-font-grouping-keywords-face): Make the begin..end keywords standout more than other verilog keywords. (verilog-type-font-keywords): Move the begin..end out of this list to facilitate making them to (potentially) stand out more. (verilog-backward-token): Fix indent of bare always{_*}?, initial, function & task blocks. (verilog-behavioral-block-beg-re): Fix indent of bare always{_*}?, initial, function & task blocks. (verilog-forward-sexp): Handle the new "disable fork" statement of IEEE-1800 Verilog. (verilog-beg-block-re-ordered): Handle the new "disable fork" statement of IEEE-1800 Verilog. (verilog-calc-1): Handle the new "disable fork" statement of IEEE-1800 Verilog. (verilog-disable-fork-re): Add const to help handle the new "disable fork" statement of IEEE-1800 Verilog. (verilog-declaration-core-re): Add port directions by themselves, with no qualification, as base item of a declaration. (verilog-pretty-declarations): Add new flag to ask it to refrain from printing to the message buffer. (verilog-pretty-expr): Add a QUIET flag to ask it to refrain from printing to the message buffer. Improve handling of the many types of expression line up. (verilog-just-one-space): Remove printing of an empty message. (verilog-get-lineup-indent): Rework to support the better handling of expression lineup for verilog-pretty-expr. (verilog-auto-wire): Pass the quiet flag to verilog-pretty-expr. diff -r 3e4f6980296d -r 97019d686b43 lisp/ChangeLog --- a/lisp/ChangeLog Wed Feb 20 22:18:28 2008 +0000 +++ b/lisp/ChangeLog Thu Feb 21 05:15:31 2008 +0000 @@ -1,3 +1,35 @@ +2008-02-21 Michael McNamara + + * progmodes/verilog-mode.el (verilog-xemacs-menu): Remove XEmacs + conditional. + (verilog-font-grouping-keywords-face): Make the begin..end + keywords standout more than other verilog keywords. + (verilog-type-font-keywords): Move the begin..end out of this list + to facilitate making them to (potentially) stand out more. + (verilog-backward-token): Fix indent of bare always{_*}?, initial, + function & task blocks. + (verilog-behavioral-block-beg-re): Fix indent of bare always{_*}?, + initial, function & task blocks. + (verilog-forward-sexp): Handle the new "disable fork" statement of + IEEE-1800 Verilog. + (verilog-beg-block-re-ordered): Handle the new "disable fork" + statement of IEEE-1800 Verilog. + (verilog-calc-1): Handle the new "disable fork" statement of + IEEE-1800 Verilog. + (verilog-disable-fork-re): Add const to help handle the new + "disable fork" statement of IEEE-1800 Verilog. + (verilog-declaration-core-re): Add port directions by themselves, + with no qualification, as base item of a declaration. + (verilog-pretty-declarations): Add new flag to ask it to refrain + from printing to the message buffer. + (verilog-pretty-expr): Add a QUIET flag to ask it to refrain from + printing to the message buffer. Improve handling of the many + types of expression line up. + (verilog-just-one-space): Remove printing of an empty message. + (verilog-get-lineup-indent): Rework to support the better handling + of expression lineup for verilog-pretty-expr. + (verilog-auto-wire): Pass the quiet flag to verilog-pretty-expr. + 2008-02-20 Alan Mackenzie * progmodes/cc-mode.el (c-extend-region-for-CPP): Bug fix from diff -r 3e4f6980296d -r 97019d686b43 lisp/progmodes/verilog-mode.el --- a/lisp/progmodes/verilog-mode.el Wed Feb 20 22:18:28 2008 +0000 +++ b/lisp/progmodes/verilog-mode.el Thu Feb 21 05:15:31 2008 +0000 @@ -115,9 +115,9 @@ ;;; Code: ;; This variable will always hold the version number of the mode -(defconst verilog-mode-version "389" +(defconst verilog-mode-version "399" "Version of this Verilog mode.") -(defconst verilog-mode-release-date "2008-02-01-GNU" +(defconst verilog-mode-release-date "2008-02-19-GNU" "Release date of this Verilog mode.") (defconst verilog-mode-release-emacs t "If non-nil, this version of Verilog mode was released with Emacs itself.") @@ -992,15 +992,9 @@ :selected (equal verilog-tool `verilog-compiler)] ) ("Move" - ,(if (featurep 'xemacs) - (progn - ["Beginning of function" verilog-beg-of-defun t] - ["End of function" verilog-end-of-defun t] - ["Mark function" verilog-mark-defun t]) - ["Beginning of function" beginning-of-defun t] - ["End of function" end-of-defun t] - ["Mark function" mark-defun t]) - + ["Beginning of function" verilog-beg-of-defun t] + ["End of function" verilog-end-of-defun t] + ["Mark function" verilog-mark-defun t] ["Goto function/module" verilog-goto-defun t] ["Move to beginning of block" electric-verilog-backward-sexp t] ["Move to end of block" electric-verilog-forward-sexp t] @@ -1451,19 +1445,18 @@ (defconst verilog-beg-block-re-ordered ( concat "\\<" "\\(begin\\)" ;1 - "\\|\\(randcase\\|\\(unique\\s-+\\|priority\\s-+\\)?case[xz]?\\)" ; 2 -;; "\\|\\(randcase\\|case[xz]?\\)" ; 2 - "\\|\\(fork\\)" ;3 - "\\|\\(class\\)" ;4 - "\\|\\(table\\)" ;5 - "\\|\\(specify\\)" ;6 - "\\|\\(function\\)" ;7 - "\\|\\(task\\)" ;8 - "\\|\\(generate\\)" ;9 - "\\|\\(covergroup\\)" ;10 - "\\|\\(property\\)" ;11 - "\\|\\(\\(rand\\)?sequence\\)" ;12 - "\\|\\(clocking\\)" ;13 + "\\|\\(randcase\\|\\(unique\\s-+\\|priority\\s-+\\)?case[xz]?\\)" ; 2,3 + "\\|\\(\\(disable\\s-+\\)?fork\\)" ;4 + "\\|\\(class\\)" ;5 + "\\|\\(table\\)" ;6 + "\\|\\(specify\\)" ;7 + "\\|\\(function\\)" ;8 + "\\|\\(task\\)" ;9 + "\\|\\(generate\\)" ;10 + "\\|\\(covergroup\\)" ;11 + "\\|\\(property\\)" ;12 + "\\|\\(\\(rand\\)?sequence\\)" ;13 + "\\|\\(clocking\\)" ;14 "\\>")) (defconst verilog-end-block-ordered-rry @@ -1574,8 +1567,8 @@ (concat verilog-defun-re "\\|" verilog-end-defun-re)) (defconst verilog-behavioral-block-beg-re - (concat "\\(\\\\|\\\\|\\\\|\\\\|\\\\|" - "\\\\|\\\\|\\\\)")) + (eval-when-compile (verilog-regexp-words `("initial" "final" "always" "always_comb" "always_latch" "always_ff" + "function" "task")))) (defconst verilog-indent-re (eval-when-compile @@ -1640,6 +1633,7 @@ `( "endmodule" "endprimitive" "endinterface" "endpackage" "endprogram" "endclass" )))) +(defconst verilog-disable-fork-re "disable\\s-+fork") (defconst verilog-extended-case-re "\\(unique\\s-+\\|priority\\s-+\\)?case[xz]?") (defconst verilog-extended-complete-re (concat "\\(\\\\|\\\\)" @@ -1815,6 +1809,20 @@ "Font lock mode face used to highlight AMS keywords." :group 'font-lock-highlighting-faces) +(defvar verilog-font-grouping-keywords-face + 'verilog-font-lock-grouping-keywords-face + "Font to use for Verilog Grouping Keywords (such as begin..end).") +(defface verilog-font-lock-grouping-keywords-face + '((((class color) + (background light)) + (:foreground "red4" :bold t )) + (((class color) + (background dark)) + (:foreground "red4" :bold t )) + (t (:italic t))) + "Font lock mode face used to highlight verilog grouping keywords." + :group 'font-lock-highlighting-faces) + (let* ((verilog-type-font-keywords (eval-when-compile (verilog-regexp-opt @@ -1879,8 +1887,8 @@ (eval-when-compile (verilog-regexp-opt '( - "assign" "begin" "case" "casex" "casez" "randcase" "deassign" - "default" "disable" "else" "end" "endcase" "endfunction" + "assign" "case" "casex" "casez" "randcase" "deassign" + "default" "disable" "else" "endcase" "endfunction" "endgenerate" "endinterface" "endmodule" "endprimitive" "endspecify" "endtable" "endtask" "final" "for" "force" "return" "break" "continue" "forever" "fork" "function" "generate" "if" "iff" "initial" @@ -1889,7 +1897,12 @@ "always_latch" "posedge" "primitive" "priority" "release" "repeat" "specify" "table" "task" "unique" "wait" "while" "class" "program" "endclass" "endprogram" - ) nil )))) + ) nil ))) + + (verilog-font-grouping-keywords + (eval-when-compile + (verilog-regexp-opt + '( "begin" "end" ) nil )))) (setq verilog-font-lock-keywords (list @@ -1899,7 +1912,9 @@ "\\$[a-zA-Z][a-zA-Z0-9_\\$]*" "\\)\\>") ;; Fontify all types - (cons (concat "\\<\\(" verilog-type-font-keywords "\\)\\>") + (cons (concat "\\(\\<" verilog-font-grouping-keywords "\\)\\>") + 'verilog-font-lock-ams-face) + (cons (concat "\\<\\(" verilog-type-font-keywords "\\)\\>") 'font-lock-type-face) ;; Fontify IEEE-P1800 keywords appropriately (if verilog-highlight-p1800-keywords @@ -2066,49 +2081,64 @@ (cond ((verilog-skip-forward-comment-or-string) (verilog-forward-syntactic-ws)) - ((looking-at verilog-beg-block-re-ordered);; begin|case|fork|class|table|specify|function|task|generate|covergroup|property|sequence|clocking + ((looking-at verilog-beg-block-re-ordered) ;; begin|(case)|xx|(fork)|class|table|specify|function|task|generate|covergroup|property|sequence|clocking (cond ((match-end 1) ; end ;; Search forward for matching begin (setq reg "\\(\\\\)\\|\\(\\\\)" )) ((match-end 2) ; endcase ;; Search forward for matching case - (setq reg "\\(\\\\|\\(\\\\s-+\\|\\\\s-+\\)?\\[^:]\\)\\|\\(\\\\)" )) - ((match-end 3) ; join - ;; Search forward for matching fork - (setq reg "\\(\\\\)\\|\\(\\\\)" )) - ((match-end 4) ; endclass + (setq reg "\\(\\\\|\\(\\\\s-+\\|\\\\s-+\\)?\\[^:]\\)\\|\\(\\\\)" ) + (setq md 3) ;; ender is third item in regexp + ) + ((match-end 4) ; join + ;; might be "disable fork" + (if (or + (looking-at verilog-disable-fork-re) + (and (looking-at "fork") + (progn + (forward-word -1) + (looking-at verilog-disable-fork-re)))) + (progn + (goto-char (match-end 0)) + (forward-word) + (setq reg nil)) + (progn + ;; Search forward for matching fork + (setq reg "\\(\\\\)\\|\\(\\\\)" )))) + ((match-end 5) ; endclass ;; Search forward for matching class (setq reg "\\(\\\\)\\|\\(\\\\)" )) - ((match-end 5) ; endtable + ((match-end 6) ; endtable ;; Search forward for matching table (setq reg "\\(\\\\)\\|\\(\\\\)" )) - ((match-end 6) ; endspecify + ((match-end 7) ; endspecify ;; Search forward for matching specify (setq reg "\\(\\\\)\\|\\(\\\\)" )) - ((match-end 7) ; endfunction + ((match-end 8) ; endfunction ;; Search forward for matching function (setq reg "\\(\\\\)\\|\\(\\\\)" )) - ((match-end 8) ; endtask + ((match-end 9) ; endtask ;; Search forward for matching task (setq reg "\\(\\\\)\\|\\(\\\\)" )) - ((match-end 9) ; endgenerate + ((match-end 10) ; endgenerate ;; Search forward for matching generate (setq reg "\\(\\\\)\\|\\(\\\\)" )) - ((match-end 10) ; endgroup + ((match-end 11) ; endgroup ;; Search forward for matching covergroup (setq reg "\\(\\\\)\\|\\(\\\\)" )) - ((match-end 11) ; endproperty + ((match-end 12) ; endproperty ;; Search forward for matching property (setq reg "\\(\\\\)\\|\\(\\\\)" )) - ((match-end 12) ; endsequence + ((match-end 13) ; endsequence ;; Search forward for matching sequence (setq reg "\\(\\<\\(rand\\)?sequence\\>\\)\\|\\(\\\\)" ) (setq md 3)) ; 3 to get to endsequence in the reg above - ((match-end 13) ; endclocking + ((match-end 14) ; endclocking ;; Search forward for matching clocking (setq reg "\\(\\\\)\\|\\(\\\\)" ))) - (if (forward-word 1) + (if (and reg + (forward-word 1)) (catch 'skip (let ((nest 1)) (while (verilog-re-search-forward reg nil 'move) @@ -3934,6 +3964,16 @@ (throw 'nesting 'case) (goto-char here))) (throw 'nesting 'case)) + + ((match-end 4) ; *sigh* could be "disable fork" + (let ((here (point))) + (verilog-beg-of-statement) + (if (looking-at verilog-disable-fork-re) + t ; is disable fork, this is a normal statement + (progn ; or is fork, starts a new block + (goto-char here) + (throw 'nesting 'block))))) + ;; need to consider typedef struct here... ((looking-at "\\") @@ -4169,6 +4209,8 @@ (cond ((looking-at "\\") t) + ((looking-at verilog-behavioral-block-beg-re) + t) ((looking-at verilog-indent-re) nil) (t