annotate arm/dsputil_armv6.S @ 11386:0262869c11a9 libavcodec

Band quant tables should not be assigned inside band tile loop, one time is enough. Patch by Maxim (max_pole, gmx de)
author kostya
date Sun, 07 Mar 2010 12:12:42 +0000
parents cbf3161706f4
children 361a5fcb4393
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1 /*
e55d957ef1a2 ARM: ARMv6 optimised add_pixels_clamped()
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2 * Copyright (c) 2009 Mans Rullgard <mans@mansr.com>
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3 *
e55d957ef1a2 ARM: ARMv6 optimised add_pixels_clamped()
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4 * This file is part of FFmpeg.
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5 *
e55d957ef1a2 ARM: ARMv6 optimised add_pixels_clamped()
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6 * FFmpeg is free software; you can redistribute it and/or
e55d957ef1a2 ARM: ARMv6 optimised add_pixels_clamped()
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7 * modify it under the terms of the GNU Lesser General Public
e55d957ef1a2 ARM: ARMv6 optimised add_pixels_clamped()
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8 * License as published by the Free Software Foundation; either
e55d957ef1a2 ARM: ARMv6 optimised add_pixels_clamped()
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9 * version 2.1 of the License, or (at your option) any later version.
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10 *
e55d957ef1a2 ARM: ARMv6 optimised add_pixels_clamped()
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11 * FFmpeg is distributed in the hope that it will be useful,
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12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
e55d957ef1a2 ARM: ARMv6 optimised add_pixels_clamped()
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14 * Lesser General Public License for more details.
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15 *
e55d957ef1a2 ARM: ARMv6 optimised add_pixels_clamped()
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16 * You should have received a copy of the GNU Lesser General Public
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17 * License along with FFmpeg; if not, write to the Free Software
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18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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19 */
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20
e55d957ef1a2 ARM: ARMv6 optimised add_pixels_clamped()
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21 #include "asm.S"
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22
11241
cbf3161706f4 ARM: add missing preserve8 directives
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23 preserve8
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24
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e55d957ef1a2 ARM: ARMv6 optimised add_pixels_clamped()
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25 .text
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26
11108
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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27 .macro call_2x_pixels type, subp
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28 function ff_\type\()_pixels16\subp\()_armv6, export=1
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29 push {r0-r3, lr}
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30 bl ff_\type\()_pixels8\subp\()_armv6
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31 pop {r0-r3, lr}
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32 add r0, r0, #8
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33 add r1, r1, #8
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34 b ff_\type\()_pixels8\subp\()_armv6
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35 .endfunc
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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36 .endm
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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37
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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38 call_2x_pixels avg
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39 call_2x_pixels put, _x2
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40 call_2x_pixels put, _y2
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41 call_2x_pixels put, _x2_no_rnd
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42 call_2x_pixels put, _y2_no_rnd
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43
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44 function ff_put_pixels16_armv6, export=1
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45 push {r4-r11}
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46 1:
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47 ldr r5, [r1, #4]
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48 ldr r6, [r1, #8]
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49 ldr r7, [r1, #12]
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50 ldr r4, [r1], r2
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51 strd r6, r7, [r0, #8]
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52 ldr r9, [r1, #4]
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53 strd r4, r5, [r0], r2
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54 ldr r10, [r1, #8]
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55 ldr r11, [r1, #12]
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56 ldr r8, [r1], r2
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57 strd r10, r11, [r0, #8]
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58 subs r3, r3, #2
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59 strd r8, r9, [r0], r2
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60 bne 1b
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61
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62 pop {r4-r11}
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63 bx lr
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64 .endfunc
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65
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66 function ff_put_pixels8_armv6, export=1
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67 push {r4-r7}
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68 1:
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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69 ldr r5, [r1, #4]
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70 ldr r4, [r1], r2
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71 ldr r7, [r1, #4]
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72 strd r4, r5, [r0], r2
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73 ldr r6, [r1], r2
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74 subs r3, r3, #2
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75 strd r6, r7, [r0], r2
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76 bne 1b
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77
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78 pop {r4-r7}
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79 bx lr
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80 .endfunc
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81
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82 function ff_put_pixels8_x2_armv6, export=1
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83 push {r4-r11, lr}
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84 mov r12, #1
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85 orr r12, r12, r12, lsl #8
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86 orr r12, r12, r12, lsl #16
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87 1:
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88 ldr r4, [r1]
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89 subs r3, r3, #2
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90 ldr r5, [r1, #4]
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91 ldr r7, [r1, #5]
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92 lsr r6, r4, #8
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93 ldr r8, [r1, r2]!
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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94 orr r6, r6, r5, lsl #24
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95 ldr r9, [r1, #4]
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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96 ldr r11, [r1, #5]
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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97 lsr r10, r8, #8
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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98 add r1, r1, r2
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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99 orr r10, r10, r9, lsl #24
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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100 eor r14, r4, r6
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101 uhadd8 r4, r4, r6
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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102 eor r6, r5, r7
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103 uhadd8 r5, r5, r7
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104 and r14, r14, r12
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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105 and r6, r6, r12
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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106 uadd8 r4, r4, r14
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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107 eor r14, r8, r10
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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108 uadd8 r5, r5, r6
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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109 eor r6, r9, r11
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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110 uhadd8 r8, r8, r10
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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111 and r14, r14, r12
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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112 uhadd8 r9, r9, r11
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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113 and r6, r6, r12
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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114 uadd8 r8, r8, r14
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115 strd r4, r5, [r0], r2
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116 uadd8 r9, r9, r6
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117 strd r8, r9, [r0], r2
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118 bne 1b
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119
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120 pop {r4-r11, pc}
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121 .endfunc
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122
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123 function ff_put_pixels8_y2_armv6, export=1
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124 push {r4-r11}
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125 mov r12, #1
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126 orr r12, r12, r12, lsl #8
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127 orr r12, r12, r12, lsl #16
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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128 ldr r4, [r1]
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129 ldr r5, [r1, #4]
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130 ldr r6, [r1, r2]!
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131 ldr r7, [r1, #4]
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132 1:
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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133 subs r3, r3, #2
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134 uhadd8 r8, r4, r6
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135 eor r10, r4, r6
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136 uhadd8 r9, r5, r7
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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137 eor r11, r5, r7
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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138 and r10, r10, r12
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139 ldr r4, [r1, r2]!
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140 uadd8 r8, r8, r10
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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141 and r11, r11, r12
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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142 uadd8 r9, r9, r11
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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143 ldr r5, [r1, #4]
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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144 uhadd8 r10, r4, r6
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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145 eor r6, r4, r6
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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146 uhadd8 r11, r5, r7
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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147 and r6, r6, r12
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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148 eor r7, r5, r7
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149 uadd8 r10, r10, r6
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150 and r7, r7, r12
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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151 ldr r6, [r1, r2]!
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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152 uadd8 r11, r11, r7
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153 strd r8, r9, [r0], r2
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diff changeset
154 ldr r7, [r1, #4]
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
155 strd r10, r11, [r0], r2
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
156 bne 1b
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
157
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
158 pop {r4-r11}
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
159 bx lr
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
160 .endfunc
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
161
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
162 function ff_put_pixels8_x2_no_rnd_armv6, export=1
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
163 push {r4-r9, lr}
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
164 1:
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
165 subs r3, r3, #2
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
166 ldr r4, [r1]
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
167 ldr r5, [r1, #4]
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
168 ldr r7, [r1, #5]
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
169 ldr r8, [r1, r2]!
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
170 ldr r9, [r1, #4]
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
171 ldr r14, [r1, #5]
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
172 add r1, r1, r2
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
173 lsr r6, r4, #8
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
174 orr r6, r6, r5, lsl #24
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
175 lsr r12, r8, #8
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
176 orr r12, r12, r9, lsl #24
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
177 uhadd8 r4, r4, r6
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
178 uhadd8 r5, r5, r7
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
179 uhadd8 r8, r8, r12
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
180 uhadd8 r9, r9, r14
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
181 stm r0, {r4,r5}
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
182 add r0, r0, r2
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
183 stm r0, {r8,r9}
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
184 add r0, r0, r2
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
185 bne 1b
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
186
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
187 pop {r4-r9, pc}
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
188 .endfunc
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
189
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
190 function ff_put_pixels8_y2_no_rnd_armv6, export=1
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
191 push {r4-r9, lr}
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
192 ldr r4, [r1]
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
193 ldr r5, [r1, #4]
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
194 ldr r6, [r1, r2]!
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
195 ldr r7, [r1, #4]
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
196 1:
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
197 subs r3, r3, #2
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
198 uhadd8 r8, r4, r6
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
199 ldr r4, [r1, r2]!
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
200 uhadd8 r9, r5, r7
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
201 ldr r5, [r1, #4]
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
202 uhadd8 r12, r4, r6
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
203 ldr r6, [r1, r2]!
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
204 uhadd8 r14, r5, r7
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
205 ldr r7, [r1, #4]
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
206 stm r0, {r8,r9}
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
207 add r0, r0, r2
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
208 stm r0, {r12,r14}
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
209 add r0, r0, r2
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
210 bne 1b
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
211
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
212 pop {r4-r9, pc}
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
213 .endfunc
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
214
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
215 function ff_avg_pixels8_armv6, export=1
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
216 pld [r1, r2]
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
217 push {r4-r10, lr}
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
218 mov lr, #1
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
219 orr lr, lr, lr, lsl #8
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
220 orr lr, lr, lr, lsl #16
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
221 ldrd r4, r5, [r0]
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
222 ldr r10, [r1, #4]
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
223 ldr r9, [r1], r2
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
224 subs r3, r3, #2
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
225 1:
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
226 pld [r1, r2]
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
227 eor r8, r4, r9
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
228 uhadd8 r4, r4, r9
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
229 eor r12, r5, r10
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
230 ldrd r6, r7, [r0, r2]
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
231 uhadd8 r5, r5, r10
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
232 and r8, r8, lr
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
233 ldr r10, [r1, #4]
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
234 and r12, r12, lr
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
235 uadd8 r4, r4, r8
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
236 ldr r9, [r1], r2
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
237 eor r8, r6, r9
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
238 uadd8 r5, r5, r12
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
239 pld [r1, r2, lsl #1]
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
240 eor r12, r7, r10
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
241 uhadd8 r6, r6, r9
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
242 strd r4, r5, [r0], r2
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
243 uhadd8 r7, r7, r10
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
244 beq 2f
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
245 and r8, r8, lr
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
246 ldrd r4, r5, [r0, r2]
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
247 uadd8 r6, r6, r8
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
248 ldr r10, [r1, #4]
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
249 and r12, r12, lr
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
250 subs r3, r3, #2
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
251 uadd8 r7, r7, r12
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
252 ldr r9, [r1], r2
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
253 strd r6, r7, [r0], r2
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
254 b 1b
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
255 2:
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
256 and r8, r8, lr
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
257 and r12, r12, lr
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
258 uadd8 r6, r6, r8
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
259 uadd8 r7, r7, r12
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
260 strd r6, r7, [r0], r2
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
261
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
262 pop {r4-r10, pc}
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
263 .endfunc
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
264
10372
e55d957ef1a2 ARM: ARMv6 optimised add_pixels_clamped()
mru
parents:
diff changeset
265 function ff_add_pixels_clamped_armv6, export=1
e55d957ef1a2 ARM: ARMv6 optimised add_pixels_clamped()
mru
parents:
diff changeset
266 push {r4-r8,lr}
e55d957ef1a2 ARM: ARMv6 optimised add_pixels_clamped()
mru
parents:
diff changeset
267 mov r3, #8
e55d957ef1a2 ARM: ARMv6 optimised add_pixels_clamped()
mru
parents:
diff changeset
268 1:
e55d957ef1a2 ARM: ARMv6 optimised add_pixels_clamped()
mru
parents:
diff changeset
269 ldm r0!, {r4,r5,r12,lr}
e55d957ef1a2 ARM: ARMv6 optimised add_pixels_clamped()
mru
parents:
diff changeset
270 ldrd r6, r7, [r1]
e55d957ef1a2 ARM: ARMv6 optimised add_pixels_clamped()
mru
parents:
diff changeset
271 pkhbt r8, r4, r5, lsl #16
e55d957ef1a2 ARM: ARMv6 optimised add_pixels_clamped()
mru
parents:
diff changeset
272 pkhtb r5, r5, r4, asr #16
e55d957ef1a2 ARM: ARMv6 optimised add_pixels_clamped()
mru
parents:
diff changeset
273 pkhbt r4, r12, lr, lsl #16
e55d957ef1a2 ARM: ARMv6 optimised add_pixels_clamped()
mru
parents:
diff changeset
274 pkhtb lr, lr, r12, asr #16
e55d957ef1a2 ARM: ARMv6 optimised add_pixels_clamped()
mru
parents:
diff changeset
275 pld [r1, r2]
e55d957ef1a2 ARM: ARMv6 optimised add_pixels_clamped()
mru
parents:
diff changeset
276 uxtab16 r8, r8, r6
e55d957ef1a2 ARM: ARMv6 optimised add_pixels_clamped()
mru
parents:
diff changeset
277 uxtab16 r5, r5, r6, ror #8
e55d957ef1a2 ARM: ARMv6 optimised add_pixels_clamped()
mru
parents:
diff changeset
278 uxtab16 r4, r4, r7
e55d957ef1a2 ARM: ARMv6 optimised add_pixels_clamped()
mru
parents:
diff changeset
279 uxtab16 lr, lr, r7, ror #8
e55d957ef1a2 ARM: ARMv6 optimised add_pixels_clamped()
mru
parents:
diff changeset
280 usat16 r8, #8, r8
e55d957ef1a2 ARM: ARMv6 optimised add_pixels_clamped()
mru
parents:
diff changeset
281 usat16 r5, #8, r5
e55d957ef1a2 ARM: ARMv6 optimised add_pixels_clamped()
mru
parents:
diff changeset
282 usat16 r4, #8, r4
e55d957ef1a2 ARM: ARMv6 optimised add_pixels_clamped()
mru
parents:
diff changeset
283 usat16 lr, #8, lr
e55d957ef1a2 ARM: ARMv6 optimised add_pixels_clamped()
mru
parents:
diff changeset
284 orr r6, r8, r5, lsl #8
e55d957ef1a2 ARM: ARMv6 optimised add_pixels_clamped()
mru
parents:
diff changeset
285 orr r7, r4, lr, lsl #8
e55d957ef1a2 ARM: ARMv6 optimised add_pixels_clamped()
mru
parents:
diff changeset
286 subs r3, r3, #1
e55d957ef1a2 ARM: ARMv6 optimised add_pixels_clamped()
mru
parents:
diff changeset
287 strd r6, r7, [r1], r2
e55d957ef1a2 ARM: ARMv6 optimised add_pixels_clamped()
mru
parents:
diff changeset
288 bgt 1b
e55d957ef1a2 ARM: ARMv6 optimised add_pixels_clamped()
mru
parents:
diff changeset
289 pop {r4-r8,pc}
e55d957ef1a2 ARM: ARMv6 optimised add_pixels_clamped()
mru
parents:
diff changeset
290 .endfunc
11109
9f00412b0bc8 ARMv6 optimised pix_abs16
mru
parents: 11108
diff changeset
291
11113
b529129c4563 ARMv6 optimised get_pixels
mru
parents: 11112
diff changeset
292 function ff_get_pixels_armv6, export=1
b529129c4563 ARMv6 optimised get_pixels
mru
parents: 11112
diff changeset
293 pld [r1, r2]
b529129c4563 ARMv6 optimised get_pixels
mru
parents: 11112
diff changeset
294 push {r4-r8, lr}
b529129c4563 ARMv6 optimised get_pixels
mru
parents: 11112
diff changeset
295 mov lr, #8
b529129c4563 ARMv6 optimised get_pixels
mru
parents: 11112
diff changeset
296 1:
b529129c4563 ARMv6 optimised get_pixels
mru
parents: 11112
diff changeset
297 ldrd r4, r5, [r1], r2
b529129c4563 ARMv6 optimised get_pixels
mru
parents: 11112
diff changeset
298 subs lr, lr, #1
b529129c4563 ARMv6 optimised get_pixels
mru
parents: 11112
diff changeset
299 uxtb16 r6, r4
b529129c4563 ARMv6 optimised get_pixels
mru
parents: 11112
diff changeset
300 uxtb16 r4, r4, ror #8
b529129c4563 ARMv6 optimised get_pixels
mru
parents: 11112
diff changeset
301 uxtb16 r12, r5
b529129c4563 ARMv6 optimised get_pixels
mru
parents: 11112
diff changeset
302 uxtb16 r8, r5, ror #8
b529129c4563 ARMv6 optimised get_pixels
mru
parents: 11112
diff changeset
303 pld [r1, r2]
b529129c4563 ARMv6 optimised get_pixels
mru
parents: 11112
diff changeset
304 pkhbt r5, r6, r4, lsl #16
b529129c4563 ARMv6 optimised get_pixels
mru
parents: 11112
diff changeset
305 pkhtb r6, r4, r6, asr #16
b529129c4563 ARMv6 optimised get_pixels
mru
parents: 11112
diff changeset
306 pkhbt r7, r12, r8, lsl #16
b529129c4563 ARMv6 optimised get_pixels
mru
parents: 11112
diff changeset
307 pkhtb r12, r8, r12, asr #16
b529129c4563 ARMv6 optimised get_pixels
mru
parents: 11112
diff changeset
308 stm r0!, {r5,r6,r7,r12}
b529129c4563 ARMv6 optimised get_pixels
mru
parents: 11112
diff changeset
309 bgt 1b
b529129c4563 ARMv6 optimised get_pixels
mru
parents: 11112
diff changeset
310
b529129c4563 ARMv6 optimised get_pixels
mru
parents: 11112
diff changeset
311 pop {r4-r8, pc}
b529129c4563 ARMv6 optimised get_pixels
mru
parents: 11112
diff changeset
312 .endfunc
b529129c4563 ARMv6 optimised get_pixels
mru
parents: 11112
diff changeset
313
11114
852772c36cc6 ARMv6 optimised diff_pixels
mru
parents: 11113
diff changeset
314 function ff_diff_pixels_armv6, export=1
852772c36cc6 ARMv6 optimised diff_pixels
mru
parents: 11113
diff changeset
315 pld [r1, r3]
852772c36cc6 ARMv6 optimised diff_pixels
mru
parents: 11113
diff changeset
316 pld [r2, r3]
852772c36cc6 ARMv6 optimised diff_pixels
mru
parents: 11113
diff changeset
317 push {r4-r9, lr}
852772c36cc6 ARMv6 optimised diff_pixels
mru
parents: 11113
diff changeset
318 mov lr, #8
852772c36cc6 ARMv6 optimised diff_pixels
mru
parents: 11113
diff changeset
319 1:
852772c36cc6 ARMv6 optimised diff_pixels
mru
parents: 11113
diff changeset
320 ldrd r4, r5, [r1], r3
852772c36cc6 ARMv6 optimised diff_pixels
mru
parents: 11113
diff changeset
321 ldrd r6, r7, [r2], r3
852772c36cc6 ARMv6 optimised diff_pixels
mru
parents: 11113
diff changeset
322 uxtb16 r8, r4
852772c36cc6 ARMv6 optimised diff_pixels
mru
parents: 11113
diff changeset
323 uxtb16 r4, r4, ror #8
852772c36cc6 ARMv6 optimised diff_pixels
mru
parents: 11113
diff changeset
324 uxtb16 r9, r6
852772c36cc6 ARMv6 optimised diff_pixels
mru
parents: 11113
diff changeset
325 uxtb16 r6, r6, ror #8
852772c36cc6 ARMv6 optimised diff_pixels
mru
parents: 11113
diff changeset
326 pld [r1, r3]
852772c36cc6 ARMv6 optimised diff_pixels
mru
parents: 11113
diff changeset
327 ssub16 r9, r8, r9
852772c36cc6 ARMv6 optimised diff_pixels
mru
parents: 11113
diff changeset
328 ssub16 r6, r4, r6
852772c36cc6 ARMv6 optimised diff_pixels
mru
parents: 11113
diff changeset
329 uxtb16 r8, r5
852772c36cc6 ARMv6 optimised diff_pixels
mru
parents: 11113
diff changeset
330 uxtb16 r5, r5, ror #8
852772c36cc6 ARMv6 optimised diff_pixels
mru
parents: 11113
diff changeset
331 pld [r2, r3]
852772c36cc6 ARMv6 optimised diff_pixels
mru
parents: 11113
diff changeset
332 pkhbt r4, r9, r6, lsl #16
852772c36cc6 ARMv6 optimised diff_pixels
mru
parents: 11113
diff changeset
333 pkhtb r6, r6, r9, asr #16
852772c36cc6 ARMv6 optimised diff_pixels
mru
parents: 11113
diff changeset
334 uxtb16 r9, r7
852772c36cc6 ARMv6 optimised diff_pixels
mru
parents: 11113
diff changeset
335 uxtb16 r7, r7, ror #8
852772c36cc6 ARMv6 optimised diff_pixels
mru
parents: 11113
diff changeset
336 ssub16 r9, r8, r9
852772c36cc6 ARMv6 optimised diff_pixels
mru
parents: 11113
diff changeset
337 ssub16 r5, r5, r7
852772c36cc6 ARMv6 optimised diff_pixels
mru
parents: 11113
diff changeset
338 subs lr, lr, #1
852772c36cc6 ARMv6 optimised diff_pixels
mru
parents: 11113
diff changeset
339 pkhbt r8, r9, r5, lsl #16
852772c36cc6 ARMv6 optimised diff_pixels
mru
parents: 11113
diff changeset
340 pkhtb r9, r5, r9, asr #16
852772c36cc6 ARMv6 optimised diff_pixels
mru
parents: 11113
diff changeset
341 stm r0!, {r4,r6,r8,r9}
852772c36cc6 ARMv6 optimised diff_pixels
mru
parents: 11113
diff changeset
342 bgt 1b
852772c36cc6 ARMv6 optimised diff_pixels
mru
parents: 11113
diff changeset
343
852772c36cc6 ARMv6 optimised diff_pixels
mru
parents: 11113
diff changeset
344 pop {r4-r9, pc}
852772c36cc6 ARMv6 optimised diff_pixels
mru
parents: 11113
diff changeset
345 .endfunc
852772c36cc6 ARMv6 optimised diff_pixels
mru
parents: 11113
diff changeset
346
11109
9f00412b0bc8 ARMv6 optimised pix_abs16
mru
parents: 11108
diff changeset
347 function ff_pix_abs16_armv6, export=1
9f00412b0bc8 ARMv6 optimised pix_abs16
mru
parents: 11108
diff changeset
348 ldr r0, [sp]
9f00412b0bc8 ARMv6 optimised pix_abs16
mru
parents: 11108
diff changeset
349 push {r4-r9, lr}
9f00412b0bc8 ARMv6 optimised pix_abs16
mru
parents: 11108
diff changeset
350 mov r12, #0
9f00412b0bc8 ARMv6 optimised pix_abs16
mru
parents: 11108
diff changeset
351 mov lr, #0
9f00412b0bc8 ARMv6 optimised pix_abs16
mru
parents: 11108
diff changeset
352 ldm r1, {r4-r7}
9f00412b0bc8 ARMv6 optimised pix_abs16
mru
parents: 11108
diff changeset
353 ldr r8, [r2]
9f00412b0bc8 ARMv6 optimised pix_abs16
mru
parents: 11108
diff changeset
354 1:
9f00412b0bc8 ARMv6 optimised pix_abs16
mru
parents: 11108
diff changeset
355 ldr r9, [r2, #4]
9f00412b0bc8 ARMv6 optimised pix_abs16
mru
parents: 11108
diff changeset
356 pld [r1, r3]
9f00412b0bc8 ARMv6 optimised pix_abs16
mru
parents: 11108
diff changeset
357 usada8 r12, r4, r8, r12
9f00412b0bc8 ARMv6 optimised pix_abs16
mru
parents: 11108
diff changeset
358 ldr r8, [r2, #8]
9f00412b0bc8 ARMv6 optimised pix_abs16
mru
parents: 11108
diff changeset
359 pld [r2, r3]
9f00412b0bc8 ARMv6 optimised pix_abs16
mru
parents: 11108
diff changeset
360 usada8 lr, r5, r9, lr
9f00412b0bc8 ARMv6 optimised pix_abs16
mru
parents: 11108
diff changeset
361 ldr r9, [r2, #12]
9f00412b0bc8 ARMv6 optimised pix_abs16
mru
parents: 11108
diff changeset
362 usada8 r12, r6, r8, r12
9f00412b0bc8 ARMv6 optimised pix_abs16
mru
parents: 11108
diff changeset
363 subs r0, r0, #1
9f00412b0bc8 ARMv6 optimised pix_abs16
mru
parents: 11108
diff changeset
364 usada8 lr, r7, r9, lr
9f00412b0bc8 ARMv6 optimised pix_abs16
mru
parents: 11108
diff changeset
365 beq 2f
9f00412b0bc8 ARMv6 optimised pix_abs16
mru
parents: 11108
diff changeset
366 add r1, r1, r3
9f00412b0bc8 ARMv6 optimised pix_abs16
mru
parents: 11108
diff changeset
367 ldm r1, {r4-r7}
9f00412b0bc8 ARMv6 optimised pix_abs16
mru
parents: 11108
diff changeset
368 add r2, r2, r3
9f00412b0bc8 ARMv6 optimised pix_abs16
mru
parents: 11108
diff changeset
369 ldr r8, [r2]
9f00412b0bc8 ARMv6 optimised pix_abs16
mru
parents: 11108
diff changeset
370 b 1b
9f00412b0bc8 ARMv6 optimised pix_abs16
mru
parents: 11108
diff changeset
371 2:
9f00412b0bc8 ARMv6 optimised pix_abs16
mru
parents: 11108
diff changeset
372 add r0, r12, lr
9f00412b0bc8 ARMv6 optimised pix_abs16
mru
parents: 11108
diff changeset
373 pop {r4-r9, pc}
9f00412b0bc8 ARMv6 optimised pix_abs16
mru
parents: 11108
diff changeset
374 .endfunc
11110
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
375
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
376 function ff_pix_abs16_x2_armv6, export=1
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
377 ldr r12, [sp]
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
378 push {r4-r11, lr}
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
379 mov r0, #0
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
380 mov lr, #1
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
381 orr lr, lr, lr, lsl #8
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
382 orr lr, lr, lr, lsl #16
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
383 1:
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
384 ldr r8, [r2]
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
385 ldr r9, [r2, #4]
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
386 lsr r10, r8, #8
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
387 ldr r4, [r1]
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
388 lsr r6, r9, #8
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
389 orr r10, r10, r9, lsl #24
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
390 ldr r5, [r2, #8]
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
391 eor r11, r8, r10
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
392 uhadd8 r7, r8, r10
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
393 orr r6, r6, r5, lsl #24
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
394 and r11, r11, lr
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
395 uadd8 r7, r7, r11
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
396 ldr r8, [r1, #4]
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
397 usada8 r0, r4, r7, r0
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
398 eor r7, r9, r6
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
399 lsr r10, r5, #8
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
400 and r7, r7, lr
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
401 uhadd8 r4, r9, r6
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
402 ldr r6, [r2, #12]
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
403 uadd8 r4, r4, r7
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
404 pld [r1, r3]
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
405 orr r10, r10, r6, lsl #24
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
406 usada8 r0, r8, r4, r0
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
407 ldr r4, [r1, #8]
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
408 eor r11, r5, r10
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
409 ldrb r7, [r2, #16]
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
410 and r11, r11, lr
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
411 uhadd8 r8, r5, r10
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
412 ldr r5, [r1, #12]
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
413 uadd8 r8, r8, r11
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
414 pld [r2, r3]
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
415 lsr r10, r6, #8
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
416 usada8 r0, r4, r8, r0
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
417 orr r10, r10, r7, lsl #24
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
418 subs r12, r12, #1
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
419 eor r11, r6, r10
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
420 add r1, r1, r3
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
421 uhadd8 r9, r6, r10
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
422 and r11, r11, lr
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
423 uadd8 r9, r9, r11
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
424 add r2, r2, r3
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
425 usada8 r0, r5, r9, r0
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
426 bgt 1b
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
427
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
428 pop {r4-r11, pc}
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
429 .endfunc
11111
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
430
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
431 .macro usad_y2 p0, p1, p2, p3, n0, n1, n2, n3
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
432 ldr \n0, [r2]
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
433 eor \n1, \p0, \n0
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
434 uhadd8 \p0, \p0, \n0
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
435 and \n1, \n1, lr
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
436 ldr \n2, [r1]
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
437 uadd8 \p0, \p0, \n1
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
438 ldr \n1, [r2, #4]
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
439 usada8 r0, \p0, \n2, r0
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
440 pld [r1, r3]
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
441 eor \n3, \p1, \n1
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
442 uhadd8 \p1, \p1, \n1
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
443 and \n3, \n3, lr
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
444 ldr \p0, [r1, #4]
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
445 uadd8 \p1, \p1, \n3
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
446 ldr \n2, [r2, #8]
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
447 usada8 r0, \p1, \p0, r0
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
448 pld [r2, r3]
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
449 eor \p0, \p2, \n2
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
450 uhadd8 \p2, \p2, \n2
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
451 and \p0, \p0, lr
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
452 ldr \p1, [r1, #8]
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
453 uadd8 \p2, \p2, \p0
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
454 ldr \n3, [r2, #12]
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
455 usada8 r0, \p2, \p1, r0
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
456 eor \p1, \p3, \n3
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
457 uhadd8 \p3, \p3, \n3
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
458 and \p1, \p1, lr
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
459 ldr \p0, [r1, #12]
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
460 uadd8 \p3, \p3, \p1
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
461 add r1, r1, r3
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
462 usada8 r0, \p3, \p0, r0
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
463 add r2, r2, r3
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
464 .endm
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
465
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
466 function ff_pix_abs16_y2_armv6, export=1
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
467 pld [r1]
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
468 pld [r2]
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
469 ldr r12, [sp]
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
470 push {r4-r11, lr}
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
471 mov r0, #0
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
472 mov lr, #1
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
473 orr lr, lr, lr, lsl #8
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
474 orr lr, lr, lr, lsl #16
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
475 ldr r4, [r2]
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
476 ldr r5, [r2, #4]
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
477 ldr r6, [r2, #8]
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
478 ldr r7, [r2, #12]
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
479 add r2, r2, r3
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
480 1:
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
481 usad_y2 r4, r5, r6, r7, r8, r9, r10, r11
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
482 subs r12, r12, #2
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
483 usad_y2 r8, r9, r10, r11, r4, r5, r6, r7
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
484 bgt 1b
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
485
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
486 pop {r4-r11, pc}
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
487 .endfunc
11112
ffe1ea72ea29 ARMv6 optimised pix_abs8
mru
parents: 11111
diff changeset
488
ffe1ea72ea29 ARMv6 optimised pix_abs8
mru
parents: 11111
diff changeset
489 function ff_pix_abs8_armv6, export=1
ffe1ea72ea29 ARMv6 optimised pix_abs8
mru
parents: 11111
diff changeset
490 pld [r2, r3]
ffe1ea72ea29 ARMv6 optimised pix_abs8
mru
parents: 11111
diff changeset
491 ldr r12, [sp]
ffe1ea72ea29 ARMv6 optimised pix_abs8
mru
parents: 11111
diff changeset
492 push {r4-r9, lr}
ffe1ea72ea29 ARMv6 optimised pix_abs8
mru
parents: 11111
diff changeset
493 mov r0, #0
ffe1ea72ea29 ARMv6 optimised pix_abs8
mru
parents: 11111
diff changeset
494 mov lr, #0
ffe1ea72ea29 ARMv6 optimised pix_abs8
mru
parents: 11111
diff changeset
495 ldrd r4, r5, [r1], r3
ffe1ea72ea29 ARMv6 optimised pix_abs8
mru
parents: 11111
diff changeset
496 1:
ffe1ea72ea29 ARMv6 optimised pix_abs8
mru
parents: 11111
diff changeset
497 subs r12, r12, #2
ffe1ea72ea29 ARMv6 optimised pix_abs8
mru
parents: 11111
diff changeset
498 ldr r7, [r2, #4]
ffe1ea72ea29 ARMv6 optimised pix_abs8
mru
parents: 11111
diff changeset
499 ldr r6, [r2], r3
ffe1ea72ea29 ARMv6 optimised pix_abs8
mru
parents: 11111
diff changeset
500 ldrd r8, r9, [r1], r3
ffe1ea72ea29 ARMv6 optimised pix_abs8
mru
parents: 11111
diff changeset
501 usada8 r0, r4, r6, r0
ffe1ea72ea29 ARMv6 optimised pix_abs8
mru
parents: 11111
diff changeset
502 pld [r2, r3]
ffe1ea72ea29 ARMv6 optimised pix_abs8
mru
parents: 11111
diff changeset
503 usada8 lr, r5, r7, lr
ffe1ea72ea29 ARMv6 optimised pix_abs8
mru
parents: 11111
diff changeset
504 ldr r7, [r2, #4]
ffe1ea72ea29 ARMv6 optimised pix_abs8
mru
parents: 11111
diff changeset
505 ldr r6, [r2], r3
ffe1ea72ea29 ARMv6 optimised pix_abs8
mru
parents: 11111
diff changeset
506 beq 2f
ffe1ea72ea29 ARMv6 optimised pix_abs8
mru
parents: 11111
diff changeset
507 ldrd r4, r5, [r1], r3
ffe1ea72ea29 ARMv6 optimised pix_abs8
mru
parents: 11111
diff changeset
508 usada8 r0, r8, r6, r0
ffe1ea72ea29 ARMv6 optimised pix_abs8
mru
parents: 11111
diff changeset
509 pld [r2, r3]
ffe1ea72ea29 ARMv6 optimised pix_abs8
mru
parents: 11111
diff changeset
510 usada8 lr, r9, r7, lr
ffe1ea72ea29 ARMv6 optimised pix_abs8
mru
parents: 11111
diff changeset
511 b 1b
ffe1ea72ea29 ARMv6 optimised pix_abs8
mru
parents: 11111
diff changeset
512 2:
ffe1ea72ea29 ARMv6 optimised pix_abs8
mru
parents: 11111
diff changeset
513 usada8 r0, r8, r6, r0
ffe1ea72ea29 ARMv6 optimised pix_abs8
mru
parents: 11111
diff changeset
514 usada8 lr, r9, r7, lr
ffe1ea72ea29 ARMv6 optimised pix_abs8
mru
parents: 11111
diff changeset
515 add r0, r0, lr
ffe1ea72ea29 ARMv6 optimised pix_abs8
mru
parents: 11111
diff changeset
516 pop {r4-r9, pc}
ffe1ea72ea29 ARMv6 optimised pix_abs8
mru
parents: 11111
diff changeset
517 .endfunc
11115
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
518
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
519 function ff_sse16_armv6, export=1
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
520 ldr r12, [sp]
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
521 push {r4-r9, lr}
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
522 mov r0, #0
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
523 1:
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
524 ldrd r4, r5, [r1]
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
525 ldr r8, [r2]
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
526 uxtb16 lr, r4
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
527 uxtb16 r4, r4, ror #8
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
528 uxtb16 r9, r8
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
529 uxtb16 r8, r8, ror #8
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
530 ldr r7, [r2, #4]
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
531 usub16 lr, lr, r9
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
532 usub16 r4, r4, r8
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
533 smlad r0, lr, lr, r0
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
534 uxtb16 r6, r5
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
535 uxtb16 lr, r5, ror #8
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
536 uxtb16 r8, r7
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
537 uxtb16 r9, r7, ror #8
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
538 smlad r0, r4, r4, r0
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
539 ldrd r4, r5, [r1, #8]
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
540 usub16 r6, r6, r8
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
541 usub16 r8, lr, r9
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
542 ldr r7, [r2, #8]
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
543 smlad r0, r6, r6, r0
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
544 uxtb16 lr, r4
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
545 uxtb16 r4, r4, ror #8
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
546 uxtb16 r9, r7
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
547 uxtb16 r7, r7, ror #8
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
548 smlad r0, r8, r8, r0
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
549 ldr r8, [r2, #12]
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
550 usub16 lr, lr, r9
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
551 usub16 r4, r4, r7
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
552 smlad r0, lr, lr, r0
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
553 uxtb16 r6, r5
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
554 uxtb16 r5, r5, ror #8
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
555 uxtb16 r9, r8
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
556 uxtb16 r8, r8, ror #8
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
557 smlad r0, r4, r4, r0
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
558 usub16 r6, r6, r9
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
559 usub16 r5, r5, r8
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
560 smlad r0, r6, r6, r0
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
561 add r1, r1, r3
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
562 add r2, r2, r3
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
563 subs r12, r12, #1
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
564 smlad r0, r5, r5, r0
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
565 bgt 1b
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
566
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
567 pop {r4-r9, pc}
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
568 .endfunc
11116
0198e3582544 ARMv6 optimised pix_norm1
mru
parents: 11115
diff changeset
569
0198e3582544 ARMv6 optimised pix_norm1
mru
parents: 11115
diff changeset
570 function ff_pix_norm1_armv6, export=1
0198e3582544 ARMv6 optimised pix_norm1
mru
parents: 11115
diff changeset
571 push {r4-r6, lr}
0198e3582544 ARMv6 optimised pix_norm1
mru
parents: 11115
diff changeset
572 mov r12, #16
0198e3582544 ARMv6 optimised pix_norm1
mru
parents: 11115
diff changeset
573 mov lr, #0
0198e3582544 ARMv6 optimised pix_norm1
mru
parents: 11115
diff changeset
574 1:
0198e3582544 ARMv6 optimised pix_norm1
mru
parents: 11115
diff changeset
575 ldm r0, {r2-r5}
0198e3582544 ARMv6 optimised pix_norm1
mru
parents: 11115
diff changeset
576 uxtb16 r6, r2
0198e3582544 ARMv6 optimised pix_norm1
mru
parents: 11115
diff changeset
577 uxtb16 r2, r2, ror #8
0198e3582544 ARMv6 optimised pix_norm1
mru
parents: 11115
diff changeset
578 smlad lr, r6, r6, lr
0198e3582544 ARMv6 optimised pix_norm1
mru
parents: 11115
diff changeset
579 uxtb16 r6, r3
0198e3582544 ARMv6 optimised pix_norm1
mru
parents: 11115
diff changeset
580 smlad lr, r2, r2, lr
0198e3582544 ARMv6 optimised pix_norm1
mru
parents: 11115
diff changeset
581 uxtb16 r3, r3, ror #8
0198e3582544 ARMv6 optimised pix_norm1
mru
parents: 11115
diff changeset
582 smlad lr, r6, r6, lr
0198e3582544 ARMv6 optimised pix_norm1
mru
parents: 11115
diff changeset
583 uxtb16 r6, r4
0198e3582544 ARMv6 optimised pix_norm1
mru
parents: 11115
diff changeset
584 smlad lr, r3, r3, lr
0198e3582544 ARMv6 optimised pix_norm1
mru
parents: 11115
diff changeset
585 uxtb16 r4, r4, ror #8
0198e3582544 ARMv6 optimised pix_norm1
mru
parents: 11115
diff changeset
586 smlad lr, r6, r6, lr
0198e3582544 ARMv6 optimised pix_norm1
mru
parents: 11115
diff changeset
587 uxtb16 r6, r5
0198e3582544 ARMv6 optimised pix_norm1
mru
parents: 11115
diff changeset
588 smlad lr, r4, r4, lr
0198e3582544 ARMv6 optimised pix_norm1
mru
parents: 11115
diff changeset
589 uxtb16 r5, r5, ror #8
0198e3582544 ARMv6 optimised pix_norm1
mru
parents: 11115
diff changeset
590 smlad lr, r6, r6, lr
0198e3582544 ARMv6 optimised pix_norm1
mru
parents: 11115
diff changeset
591 subs r12, r12, #1
0198e3582544 ARMv6 optimised pix_norm1
mru
parents: 11115
diff changeset
592 add r0, r0, r1
0198e3582544 ARMv6 optimised pix_norm1
mru
parents: 11115
diff changeset
593 smlad lr, r5, r5, lr
0198e3582544 ARMv6 optimised pix_norm1
mru
parents: 11115
diff changeset
594 bgt 1b
0198e3582544 ARMv6 optimised pix_norm1
mru
parents: 11115
diff changeset
595
0198e3582544 ARMv6 optimised pix_norm1
mru
parents: 11115
diff changeset
596 mov r0, lr
0198e3582544 ARMv6 optimised pix_norm1
mru
parents: 11115
diff changeset
597 pop {r4-r6, pc}
0198e3582544 ARMv6 optimised pix_norm1
mru
parents: 11115
diff changeset
598 .endfunc
11117
ad6d17b36a3a ARMv6 optimised pix_sum
mru
parents: 11116
diff changeset
599
ad6d17b36a3a ARMv6 optimised pix_sum
mru
parents: 11116
diff changeset
600 function ff_pix_sum_armv6, export=1
ad6d17b36a3a ARMv6 optimised pix_sum
mru
parents: 11116
diff changeset
601 push {r4-r7, lr}
ad6d17b36a3a ARMv6 optimised pix_sum
mru
parents: 11116
diff changeset
602 mov r12, #16
ad6d17b36a3a ARMv6 optimised pix_sum
mru
parents: 11116
diff changeset
603 mov r2, #0
ad6d17b36a3a ARMv6 optimised pix_sum
mru
parents: 11116
diff changeset
604 mov r3, #0
ad6d17b36a3a ARMv6 optimised pix_sum
mru
parents: 11116
diff changeset
605 mov lr, #0
ad6d17b36a3a ARMv6 optimised pix_sum
mru
parents: 11116
diff changeset
606 ldr r4, [r0]
ad6d17b36a3a ARMv6 optimised pix_sum
mru
parents: 11116
diff changeset
607 1:
ad6d17b36a3a ARMv6 optimised pix_sum
mru
parents: 11116
diff changeset
608 subs r12, r12, #1
ad6d17b36a3a ARMv6 optimised pix_sum
mru
parents: 11116
diff changeset
609 ldr r5, [r0, #4]
ad6d17b36a3a ARMv6 optimised pix_sum
mru
parents: 11116
diff changeset
610 usada8 r2, r4, lr, r2
ad6d17b36a3a ARMv6 optimised pix_sum
mru
parents: 11116
diff changeset
611 ldr r6, [r0, #8]
ad6d17b36a3a ARMv6 optimised pix_sum
mru
parents: 11116
diff changeset
612 usada8 r3, r5, lr, r3
ad6d17b36a3a ARMv6 optimised pix_sum
mru
parents: 11116
diff changeset
613 ldr r7, [r0, #12]
ad6d17b36a3a ARMv6 optimised pix_sum
mru
parents: 11116
diff changeset
614 usada8 r2, r6, lr, r2
ad6d17b36a3a ARMv6 optimised pix_sum
mru
parents: 11116
diff changeset
615 beq 2f
ad6d17b36a3a ARMv6 optimised pix_sum
mru
parents: 11116
diff changeset
616 ldr r4, [r0, r1]!
ad6d17b36a3a ARMv6 optimised pix_sum
mru
parents: 11116
diff changeset
617 usada8 r3, r7, lr, r3
ad6d17b36a3a ARMv6 optimised pix_sum
mru
parents: 11116
diff changeset
618 bgt 1b
ad6d17b36a3a ARMv6 optimised pix_sum
mru
parents: 11116
diff changeset
619 2:
ad6d17b36a3a ARMv6 optimised pix_sum
mru
parents: 11116
diff changeset
620 usada8 r3, r7, lr, r3
ad6d17b36a3a ARMv6 optimised pix_sum
mru
parents: 11116
diff changeset
621 add r0, r2, r3
ad6d17b36a3a ARMv6 optimised pix_sum
mru
parents: 11116
diff changeset
622 pop {r4-r7, pc}
ad6d17b36a3a ARMv6 optimised pix_sum
mru
parents: 11116
diff changeset
623 .endfunc