annotate arm/simple_idct_armv5te.S @ 9899:06ab8ac1a593 libavcodec

Fix libx264.c to not drop SEI userdata from x264 encoder. Most muxers in ffmpeg ignore the SEI if it is placed in extradata, so instead it has to be catted to the front of the first video frame.
author darkshikari
date Tue, 30 Jun 2009 23:45:01 +0000
parents 9281a8a9387a
children 989ea69f6a4e
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1 /*
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2 * Simple IDCT
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3 *
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4 * Copyright (c) 2001 Michael Niedermayer <michaelni@gmx.at>
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5 * Copyright (c) 2006 Mans Rullgard <mans@mansr.com>
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6 *
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7 * This file is part of FFmpeg.
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8 *
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9 * FFmpeg is free software; you can redistribute it and/or
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10 * modify it under the terms of the GNU Lesser General Public
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11 * License as published by the Free Software Foundation; either
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12 * version 2.1 of the License, or (at your option) any later version.
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13 *
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14 * FFmpeg is distributed in the hope that it will be useful,
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15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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17 * Lesser General Public License for more details.
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18 *
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19 * You should have received a copy of the GNU Lesser General Public
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20 * License along with FFmpeg; if not, write to the Free Software
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21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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22 */
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23
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24 #include "asm.S"
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25
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26 #define W1 22725 /* cos(i*M_PI/16)*sqrt(2)*(1<<14) + 0.5 */
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27 #define W2 21407 /* cos(i*M_PI/16)*sqrt(2)*(1<<14) + 0.5 */
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28 #define W3 19266 /* cos(i*M_PI/16)*sqrt(2)*(1<<14) + 0.5 */
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29 #define W4 16383 /* cos(i*M_PI/16)*sqrt(2)*(1<<14) + 0.5 */
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30 #define W5 12873 /* cos(i*M_PI/16)*sqrt(2)*(1<<14) + 0.5 */
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31 #define W6 8867 /* cos(i*M_PI/16)*sqrt(2)*(1<<14) + 0.5 */
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32 #define W7 4520 /* cos(i*M_PI/16)*sqrt(2)*(1<<14) + 0.5 */
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33 #define ROW_SHIFT 11
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34 #define COL_SHIFT 20
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35
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36 #define W13 (W1 | (W3 << 16))
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37 #define W26 (W2 | (W6 << 16))
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38 #define W57 (W5 | (W7 << 16))
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39
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40 .text
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41 .align
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42 w13: .long W13
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43 w26: .long W26
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44 w57: .long W57
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45
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46 function idct_row_armv5te
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47 str lr, [sp, #-4]!
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48
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49 ldrd v1, [a1, #8]
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50 ldrd a3, [a1] /* a3 = row[1:0], a4 = row[3:2] */
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51 orrs v1, v1, v2
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52 cmpeq v1, a4
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53 cmpeq v1, a3, lsr #16
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54 beq row_dc_only
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55
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56 mov v1, #(1<<(ROW_SHIFT-1))
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57 mov ip, #16384
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58 sub ip, ip, #1 /* ip = W4 */
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59 smlabb v1, ip, a3, v1 /* v1 = W4*row[0]+(1<<(RS-1)) */
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60 ldr ip, [pc, #(w26-.-8)] /* ip = W2 | (W6 << 16) */
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61 smultb a2, ip, a4
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62 smulbb lr, ip, a4
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63 add v2, v1, a2
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64 sub v3, v1, a2
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65 sub v4, v1, lr
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66 add v1, v1, lr
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67
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68 ldr ip, [pc, #(w13-.-8)] /* ip = W1 | (W3 << 16) */
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69 ldr lr, [pc, #(w57-.-8)] /* lr = W5 | (W7 << 16) */
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70 smulbt v5, ip, a3
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71 smultt v6, lr, a4
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72 smlatt v5, ip, a4, v5
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73 smultt a2, ip, a3
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74 smulbt v7, lr, a3
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75 sub v6, v6, a2
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76 smulbt a2, ip, a4
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77 smultt fp, lr, a3
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78 sub v7, v7, a2
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79 smulbt a2, lr, a4
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80 ldrd a3, [a1, #8] /* a3=row[5:4] a4=row[7:6] */
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81 sub fp, fp, a2
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82
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83 orrs a2, a3, a4
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84 beq 1f
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85
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86 smlabt v5, lr, a3, v5
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87 smlabt v6, ip, a3, v6
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88 smlatt v5, lr, a4, v5
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89 smlabt v6, lr, a4, v6
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90 smlatt v7, lr, a3, v7
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91 smlatt fp, ip, a3, fp
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92 smulbt a2, ip, a4
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93 smlatt v7, ip, a4, v7
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94 sub fp, fp, a2
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95
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96 ldr ip, [pc, #(w26-.-8)] /* ip = W2 | (W6 << 16) */
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97 mov a2, #16384
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98 sub a2, a2, #1 /* a2 = W4 */
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99 smulbb a2, a2, a3 /* a2 = W4*row[4] */
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100 smultb lr, ip, a4 /* lr = W6*row[6] */
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101 add v1, v1, a2 /* v1 += W4*row[4] */
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102 add v1, v1, lr /* v1 += W6*row[6] */
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103 add v4, v4, a2 /* v4 += W4*row[4] */
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104 sub v4, v4, lr /* v4 -= W6*row[6] */
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105 smulbb lr, ip, a4 /* lr = W2*row[6] */
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106 sub v2, v2, a2 /* v2 -= W4*row[4] */
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107 sub v2, v2, lr /* v2 -= W2*row[6] */
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108 sub v3, v3, a2 /* v3 -= W4*row[4] */
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109 add v3, v3, lr /* v3 += W2*row[6] */
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110
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111 1: add a2, v1, v5
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112 mov a3, a2, lsr #11
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113 bic a3, a3, #0x1f0000
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114 sub a2, v2, v6
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115 mov a2, a2, lsr #11
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116 add a3, a3, a2, lsl #16
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117 add a2, v3, v7
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118 mov a4, a2, lsr #11
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119 bic a4, a4, #0x1f0000
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120 add a2, v4, fp
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121 mov a2, a2, lsr #11
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122 add a4, a4, a2, lsl #16
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123 strd a3, [a1]
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124
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125 sub a2, v4, fp
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126 mov a3, a2, lsr #11
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127 bic a3, a3, #0x1f0000
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128 sub a2, v3, v7
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129 mov a2, a2, lsr #11
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130 add a3, a3, a2, lsl #16
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131 add a2, v2, v6
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132 mov a4, a2, lsr #11
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133 bic a4, a4, #0x1f0000
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134 sub a2, v1, v5
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135 mov a2, a2, lsr #11
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136 add a4, a4, a2, lsl #16
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137 strd a3, [a1, #8]
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138
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139 ldr pc, [sp], #4
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140
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141 row_dc_only:
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142 orr a3, a3, a3, lsl #16
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143 bic a3, a3, #0xe000
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144 mov a3, a3, lsl #3
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145 mov a4, a3
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146 strd a3, [a1]
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147 strd a3, [a1, #8]
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148
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149 ldr pc, [sp], #4
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150 .endfunc
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151
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152 .macro idct_col
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153 ldr a4, [a1] /* a4 = col[1:0] */
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154 mov ip, #16384
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155 sub ip, ip, #1 /* ip = W4 */
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156 #if 0
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157 mov v1, #(1<<(COL_SHIFT-1))
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158 smlabt v2, ip, a4, v1 /* v2 = W4*col[1] + (1<<(COL_SHIFT-1)) */
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159 smlabb v1, ip, a4, v1 /* v1 = W4*col[0] + (1<<(COL_SHIFT-1)) */
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160 ldr a4, [a1, #(16*4)]
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161 #else
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162 mov v1, #((1<<(COL_SHIFT-1))/W4) /* this matches the C version */
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163 add v2, v1, a4, asr #16
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164 rsb v2, v2, v2, lsl #14
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165 mov a4, a4, lsl #16
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166 add v1, v1, a4, asr #16
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167 ldr a4, [a1, #(16*4)]
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168 rsb v1, v1, v1, lsl #14
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169 #endif
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170
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171 smulbb lr, ip, a4
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172 smulbt a3, ip, a4
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173 sub v3, v1, lr
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174 sub v5, v1, lr
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175 add v7, v1, lr
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176 add v1, v1, lr
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177 sub v4, v2, a3
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178 sub v6, v2, a3
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179 add fp, v2, a3
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180 ldr ip, [pc, #(w26-.-8)]
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
181 ldr a4, [a1, #(16*2)]
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
182 add v2, v2, a3
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
183
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
184 smulbb lr, ip, a4
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
185 smultb a3, ip, a4
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
186 add v1, v1, lr
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
187 sub v7, v7, lr
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
188 add v3, v3, a3
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
189 sub v5, v5, a3
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
190 smulbt lr, ip, a4
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
191 smultt a3, ip, a4
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
192 add v2, v2, lr
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
193 sub fp, fp, lr
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
194 add v4, v4, a3
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
195 ldr a4, [a1, #(16*6)]
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
196 sub v6, v6, a3
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
197
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
198 smultb lr, ip, a4
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
199 smulbb a3, ip, a4
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
200 add v1, v1, lr
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
201 sub v7, v7, lr
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
202 sub v3, v3, a3
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
203 add v5, v5, a3
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
204 smultt lr, ip, a4
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
205 smulbt a3, ip, a4
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
206 add v2, v2, lr
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
207 sub fp, fp, lr
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
208 sub v4, v4, a3
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
209 add v6, v6, a3
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
210
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
211 stmfd sp!, {v1, v2, v3, v4, v5, v6, v7, fp}
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
212
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
213 ldr ip, [pc, #(w13-.-8)]
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
214 ldr a4, [a1, #(16*1)]
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
215 ldr lr, [pc, #(w57-.-8)]
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
216 smulbb v1, ip, a4
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
217 smultb v3, ip, a4
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
218 smulbb v5, lr, a4
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
219 smultb v7, lr, a4
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
220 smulbt v2, ip, a4
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
221 smultt v4, ip, a4
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
222 smulbt v6, lr, a4
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
223 smultt fp, lr, a4
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
224 rsb v4, v4, #0
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
225 ldr a4, [a1, #(16*3)]
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
226 rsb v3, v3, #0
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
227
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
228 smlatb v1, ip, a4, v1
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
229 smlatb v3, lr, a4, v3
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
230 smulbb a3, ip, a4
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
231 smulbb a2, lr, a4
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
232 sub v5, v5, a3
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
233 sub v7, v7, a2
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
234 smlatt v2, ip, a4, v2
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
235 smlatt v4, lr, a4, v4
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
236 smulbt a3, ip, a4
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
237 smulbt a2, lr, a4
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
238 sub v6, v6, a3
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
239 ldr a4, [a1, #(16*5)]
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
240 sub fp, fp, a2
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
241
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
242 smlabb v1, lr, a4, v1
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
243 smlabb v3, ip, a4, v3
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
244 smlatb v5, lr, a4, v5
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
245 smlatb v7, ip, a4, v7
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
246 smlabt v2, lr, a4, v2
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
247 smlabt v4, ip, a4, v4
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
248 smlatt v6, lr, a4, v6
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
249 ldr a3, [a1, #(16*7)]
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
250 smlatt fp, ip, a4, fp
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
251
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
252 smlatb v1, lr, a3, v1
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
253 smlabb v3, lr, a3, v3
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
254 smlatb v5, ip, a3, v5
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
255 smulbb a4, ip, a3
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
256 smlatt v2, lr, a3, v2
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
257 sub v7, v7, a4
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
258 smlabt v4, lr, a3, v4
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
259 smulbt a4, ip, a3
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
260 smlatt v6, ip, a3, v6
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
261 sub fp, fp, a4
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
262 .endm
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
263
8069
316762ae96a7 ARM: use new macros for assembler function labels
mru
parents: 5220
diff changeset
264 function idct_col_armv5te
3769
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
265 str lr, [sp, #-4]!
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
266
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
267 idct_col
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
268
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
269 ldmfd sp!, {a3, a4}
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
270 adds a2, a3, v1
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
271 mov a2, a2, lsr #20
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
272 orrmi a2, a2, #0xf000
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
273 add ip, a4, v2
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
274 mov ip, ip, asr #20
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
275 orr a2, a2, ip, lsl #16
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
276 str a2, [a1]
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
277 subs a3, a3, v1
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
278 mov a2, a3, lsr #20
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
279 orrmi a2, a2, #0xf000
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
280 sub a4, a4, v2
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
281 mov a4, a4, asr #20
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
282 orr a2, a2, a4, lsl #16
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
283 ldmfd sp!, {a3, a4}
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
284 str a2, [a1, #(16*7)]
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
285
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
286 subs a2, a3, v3
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
287 mov a2, a2, lsr #20
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
288 orrmi a2, a2, #0xf000
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
289 sub ip, a4, v4
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
290 mov ip, ip, asr #20
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
291 orr a2, a2, ip, lsl #16
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
292 str a2, [a1, #(16*1)]
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
293 adds a3, a3, v3
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
294 mov a2, a3, lsr #20
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
295 orrmi a2, a2, #0xf000
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
296 add a4, a4, v4
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
297 mov a4, a4, asr #20
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
298 orr a2, a2, a4, lsl #16
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
299 ldmfd sp!, {a3, a4}
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
300 str a2, [a1, #(16*6)]
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
301
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
302 adds a2, a3, v5
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
303 mov a2, a2, lsr #20
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
304 orrmi a2, a2, #0xf000
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
305 add ip, a4, v6
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
306 mov ip, ip, asr #20
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
307 orr a2, a2, ip, lsl #16
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
308 str a2, [a1, #(16*2)]
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
309 subs a3, a3, v5
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
310 mov a2, a3, lsr #20
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
311 orrmi a2, a2, #0xf000
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
312 sub a4, a4, v6
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
313 mov a4, a4, asr #20
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
314 orr a2, a2, a4, lsl #16
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
315 ldmfd sp!, {a3, a4}
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
316 str a2, [a1, #(16*5)]
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
317
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
318 adds a2, a3, v7
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
319 mov a2, a2, lsr #20
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
320 orrmi a2, a2, #0xf000
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
321 add ip, a4, fp
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
322 mov ip, ip, asr #20
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
323 orr a2, a2, ip, lsl #16
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
324 str a2, [a1, #(16*3)]
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
325 subs a3, a3, v7
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
326 mov a2, a3, lsr #20
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
327 orrmi a2, a2, #0xf000
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
328 sub a4, a4, fp
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
329 mov a4, a4, asr #20
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
330 orr a2, a2, a4, lsl #16
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
331 str a2, [a1, #(16*4)]
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
332
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
333 ldr pc, [sp], #4
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
334 .endfunc
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
335
8069
316762ae96a7 ARM: use new macros for assembler function labels
mru
parents: 5220
diff changeset
336 function idct_col_put_armv5te
3769
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
337 str lr, [sp, #-4]!
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
338
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
339 idct_col
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
340
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
341 ldmfd sp!, {a3, a4}
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
342 ldr lr, [sp, #32]
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
343 add a2, a3, v1
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
344 movs a2, a2, asr #20
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
345 movmi a2, #0
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
346 cmp a2, #255
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
347 movgt a2, #255
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
348 add ip, a4, v2
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
349 movs ip, ip, asr #20
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
350 movmi ip, #0
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
351 cmp ip, #255
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
352 movgt ip, #255
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
353 orr a2, a2, ip, lsl #8
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
354 sub a3, a3, v1
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
355 movs a3, a3, asr #20
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
356 movmi a3, #0
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
357 cmp a3, #255
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
358 movgt a3, #255
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
359 sub a4, a4, v2
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
360 movs a4, a4, asr #20
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
361 movmi a4, #0
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
362 cmp a4, #255
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
363 ldr v1, [sp, #28]
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
364 movgt a4, #255
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
365 strh a2, [v1]
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
366 add a2, v1, #2
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
367 str a2, [sp, #28]
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
368 orr a2, a3, a4, lsl #8
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
369 rsb v2, lr, lr, lsl #3
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
370 ldmfd sp!, {a3, a4}
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
371 strh a2, [v2, v1]!
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
372
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
373 sub a2, a3, v3
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
374 movs a2, a2, asr #20
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
375 movmi a2, #0
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
376 cmp a2, #255
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
377 movgt a2, #255
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
378 sub ip, a4, v4
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
379 movs ip, ip, asr #20
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
380 movmi ip, #0
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
381 cmp ip, #255
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
382 movgt ip, #255
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
383 orr a2, a2, ip, lsl #8
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
384 strh a2, [v1, lr]!
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
385 add a3, a3, v3
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
386 movs a2, a3, asr #20
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
387 movmi a2, #0
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
388 cmp a2, #255
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
389 movgt a2, #255
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
390 add a4, a4, v4
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
391 movs a4, a4, asr #20
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
392 movmi a4, #0
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
393 cmp a4, #255
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
394 movgt a4, #255
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
395 orr a2, a2, a4, lsl #8
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
396 ldmfd sp!, {a3, a4}
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
397 strh a2, [v2, -lr]!
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
398
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
399 add a2, a3, v5
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
400 movs a2, a2, asr #20
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
401 movmi a2, #0
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
402 cmp a2, #255
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
403 movgt a2, #255
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
404 add ip, a4, v6
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
405 movs ip, ip, asr #20
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
406 movmi ip, #0
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
407 cmp ip, #255
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
408 movgt ip, #255
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
409 orr a2, a2, ip, lsl #8
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
410 strh a2, [v1, lr]!
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
411 sub a3, a3, v5
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
412 movs a2, a3, asr #20
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
413 movmi a2, #0
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
414 cmp a2, #255
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
415 movgt a2, #255
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
416 sub a4, a4, v6
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
417 movs a4, a4, asr #20
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
418 movmi a4, #0
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
419 cmp a4, #255
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
420 movgt a4, #255
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
421 orr a2, a2, a4, lsl #8
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
422 ldmfd sp!, {a3, a4}
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
423 strh a2, [v2, -lr]!
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
424
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
425 add a2, a3, v7
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
426 movs a2, a2, asr #20
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
427 movmi a2, #0
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
428 cmp a2, #255
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
429 movgt a2, #255
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
430 add ip, a4, fp
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
431 movs ip, ip, asr #20
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
432 movmi ip, #0
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
433 cmp ip, #255
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
434 movgt ip, #255
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
435 orr a2, a2, ip, lsl #8
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
436 strh a2, [v1, lr]
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
437 sub a3, a3, v7
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
438 movs a2, a3, asr #20
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
439 movmi a2, #0
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
440 cmp a2, #255
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
441 movgt a2, #255
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
442 sub a4, a4, fp
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
443 movs a4, a4, asr #20
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
444 movmi a4, #0
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
445 cmp a4, #255
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
446 movgt a4, #255
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
447 orr a2, a2, a4, lsl #8
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
448 strh a2, [v2, -lr]
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
449
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
450 ldr pc, [sp], #4
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
451 .endfunc
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
452
8069
316762ae96a7 ARM: use new macros for assembler function labels
mru
parents: 5220
diff changeset
453 function idct_col_add_armv5te
3769
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
454 str lr, [sp, #-4]!
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
455
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
456 idct_col
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
457
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
458 ldr lr, [sp, #36]
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
459
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
460 ldmfd sp!, {a3, a4}
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
461 ldrh ip, [lr]
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
462 add a2, a3, v1
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
463 mov a2, a2, asr #20
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
464 sub a3, a3, v1
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
465 and v1, ip, #255
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
466 adds a2, a2, v1
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
467 movmi a2, #0
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
468 cmp a2, #255
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
469 movgt a2, #255
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
470 add v1, a4, v2
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
471 mov v1, v1, asr #20
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
472 adds v1, v1, ip, lsr #8
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
473 movmi v1, #0
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
474 cmp v1, #255
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
475 movgt v1, #255
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
476 orr a2, a2, v1, lsl #8
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
477 ldr v1, [sp, #32]
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
478 sub a4, a4, v2
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
479 rsb v2, v1, v1, lsl #3
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
480 ldrh ip, [v2, lr]!
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
481 strh a2, [lr]
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
482 mov a3, a3, asr #20
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
483 and a2, ip, #255
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
484 adds a3, a3, a2
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
485 movmi a3, #0
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
486 cmp a3, #255
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
487 movgt a3, #255
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
488 mov a4, a4, asr #20
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
489 adds a4, a4, ip, lsr #8
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
490 movmi a4, #0
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
491 cmp a4, #255
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
492 movgt a4, #255
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
493 add a2, lr, #2
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
494 str a2, [sp, #28]
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
495 orr a2, a3, a4, lsl #8
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
496 strh a2, [v2]
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
497
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
498 ldmfd sp!, {a3, a4}
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
499 ldrh ip, [lr, v1]!
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
500 sub a2, a3, v3
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
501 mov a2, a2, asr #20
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
502 add a3, a3, v3
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
503 and v3, ip, #255
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
504 adds a2, a2, v3
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
505 movmi a2, #0
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
506 cmp a2, #255
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
507 movgt a2, #255
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
508 sub v3, a4, v4
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
509 mov v3, v3, asr #20
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
510 adds v3, v3, ip, lsr #8
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
511 movmi v3, #0
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
512 cmp v3, #255
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
513 movgt v3, #255
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
514 orr a2, a2, v3, lsl #8
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
515 add a4, a4, v4
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
516 ldrh ip, [v2, -v1]!
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
517 strh a2, [lr]
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
518 mov a3, a3, asr #20
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
519 and a2, ip, #255
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
520 adds a3, a3, a2
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
521 movmi a3, #0
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
522 cmp a3, #255
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
523 movgt a3, #255
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
524 mov a4, a4, asr #20
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
525 adds a4, a4, ip, lsr #8
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
526 movmi a4, #0
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
527 cmp a4, #255
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
528 movgt a4, #255
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
529 orr a2, a3, a4, lsl #8
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
530 strh a2, [v2]
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
531
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
532 ldmfd sp!, {a3, a4}
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
533 ldrh ip, [lr, v1]!
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
534 add a2, a3, v5
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
535 mov a2, a2, asr #20
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
536 sub a3, a3, v5
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
537 and v3, ip, #255
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
538 adds a2, a2, v3
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
539 movmi a2, #0
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
540 cmp a2, #255
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
541 movgt a2, #255
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
542 add v3, a4, v6
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
543 mov v3, v3, asr #20
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
544 adds v3, v3, ip, lsr #8
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
545 movmi v3, #0
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
546 cmp v3, #255
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
547 movgt v3, #255
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
548 orr a2, a2, v3, lsl #8
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
549 sub a4, a4, v6
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
550 ldrh ip, [v2, -v1]!
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
551 strh a2, [lr]
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
552 mov a3, a3, asr #20
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
553 and a2, ip, #255
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
554 adds a3, a3, a2
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
555 movmi a3, #0
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
556 cmp a3, #255
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
557 movgt a3, #255
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
558 mov a4, a4, asr #20
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
559 adds a4, a4, ip, lsr #8
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
560 movmi a4, #0
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
561 cmp a4, #255
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
562 movgt a4, #255
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
563 orr a2, a3, a4, lsl #8
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
564 strh a2, [v2]
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
565
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
566 ldmfd sp!, {a3, a4}
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
567 ldrh ip, [lr, v1]!
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
568 add a2, a3, v7
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
569 mov a2, a2, asr #20
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
570 sub a3, a3, v7
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
571 and v3, ip, #255
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
572 adds a2, a2, v3
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
573 movmi a2, #0
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
574 cmp a2, #255
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
575 movgt a2, #255
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
576 add v3, a4, fp
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
577 mov v3, v3, asr #20
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
578 adds v3, v3, ip, lsr #8
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
579 movmi v3, #0
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
580 cmp v3, #255
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
581 movgt v3, #255
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
582 orr a2, a2, v3, lsl #8
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
583 sub a4, a4, fp
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
584 ldrh ip, [v2, -v1]!
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
585 strh a2, [lr]
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
586 mov a3, a3, asr #20
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
587 and a2, ip, #255
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
588 adds a3, a3, a2
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
589 movmi a3, #0
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
590 cmp a3, #255
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
591 movgt a3, #255
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
592 mov a4, a4, asr #20
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
593 adds a4, a4, ip, lsr #8
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
594 movmi a4, #0
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
595 cmp a4, #255
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
596 movgt a4, #255
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
597 orr a2, a3, a4, lsl #8
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
598 strh a2, [v2]
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
599
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
600 ldr pc, [sp], #4
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
601 .endfunc
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
602
8069
316762ae96a7 ARM: use new macros for assembler function labels
mru
parents: 5220
diff changeset
603 function simple_idct_armv5te, export=1
3769
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
604 stmfd sp!, {v1, v2, v3, v4, v5, v6, v7, fp, lr}
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
605
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
606 bl idct_row_armv5te
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
607 add a1, a1, #16
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
608 bl idct_row_armv5te
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
609 add a1, a1, #16
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
610 bl idct_row_armv5te
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
611 add a1, a1, #16
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
612 bl idct_row_armv5te
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
613 add a1, a1, #16
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
614 bl idct_row_armv5te
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
615 add a1, a1, #16
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
616 bl idct_row_armv5te
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
617 add a1, a1, #16
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
618 bl idct_row_armv5te
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
619 add a1, a1, #16
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
620 bl idct_row_armv5te
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
621
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
622 sub a1, a1, #(16*7)
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
623
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
624 bl idct_col_armv5te
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
625 add a1, a1, #4
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
626 bl idct_col_armv5te
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
627 add a1, a1, #4
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
628 bl idct_col_armv5te
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
629 add a1, a1, #4
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
630 bl idct_col_armv5te
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
631
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
632 ldmfd sp!, {v1, v2, v3, v4, v5, v6, v7, fp, pc}
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
633 .endfunc
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
634
8069
316762ae96a7 ARM: use new macros for assembler function labels
mru
parents: 5220
diff changeset
635 function simple_idct_add_armv5te, export=1
3769
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
636 stmfd sp!, {a1, a2, v1, v2, v3, v4, v5, v6, v7, fp, lr}
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
637
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
638 mov a1, a3
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
639
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
640 bl idct_row_armv5te
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
641 add a1, a1, #16
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
642 bl idct_row_armv5te
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
643 add a1, a1, #16
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
644 bl idct_row_armv5te
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
645 add a1, a1, #16
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
646 bl idct_row_armv5te
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
647 add a1, a1, #16
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
648 bl idct_row_armv5te
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
649 add a1, a1, #16
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
650 bl idct_row_armv5te
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
651 add a1, a1, #16
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
652 bl idct_row_armv5te
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
653 add a1, a1, #16
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
654 bl idct_row_armv5te
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
655
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
656 sub a1, a1, #(16*7)
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
657
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
658 bl idct_col_add_armv5te
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
659 add a1, a1, #4
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
660 bl idct_col_add_armv5te
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
661 add a1, a1, #4
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
662 bl idct_col_add_armv5te
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
663 add a1, a1, #4
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
664 bl idct_col_add_armv5te
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
665
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
666 add sp, sp, #8
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
667 ldmfd sp!, {v1, v2, v3, v4, v5, v6, v7, fp, pc}
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
668 .endfunc
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
669
8069
316762ae96a7 ARM: use new macros for assembler function labels
mru
parents: 5220
diff changeset
670 function simple_idct_put_armv5te, export=1
3769
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
671 stmfd sp!, {a1, a2, v1, v2, v3, v4, v5, v6, v7, fp, lr}
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
672
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
673 mov a1, a3
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
674
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
675 bl idct_row_armv5te
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
676 add a1, a1, #16
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
677 bl idct_row_armv5te
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
678 add a1, a1, #16
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
679 bl idct_row_armv5te
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
680 add a1, a1, #16
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
681 bl idct_row_armv5te
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
682 add a1, a1, #16
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
683 bl idct_row_armv5te
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
684 add a1, a1, #16
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
685 bl idct_row_armv5te
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
686 add a1, a1, #16
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
687 bl idct_row_armv5te
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
688 add a1, a1, #16
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
689 bl idct_row_armv5te
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
690
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
691 sub a1, a1, #(16*7)
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
692
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
693 bl idct_col_put_armv5te
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
694 add a1, a1, #4
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
695 bl idct_col_put_armv5te
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
696 add a1, a1, #4
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
697 bl idct_col_put_armv5te
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
698 add a1, a1, #4
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
699 bl idct_col_put_armv5te
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
700
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
701 add sp, sp, #8
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
702 ldmfd sp!, {v1, v2, v3, v4, v5, v6, v7, fp, pc}
cf04e15a72ac ARMv5TE optimized IDCT
mru
parents:
diff changeset
703 .endfunc