Mercurial > libavcodec.hg
annotate sparc/vis.h @ 10392:32ee88f14239 libavcodec
Fix w32thread implementation to handle job count > thread_count.
author | reimar |
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date | Tue, 13 Oct 2009 13:03:12 +0000 |
parents | f9c847fb4839 |
children | bf6d274fef39 |
rev | line source |
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1 /* |
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2 * Copyright (C) 2003 David S. Miller <davem@redhat.com> |
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3 * |
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4 * This file is part of FFmpeg. |
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5 * |
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6 * FFmpeg is free software; you can redistribute it and/or |
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7 * modify it under the terms of the GNU Lesser General Public |
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8 * License as published by the Free Software Foundation; either |
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9 * version 2.1 of the License, or (at your option) any later version. |
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10 * |
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11 * FFmpeg is distributed in the hope that it will be useful, |
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12 * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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14 * Lesser General Public License for more details. |
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15 * |
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16 * You should have received a copy of the GNU Lesser General Public |
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17 * License along with FFmpeg; if not, write to the Free Software |
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18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA |
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19 */ |
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20 |
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21 /* You may be asking why I hard-code the instruction opcodes and don't |
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22 * use the normal VIS assembler mnenomics for the VIS instructions. |
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23 * |
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24 * The reason is that Sun, in their infinite wisdom, decided that a binary |
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25 * using a VIS instruction will cause it to be marked (in the ELF headers) |
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26 * as doing so, and this prevents the OS from loading such binaries if the |
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27 * current cpu doesn't have VIS. There is no way to easily override this |
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28 * behavior of the assembler that I am aware of. |
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29 * |
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30 * This totally defeats what libmpeg2 is trying to do which is allow a |
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31 * single binary to be created, and then detect the availability of VIS |
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32 * at runtime. |
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33 * |
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34 * I'm not saying that tainting the binary by default is bad, rather I'm |
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35 * saying that not providing a way to override this easily unnecessarily |
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36 * ties people's hands. |
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37 * |
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38 * Thus, we do the opcode encoding by hand and output 32-bit words in |
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39 * the assembler to keep the binary from becoming tainted. |
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40 */ |
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41 |
7760 | 42 #ifndef AVCODEC_SPARC_VIS_H |
43 #define AVCODEC_SPARC_VIS_H | |
5163 | 44 |
2979 | 45 #define vis_opc_base ((0x1 << 31) | (0x36 << 19)) |
46 #define vis_opf(X) ((X) << 5) | |
47 #define vis_sreg(X) (X) | |
48 #define vis_dreg(X) (((X)&0x1f)|((X)>>5)) | |
49 #define vis_rs1_s(X) (vis_sreg(X) << 14) | |
50 #define vis_rs1_d(X) (vis_dreg(X) << 14) | |
51 #define vis_rs2_s(X) (vis_sreg(X) << 0) | |
52 #define vis_rs2_d(X) (vis_dreg(X) << 0) | |
53 #define vis_rd_s(X) (vis_sreg(X) << 25) | |
54 #define vis_rd_d(X) (vis_dreg(X) << 25) | |
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55 |
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56 #define vis_ss2s(opf,rs1,rs2,rd) \ |
8031 | 57 __asm__ volatile (".word %0" \ |
2979 | 58 : : "i" (vis_opc_base | vis_opf(opf) | \ |
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59 vis_rs1_s(rs1) | \ |
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60 vis_rs2_s(rs2) | \ |
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61 vis_rd_s(rd))) |
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62 |
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63 #define vis_dd2d(opf,rs1,rs2,rd) \ |
8031 | 64 __asm__ volatile (".word %0" \ |
2979 | 65 : : "i" (vis_opc_base | vis_opf(opf) | \ |
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66 vis_rs1_d(rs1) | \ |
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67 vis_rs2_d(rs2) | \ |
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68 vis_rd_d(rd))) |
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69 |
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70 #define vis_ss2d(opf,rs1,rs2,rd) \ |
8031 | 71 __asm__ volatile (".word %0" \ |
2979 | 72 : : "i" (vis_opc_base | vis_opf(opf) | \ |
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73 vis_rs1_s(rs1) | \ |
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74 vis_rs2_s(rs2) | \ |
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75 vis_rd_d(rd))) |
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76 |
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77 #define vis_sd2d(opf,rs1,rs2,rd) \ |
8031 | 78 __asm__ volatile (".word %0" \ |
2979 | 79 : : "i" (vis_opc_base | vis_opf(opf) | \ |
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80 vis_rs1_s(rs1) | \ |
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81 vis_rs2_d(rs2) | \ |
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82 vis_rd_d(rd))) |
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83 |
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84 #define vis_d2s(opf,rs2,rd) \ |
8031 | 85 __asm__ volatile (".word %0" \ |
2979 | 86 : : "i" (vis_opc_base | vis_opf(opf) | \ |
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87 vis_rs2_d(rs2) | \ |
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88 vis_rd_s(rd))) |
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89 |
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90 #define vis_s2d(opf,rs2,rd) \ |
8031 | 91 __asm__ volatile (".word %0" \ |
2979 | 92 : : "i" (vis_opc_base | vis_opf(opf) | \ |
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93 vis_rs2_s(rs2) | \ |
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94 vis_rd_d(rd))) |
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95 |
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96 #define vis_d12d(opf,rs1,rd) \ |
8031 | 97 __asm__ volatile (".word %0" \ |
2979 | 98 : : "i" (vis_opc_base | vis_opf(opf) | \ |
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99 vis_rs1_d(rs1) | \ |
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100 vis_rd_d(rd))) |
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101 |
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102 #define vis_d22d(opf,rs2,rd) \ |
8031 | 103 __asm__ volatile (".word %0" \ |
2979 | 104 : : "i" (vis_opc_base | vis_opf(opf) | \ |
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105 vis_rs2_d(rs2) | \ |
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106 vis_rd_d(rd))) |
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107 |
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108 #define vis_s12s(opf,rs1,rd) \ |
8031 | 109 __asm__ volatile (".word %0" \ |
2979 | 110 : : "i" (vis_opc_base | vis_opf(opf) | \ |
1959
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111 vis_rs1_s(rs1) | \ |
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112 vis_rd_s(rd))) |
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113 |
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114 #define vis_s22s(opf,rs2,rd) \ |
8031 | 115 __asm__ volatile (".word %0" \ |
2979 | 116 : : "i" (vis_opc_base | vis_opf(opf) | \ |
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117 vis_rs2_s(rs2) | \ |
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118 vis_rd_s(rd))) |
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119 |
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120 #define vis_s(opf,rd) \ |
8031 | 121 __asm__ volatile (".word %0" \ |
2979 | 122 : : "i" (vis_opc_base | vis_opf(opf) | \ |
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123 vis_rd_s(rd))) |
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124 |
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125 #define vis_d(opf,rd) \ |
8031 | 126 __asm__ volatile (".word %0" \ |
2979 | 127 : : "i" (vis_opc_base | vis_opf(opf) | \ |
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128 vis_rd_d(rd))) |
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129 |
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130 #define vis_r2m(op,rd,mem) \ |
8031 | 131 __asm__ volatile (#op "\t%%f" #rd ", [%0]" : : "r" (&(mem)) ) |
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132 |
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133 #define vis_r2m_2(op,rd,mem1,mem2) \ |
8031 | 134 __asm__ volatile (#op "\t%%f" #rd ", [%0 + %1]" : : "r" (mem1), "r" (mem2) ) |
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135 |
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136 #define vis_m2r(op,mem,rd) \ |
8031 | 137 __asm__ volatile (#op "\t[%0], %%f" #rd : : "r" (&(mem)) ) |
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138 |
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139 #define vis_m2r_2(op,mem1,mem2,rd) \ |
8031 | 140 __asm__ volatile (#op "\t[%0 + %1], %%f" #rd : : "r" (mem1), "r" (mem2) ) |
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141 |
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142 static inline void vis_set_gsr(unsigned int _val) |
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143 { |
8031 | 144 register unsigned int val __asm__("g1"); |
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145 |
2979 | 146 val = _val; |
8031 | 147 __asm__ volatile(".word 0xa7804000" |
2979 | 148 : : "r" (val)); |
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149 } |
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150 |
2979 | 151 #define VIS_GSR_ALIGNADDR_MASK 0x0000007 |
152 #define VIS_GSR_ALIGNADDR_SHIFT 0 | |
153 #define VIS_GSR_SCALEFACT_MASK 0x0000078 | |
154 #define VIS_GSR_SCALEFACT_SHIFT 3 | |
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155 |
2979 | 156 #define vis_ld32(mem,rs1) vis_m2r(ld, mem, rs1) |
157 #define vis_ld32_2(mem1,mem2,rs1) vis_m2r_2(ld, mem1, mem2, rs1) | |
158 #define vis_st32(rs1,mem) vis_r2m(st, rs1, mem) | |
159 #define vis_st32_2(rs1,mem1,mem2) vis_r2m_2(st, rs1, mem1, mem2) | |
160 #define vis_ld64(mem,rs1) vis_m2r(ldd, mem, rs1) | |
161 #define vis_ld64_2(mem1,mem2,rs1) vis_m2r_2(ldd, mem1, mem2, rs1) | |
162 #define vis_st64(rs1,mem) vis_r2m(std, rs1, mem) | |
163 #define vis_st64_2(rs1,mem1,mem2) vis_r2m_2(std, rs1, mem1, mem2) | |
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164 |
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165 #define vis_ldblk(mem, rd) \ |
8031 | 166 do { register void *__mem __asm__("g1"); \ |
2979 | 167 __mem = &(mem); \ |
8031 | 168 __asm__ volatile(".word 0xc1985e00 | %1" \ |
2979 | 169 : \ |
170 : "r" (__mem), \ | |
171 "i" (vis_rd_d(rd)) \ | |
172 : "memory"); \ | |
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173 } while (0) |
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174 |
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175 #define vis_stblk(rd, mem) \ |
8031 | 176 do { register void *__mem __asm__("g1"); \ |
2979 | 177 __mem = &(mem); \ |
8031 | 178 __asm__ volatile(".word 0xc1b85e00 | %1" \ |
2979 | 179 : \ |
180 : "r" (__mem), \ | |
181 "i" (vis_rd_d(rd)) \ | |
182 : "memory"); \ | |
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183 } while (0) |
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184 |
2979 | 185 #define vis_membar_storestore() \ |
8031 | 186 __asm__ volatile(".word 0x8143e008" : : : "memory") |
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187 |
2979 | 188 #define vis_membar_sync() \ |
8031 | 189 __asm__ volatile(".word 0x8143e040" : : : "memory") |
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190 |
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191 /* 16 and 32 bit partitioned addition and subtraction. The normal |
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192 * versions perform 4 16-bit or 2 32-bit additions or subtractions. |
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193 * The 's' versions perform 2 16-bit or 1 32-bit additions or |
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194 * subtractions. |
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195 */ |
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196 |
2979 | 197 #define vis_padd16(rs1,rs2,rd) vis_dd2d(0x50, rs1, rs2, rd) |
198 #define vis_padd16s(rs1,rs2,rd) vis_ss2s(0x51, rs1, rs2, rd) | |
199 #define vis_padd32(rs1,rs2,rd) vis_dd2d(0x52, rs1, rs2, rd) | |
200 #define vis_padd32s(rs1,rs2,rd) vis_ss2s(0x53, rs1, rs2, rd) | |
201 #define vis_psub16(rs1,rs2,rd) vis_dd2d(0x54, rs1, rs2, rd) | |
202 #define vis_psub16s(rs1,rs2,rd) vis_ss2s(0x55, rs1, rs2, rd) | |
203 #define vis_psub32(rs1,rs2,rd) vis_dd2d(0x56, rs1, rs2, rd) | |
204 #define vis_psub32s(rs1,rs2,rd) vis_ss2s(0x57, rs1, rs2, rd) | |
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205 |
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206 /* Pixel formatting instructions. */ |
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207 |
2979 | 208 #define vis_pack16(rs2,rd) vis_d2s( 0x3b, rs2, rd) |
209 #define vis_pack32(rs1,rs2,rd) vis_dd2d(0x3a, rs1, rs2, rd) | |
210 #define vis_packfix(rs2,rd) vis_d2s( 0x3d, rs2, rd) | |
211 #define vis_expand(rs2,rd) vis_s2d( 0x4d, rs2, rd) | |
212 #define vis_pmerge(rs1,rs2,rd) vis_ss2d(0x4b, rs1, rs2, rd) | |
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213 |
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214 /* Partitioned multiply instructions. */ |
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215 |
2979 | 216 #define vis_mul8x16(rs1,rs2,rd) vis_sd2d(0x31, rs1, rs2, rd) |
217 #define vis_mul8x16au(rs1,rs2,rd) vis_ss2d(0x33, rs1, rs2, rd) | |
218 #define vis_mul8x16al(rs1,rs2,rd) vis_ss2d(0x35, rs1, rs2, rd) | |
219 #define vis_mul8sux16(rs1,rs2,rd) vis_dd2d(0x36, rs1, rs2, rd) | |
220 #define vis_mul8ulx16(rs1,rs2,rd) vis_dd2d(0x37, rs1, rs2, rd) | |
221 #define vis_muld8sux16(rs1,rs2,rd) vis_ss2d(0x38, rs1, rs2, rd) | |
222 #define vis_muld8ulx16(rs1,rs2,rd) vis_ss2d(0x39, rs1, rs2, rd) | |
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223 |
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224 /* Alignment instructions. */ |
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225 |
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226 static inline void *vis_alignaddr(void *_ptr) |
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227 { |
8031 | 228 register void *ptr __asm__("g1"); |
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229 |
2979 | 230 ptr = _ptr; |
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231 |
8031 | 232 __asm__ volatile(".word %2" |
2979 | 233 : "=&r" (ptr) |
234 : "0" (ptr), | |
235 "i" (vis_opc_base | vis_opf(0x18) | | |
236 vis_rs1_s(1) | | |
237 vis_rs2_s(0) | | |
238 vis_rd_s(1))); | |
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239 |
2979 | 240 return ptr; |
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241 } |
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242 |
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243 static inline void vis_alignaddr_g0(void *_ptr) |
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244 { |
8031 | 245 register void *ptr __asm__("g1"); |
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246 |
2979 | 247 ptr = _ptr; |
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248 |
8031 | 249 __asm__ volatile(".word %2" |
2979 | 250 : "=&r" (ptr) |
251 : "0" (ptr), | |
252 "i" (vis_opc_base | vis_opf(0x18) | | |
253 vis_rs1_s(1) | | |
254 vis_rs2_s(0) | | |
255 vis_rd_s(0))); | |
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256 } |
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257 |
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258 static inline void *vis_alignaddrl(void *_ptr) |
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259 { |
8031 | 260 register void *ptr __asm__("g1"); |
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261 |
2979 | 262 ptr = _ptr; |
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263 |
8031 | 264 __asm__ volatile(".word %2" |
2979 | 265 : "=&r" (ptr) |
266 : "0" (ptr), | |
267 "i" (vis_opc_base | vis_opf(0x19) | | |
268 vis_rs1_s(1) | | |
269 vis_rs2_s(0) | | |
270 vis_rd_s(1))); | |
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271 |
2979 | 272 return ptr; |
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273 } |
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274 |
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275 static inline void vis_alignaddrl_g0(void *_ptr) |
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276 { |
8031 | 277 register void *ptr __asm__("g1"); |
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278 |
2979 | 279 ptr = _ptr; |
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280 |
8031 | 281 __asm__ volatile(".word %2" |
2979 | 282 : "=&r" (ptr) |
283 : "0" (ptr), | |
284 "i" (vis_opc_base | vis_opf(0x19) | | |
285 vis_rs1_s(1) | | |
286 vis_rs2_s(0) | | |
287 vis_rd_s(0))); | |
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288 } |
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289 |
2979 | 290 #define vis_faligndata(rs1,rs2,rd) vis_dd2d(0x48, rs1, rs2, rd) |
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291 |
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292 /* Logical operate instructions. */ |
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293 |
2979 | 294 #define vis_fzero(rd) vis_d( 0x60, rd) |
295 #define vis_fzeros(rd) vis_s( 0x61, rd) | |
296 #define vis_fone(rd) vis_d( 0x7e, rd) | |
297 #define vis_fones(rd) vis_s( 0x7f, rd) | |
298 #define vis_src1(rs1,rd) vis_d12d(0x74, rs1, rd) | |
299 #define vis_src1s(rs1,rd) vis_s12s(0x75, rs1, rd) | |
300 #define vis_src2(rs2,rd) vis_d22d(0x78, rs2, rd) | |
301 #define vis_src2s(rs2,rd) vis_s22s(0x79, rs2, rd) | |
302 #define vis_not1(rs1,rd) vis_d12d(0x6a, rs1, rd) | |
303 #define vis_not1s(rs1,rd) vis_s12s(0x6b, rs1, rd) | |
304 #define vis_not2(rs2,rd) vis_d22d(0x66, rs2, rd) | |
305 #define vis_not2s(rs2,rd) vis_s22s(0x67, rs2, rd) | |
306 #define vis_or(rs1,rs2,rd) vis_dd2d(0x7c, rs1, rs2, rd) | |
307 #define vis_ors(rs1,rs2,rd) vis_ss2s(0x7d, rs1, rs2, rd) | |
308 #define vis_nor(rs1,rs2,rd) vis_dd2d(0x62, rs1, rs2, rd) | |
309 #define vis_nors(rs1,rs2,rd) vis_ss2s(0x63, rs1, rs2, rd) | |
310 #define vis_and(rs1,rs2,rd) vis_dd2d(0x70, rs1, rs2, rd) | |
311 #define vis_ands(rs1,rs2,rd) vis_ss2s(0x71, rs1, rs2, rd) | |
312 #define vis_nand(rs1,rs2,rd) vis_dd2d(0x6e, rs1, rs2, rd) | |
313 #define vis_nands(rs1,rs2,rd) vis_ss2s(0x6f, rs1, rs2, rd) | |
314 #define vis_xor(rs1,rs2,rd) vis_dd2d(0x6c, rs1, rs2, rd) | |
315 #define vis_xors(rs1,rs2,rd) vis_ss2s(0x6d, rs1, rs2, rd) | |
316 #define vis_xnor(rs1,rs2,rd) vis_dd2d(0x72, rs1, rs2, rd) | |
317 #define vis_xnors(rs1,rs2,rd) vis_ss2s(0x73, rs1, rs2, rd) | |
318 #define vis_ornot1(rs1,rs2,rd) vis_dd2d(0x7a, rs1, rs2, rd) | |
319 #define vis_ornot1s(rs1,rs2,rd) vis_ss2s(0x7b, rs1, rs2, rd) | |
320 #define vis_ornot2(rs1,rs2,rd) vis_dd2d(0x76, rs1, rs2, rd) | |
321 #define vis_ornot2s(rs1,rs2,rd) vis_ss2s(0x77, rs1, rs2, rd) | |
322 #define vis_andnot1(rs1,rs2,rd) vis_dd2d(0x68, rs1, rs2, rd) | |
323 #define vis_andnot1s(rs1,rs2,rd) vis_ss2s(0x69, rs1, rs2, rd) | |
324 #define vis_andnot2(rs1,rs2,rd) vis_dd2d(0x64, rs1, rs2, rd) | |
325 #define vis_andnot2s(rs1,rs2,rd) vis_ss2s(0x65, rs1, rs2, rd) | |
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326 |
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327 /* Pixel component distance. */ |
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328 |
2979 | 329 #define vis_pdist(rs1,rs2,rd) vis_dd2d(0x3e, rs1, rs2, rd) |
5163 | 330 |
7760 | 331 #endif /* AVCODEC_SPARC_VIS_H */ |