Mercurial > libavcodec.hg
annotate alpha/motion_est_mvi_asm.S @ 1010:3c110cba4b29 libavcodec
- removed nonsense *.d dependancy stuff, there was already a better 'make dep' support in it
- enabled .depend generation by default, so no need to 'make dep' then...
author | arpi_esp |
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date | Fri, 17 Jan 2003 22:40:00 +0000 |
parents | 107a56aa74f5 |
children | 503496800167 |
rev | line source |
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705
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1 /* |
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2 * Alpha optimized DSP utils |
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3 * Copyright (c) 2002 Falk Hueffner <falk@debian.org> |
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4 * |
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5 * This program is free software; you can redistribute it and/or modify |
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6 * it under the terms of the GNU General Public License as published by |
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7 * the Free Software Foundation; either version 2 of the License, or |
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8 * (at your option) any later version. |
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9 * |
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10 * This program is distributed in the hope that it will be useful, |
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11 * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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13 * GNU General Public License for more details. |
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14 * |
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15 * You should have received a copy of the GNU General Public License |
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16 * along with this program; if not, write to the Free Software |
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17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
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18 */ |
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19 |
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20 #include "regdef.h" |
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21 #ifdef HAVE_AV_CONFIG_H |
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22 #include "config.h" |
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23 #endif |
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24 |
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25 /* Some nicer register names. */ |
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26 #define ta t10 |
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27 #define tb t11 |
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28 #define tc t12 |
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29 #define td AT |
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30 /* Danger: these overlap with the argument list and the return value */ |
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31 #define te a5 |
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32 #define tf a4 |
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33 #define tg a3 |
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34 #define th v0 |
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35 |
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36 .set noat |
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37 .set noreorder |
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38 .arch pca56 |
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39 .text |
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40 |
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41 /***************************************************************************** |
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42 * int pix_abs16x16_mvi_asm(uint8_t *pix1, uint8_t *pix2, int line_size) |
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43 * |
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44 * This code is written with a pca56 in mind. For ev6, one should |
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45 * really take the increased latency of 3 cycles for MVI instructions |
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46 * into account. |
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47 * |
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48 * It is important to keep the loading and first use of a register as |
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49 * far apart as possible, because if a register is accessed before it |
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50 * has been fetched from memory, the CPU will stall. |
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51 */ |
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52 .align 4 |
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53 .globl pix_abs16x16_mvi_asm |
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54 .ent pix_abs16x16_mvi_asm |
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55 pix_abs16x16_mvi_asm: |
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56 .frame sp, 0, ra, 0 |
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57 .prologue 0 |
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58 |
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59 #ifdef HAVE_GPROF |
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60 lda AT, _mcount |
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61 jsr AT, (AT), _mcount |
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62 #endif |
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63 |
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64 and a1, 7, t0 |
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65 clr v0 |
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66 lda a3, 16 |
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67 beq t0, $aligned |
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68 .align 4 |
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69 $unaligned: |
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70 /* Registers: |
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71 line 0: |
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72 t0: left_u -> left lo -> left |
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73 t1: mid |
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74 t2: right_u -> right hi -> right |
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75 t3: ref left |
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76 t4: ref right |
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77 line 1: |
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78 t5: left_u -> left lo -> left |
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79 t6: mid |
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80 t7: right_u -> right hi -> right |
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81 t8: ref left |
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82 t9: ref right |
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83 temp: |
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84 ta: left hi |
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85 tb: right lo |
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86 tc: error left |
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87 td: error right */ |
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88 |
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89 /* load line 0 */ |
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90 ldq_u t0, 0(a1) # left_u |
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91 ldq_u t1, 8(a1) # mid |
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92 ldq_u t2, 16(a1) # right_u |
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93 ldq t3, 0(a0) # ref left |
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94 ldq t4, 8(a0) # ref right |
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95 addq a0, a2, a0 # pix1 |
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96 addq a1, a2, a1 # pix2 |
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97 /* load line 1 */ |
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98 ldq_u t5, 0(a1) # left_u |
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99 ldq_u t6, 8(a1) # mid |
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100 ldq_u t7, 16(a1) # right_u |
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101 ldq t8, 0(a0) # ref left |
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102 ldq t9, 8(a0) # ref right |
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103 addq a0, a2, a0 # pix1 |
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104 addq a1, a2, a1 # pix2 |
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105 /* calc line 0 */ |
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106 extql t0, a1, t0 # left lo |
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107 extqh t1, a1, ta # left hi |
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108 extql t1, a1, tb # right lo |
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109 or t0, ta, t0 # left |
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110 extqh t2, a1, t2 # right hi |
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111 perr t3, t0, tc # error left |
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112 or t2, tb, t2 # right |
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113 perr t4, t2, td # error right |
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114 addq v0, tc, v0 # add error left |
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115 addq v0, td, v0 # add error left |
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116 /* calc line 1 */ |
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117 extql t5, a1, t5 # left lo |
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118 extqh t6, a1, ta # left hi |
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119 extql t6, a1, tb # right lo |
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120 or t5, ta, t5 # left |
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121 extqh t7, a1, t7 # right hi |
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122 perr t8, t5, tc # error left |
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123 or t7, tb, t7 # right |
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124 perr t9, t7, td # error right |
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125 addq v0, tc, v0 # add error left |
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126 addq v0, td, v0 # add error left |
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127 /* loop */ |
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128 subq a3, 2, a3 # h -= 2 |
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129 bne a3, $unaligned |
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130 ret |
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131 |
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132 .align 4 |
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133 $aligned: |
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134 /* load line 0 */ |
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135 ldq t0, 0(a1) # left |
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136 ldq t1, 8(a1) # right |
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137 addq a1, a2, a1 # pix2 |
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138 ldq t2, 0(a0) # ref left |
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139 ldq t3, 8(a0) # ref right |
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140 addq a0, a2, a0 # pix1 |
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141 /* load line 1 */ |
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142 ldq t4, 0(a1) # left |
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143 ldq t5, 8(a1) # right |
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144 addq a1, a2, a1 # pix2 |
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145 ldq t6, 0(a0) # ref left |
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146 ldq t7, 8(a0) # ref right |
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147 addq a0, a2, a0 # pix1 |
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148 /* load line 2 */ |
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149 ldq t8, 0(a1) # left |
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150 ldq t9, 8(a1) # right |
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151 addq a1, a2, a1 # pix2 |
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152 ldq ta, 0(a0) # ref left |
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153 ldq tb, 8(a0) # ref right |
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154 addq a0, a2, a0 # pix1 |
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155 /* load line 3 */ |
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156 ldq tc, 0(a1) # left |
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157 ldq td, 8(a1) # right |
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158 addq a1, a2, a1 # pix2 |
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159 ldq te, 0(a0) # ref left |
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160 ldq tf, 8(a0) # ref right |
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161 /* calc line 0 */ |
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162 perr t0, t2, t0 # error left |
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163 addq a0, a2, a0 # pix1 |
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164 perr t1, t3, t1 # error right |
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165 addq v0, t0, v0 # add error left |
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166 /* calc line 1 */ |
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167 perr t4, t6, t0 # error left |
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168 addq v0, t1, v0 # add error right |
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169 perr t5, t7, t1 # error right |
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170 addq v0, t0, v0 # add error left |
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171 /* calc line 2 */ |
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172 perr t8, ta, t0 # error left |
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173 addq v0, t1, v0 # add error right |
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174 perr t9, tb, t1 # error right |
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175 addq v0, t0, v0 # add error left |
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176 /* calc line 3 */ |
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177 perr tc, te, t0 # error left |
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178 addq v0, t1, v0 # add error right |
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179 perr td, tf, t1 # error right |
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180 addq v0, t0, v0 # add error left |
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181 addq v0, t1, v0 # add error right |
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182 /* loop */ |
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183 subq a3, 4, a3 # h -= 4 |
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184 bne a3, $aligned |
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185 ret |
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186 .end pix_abs16x16_mvi_asm |