annotate i386/vc1dsp_mmx.c @ 6007:3c37faa04193 libavcodec

Add 4x4 IDCT
author kostya
date Sun, 09 Dec 2007 05:54:59 +0000
parents db875a610973
children 151508a72dd7
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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1 /*
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2 * VC-1 and WMV3 - DSP functions MMX-optimized
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3 * Copyright (c) 2007 Christophe GISQUET <christophe.gisquet@free.fr>
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4 *
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5 * Permission is hereby granted, free of charge, to any person
6ce8f15fc02b add VC-1 MMX DSP functions, under MIT license.
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6 * obtaining a copy of this software and associated documentation
6ce8f15fc02b add VC-1 MMX DSP functions, under MIT license.
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7 * files (the "Software"), to deal in the Software without
6ce8f15fc02b add VC-1 MMX DSP functions, under MIT license.
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8 * restriction, including without limitation the rights to use,
6ce8f15fc02b add VC-1 MMX DSP functions, under MIT license.
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9 * copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 * copies of the Software, and to permit persons to whom the
6ce8f15fc02b add VC-1 MMX DSP functions, under MIT license.
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11 * Software is furnished to do so, subject to the following
6ce8f15fc02b add VC-1 MMX DSP functions, under MIT license.
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12 * conditions:
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13 *
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14 * The above copyright notice and this permission notice shall be
6ce8f15fc02b add VC-1 MMX DSP functions, under MIT license.
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15 * included in all copies or substantial portions of the Software.
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16 *
6ce8f15fc02b add VC-1 MMX DSP functions, under MIT license.
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17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
6ce8f15fc02b add VC-1 MMX DSP functions, under MIT license.
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18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
6ce8f15fc02b add VC-1 MMX DSP functions, under MIT license.
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19 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
6ce8f15fc02b add VC-1 MMX DSP functions, under MIT license.
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20 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
6ce8f15fc02b add VC-1 MMX DSP functions, under MIT license.
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21 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
6ce8f15fc02b add VC-1 MMX DSP functions, under MIT license.
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22 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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24 * OTHER DEALINGS IN THE SOFTWARE.
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25 */
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26
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27 #include "dsputil.h"
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28 #include "dsputil_mmx.h"
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29 #include "x86_cpu.h"
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30
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31 /** Add rounder from mm7 to mm3 and pack result at destination */
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32 #define NORMALIZE_MMX(SHIFT) \
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33 "paddw %%mm7, %%mm3 \n\t" /* +bias-r */ \
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34 "paddw %%mm7, %%mm4 \n\t" /* +bias-r */ \
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35 "psraw "SHIFT", %%mm3 \n\t" \
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36 "psraw "SHIFT", %%mm4 \n\t"
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37
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38 #define TRANSFER_DO_PACK \
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39 "packuswb %%mm4, %%mm3 \n\t" \
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40 "movq %%mm3, (%2) \n\t"
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41
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42 #define TRANSFER_DONT_PACK \
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43 "movq %%mm3, 0(%2) \n\t" \
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44 "movq %%mm4, 8(%2) \n\t"
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45
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46 /** @see MSPEL_FILTER13_CORE for use as UNPACK macro */
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47 #define DO_UNPACK(reg) "punpcklbw %%mm0, " reg "\n\t"
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48 #define DONT_UNPACK(reg)
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49
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50 /** Compute the rounder 32-r or 8-r and unpacks it to mm7 */
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51 #define LOAD_ROUNDER_MMX(ROUND) \
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52 "movd "ROUND", %%mm7 \n\t" \
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53 "punpcklwd %%mm7, %%mm7 \n\t" \
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54 "punpckldq %%mm7, %%mm7 \n\t"
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55
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56 #define SHIFT2_LINE(OFF, R0,R1,R2,R3) \
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57 "paddw %%mm"#R2", %%mm"#R1" \n\t" \
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58 "movd (%1,%4), %%mm"#R0" \n\t" \
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59 "pmullw %%mm6, %%mm"#R1" \n\t" \
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60 "punpcklbw %%mm0, %%mm"#R0" \n\t" \
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61 "movd (%1,%3), %%mm"#R3" \n\t" \
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62 "psubw %%mm"#R0", %%mm"#R1" \n\t" \
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63 "punpcklbw %%mm0, %%mm"#R3" \n\t" \
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64 "paddw %%mm7, %%mm"#R1" \n\t" \
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65 "psubw %%mm"#R3", %%mm"#R1" \n\t" \
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66 "psraw %5, %%mm"#R1" \n\t" \
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67 "movq %%mm"#R1", "#OFF"(%2) \n\t" \
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68 "add %3, %1 \n\t"
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69
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70 DECLARE_ALIGNED_16(static const uint64_t, fact_9) = 0x0009000900090009ULL;
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71
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72 /** Sacrifying mm6 allows to pipeline loads from src */
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73 static void vc1_put_ver_16b_shift2_mmx(int16_t *dst,
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74 const uint8_t *src, long int stride,
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75 int rnd, int64_t shift)
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76 {
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77 int w = 3;
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78
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79 asm volatile(
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80 LOAD_ROUNDER_MMX("%6")
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81 "movq %7, %%mm6 \n\t"
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82 "1: \n\t"
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83 "movd (%1), %%mm2 \n\t"
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84 "add %3, %1 \n\t"
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85 "movd (%1), %%mm3 \n\t"
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86 "punpcklbw %%mm0, %%mm2 \n\t"
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87 "punpcklbw %%mm0, %%mm3 \n\t"
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88 SHIFT2_LINE( 0, 1, 2, 3, 4)
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89 SHIFT2_LINE( 24, 2, 3, 4, 1)
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90 SHIFT2_LINE( 48, 3, 4, 1, 2)
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91 SHIFT2_LINE( 72, 4, 1, 2, 3)
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92 SHIFT2_LINE( 96, 1, 2, 3, 4)
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93 SHIFT2_LINE(120, 2, 3, 4, 1)
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94 SHIFT2_LINE(144, 3, 4, 1, 2)
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95 SHIFT2_LINE(168, 4, 1, 2, 3)
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96 "sub %8, %1 \n\t"
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97 "add $8, %2 \n\t"
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98 "dec %0 \n\t"
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99 "jnz 1b \n\t"
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100 : "+g"(w), "+r"(src), "+r"(dst)
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101 : "r"(stride), "r"(-2*stride), "m"(shift),
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102 "m"(rnd), "m"(fact_9), "g"(9*stride-4)
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103 : "memory"
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104 );
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105 }
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106
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107 /**
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108 * Data is already unpacked, so some operations can directly be made from
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109 * memory.
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110 */
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111 static void vc1_put_hor_16b_shift2_mmx(uint8_t *dst, long int stride,
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112 const int16_t *src, int rnd)
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113 {
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114 int h = 8;
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115
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116 src -= 1;
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117 rnd -= (-1+9+9-1)*1024; /* Add -1024 bias */
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118 asm volatile(
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119 LOAD_ROUNDER_MMX("%4")
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120 "movq %6, %%mm6 \n\t"
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121 "movq %5, %%mm5 \n\t"
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122 "1: \n\t"
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123 "movq 2*0+0(%1), %%mm1 \n\t"
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124 "movq 2*0+8(%1), %%mm2 \n\t"
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125 "movq 2*1+0(%1), %%mm3 \n\t"
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126 "movq 2*1+8(%1), %%mm4 \n\t"
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127 "paddw 2*3+0(%1), %%mm1 \n\t"
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128 "paddw 2*3+8(%1), %%mm2 \n\t"
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129 "paddw 2*2+0(%1), %%mm3 \n\t"
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130 "paddw 2*2+8(%1), %%mm4 \n\t"
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131 "pmullw %%mm5, %%mm3 \n\t"
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132 "pmullw %%mm5, %%mm4 \n\t"
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133 "psubw %%mm1, %%mm3 \n\t"
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134 "psubw %%mm2, %%mm4 \n\t"
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135 NORMALIZE_MMX("$7")
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136 /* Remove bias */
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137 "paddw %%mm6, %%mm3 \n\t"
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138 "paddw %%mm6, %%mm4 \n\t"
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139 TRANSFER_DO_PACK
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140 "add $24, %1 \n\t"
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141 "add %3, %2 \n\t"
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142 "dec %0 \n\t"
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143 "jnz 1b \n\t"
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144 : "+g"(h), "+r" (src), "+r" (dst)
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145 : "g"(stride), "m"(rnd), "m"(fact_9), "m"(ff_pw_128)
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146 : "memory"
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147 );
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148 }
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149
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150
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151 /**
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152 * Purely vertical or horizontal 1/2 shift interpolation.
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153 * Sacrify mm6 for *9 factor.
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154 */
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155 static void vc1_put_shift2_mmx(uint8_t *dst, const uint8_t *src,
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156 long int stride, int rnd, long int offset)
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157 {
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158 int h = 8;
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159
5933
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160 rnd = 8-rnd;
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161 asm volatile(
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162 LOAD_ROUNDER_MMX("%6")
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163 "movq %8, %%mm6 \n\t"
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164 "1: \n\t"
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165 "movd 0(%1 ), %%mm3 \n\t"
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166 "movd 4(%1 ), %%mm4 \n\t"
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167 "movd 0(%1,%3), %%mm1 \n\t"
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168 "movd 4(%1,%3), %%mm2 \n\t"
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169 "add %3, %1 \n\t"
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170 "punpcklbw %%mm0, %%mm3 \n\t"
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171 "punpcklbw %%mm0, %%mm4 \n\t"
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172 "punpcklbw %%mm0, %%mm1 \n\t"
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173 "punpcklbw %%mm0, %%mm2 \n\t"
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174 "paddw %%mm1, %%mm3 \n\t"
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175 "paddw %%mm2, %%mm4 \n\t"
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176 "movd 0(%1,%4), %%mm1 \n\t"
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177 "movd 4(%1,%4), %%mm2 \n\t"
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178 "pmullw %%mm6, %%mm3 \n\t" /* 0,9,9,0*/
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179 "pmullw %%mm6, %%mm4 \n\t" /* 0,9,9,0*/
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180 "punpcklbw %%mm0, %%mm1 \n\t"
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181 "punpcklbw %%mm0, %%mm2 \n\t"
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182 "psubw %%mm1, %%mm3 \n\t" /*-1,9,9,0*/
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183 "psubw %%mm2, %%mm4 \n\t" /*-1,9,9,0*/
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184 "movd 0(%1,%3), %%mm1 \n\t"
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185 "movd 4(%1,%3), %%mm2 \n\t"
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186 "punpcklbw %%mm0, %%mm1 \n\t"
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187 "punpcklbw %%mm0, %%mm2 \n\t"
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188 "psubw %%mm1, %%mm3 \n\t" /*-1,9,9,-1*/
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189 "psubw %%mm2, %%mm4 \n\t" /*-1,9,9,-1*/
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190 NORMALIZE_MMX("$4")
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191 TRANSFER_DO_PACK
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192 "add %7, %1 \n\t"
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193 "add %5, %2 \n\t"
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194 "dec %0 \n\t"
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195 "jnz 1b \n\t"
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196 : "+g"(h), "+r"(src), "+r"(dst)
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197 : "r"(offset), "r"(-2*offset), "g"(stride), "m"(rnd),
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198 "g"(stride-offset), "m"(fact_9)
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199 : "memory"
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200 );
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201 }
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202
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203 /**
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204 * Filter coefficients made global to allow access by all 1 or 3 quarter shift
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205 * interpolation functions.
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206 */
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207 DECLARE_ALIGNED_16(static const uint64_t, fact_53) = 0x0035003500350035ULL;
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208 DECLARE_ALIGNED_16(static const uint64_t, fact_18) = 0x0012001200120012ULL;
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209
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210 /**
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211 * Core of the 1/4 and 3/4 shift bicubic interpolation.
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212 *
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213 * @param UNPACK Macro unpacking arguments from 8 to 16bits (can be empty).
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214 * @param MOVQ "movd 1" or "movq 2", if data read is already unpacked.
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215 * @param A1 Address of 1st tap (beware of unpacked/packed).
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216 * @param A2 Address of 2nd tap
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217 * @param A3 Address of 3rd tap
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218 * @param A4 Address of 4th tap
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219 */
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220 #define MSPEL_FILTER13_CORE(UNPACK, MOVQ, A1, A2, A3, A4, POS) \
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221 MOVQ "*0+"A1", %%mm1 \n\t" \
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222 MOVQ "*4+"A1", %%mm2 \n\t" \
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223 UNPACK("%%mm1") \
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224 UNPACK("%%mm2") \
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225 "pmullw "POS", %%mm1 \n\t" \
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226 "pmullw "POS", %%mm2 \n\t" \
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227 MOVQ "*0+"A2", %%mm3 \n\t" \
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228 MOVQ "*4+"A2", %%mm4 \n\t" \
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229 UNPACK("%%mm3") \
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230 UNPACK("%%mm4") \
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231 "pmullw %%mm6, %%mm3 \n\t" /* *18 */ \
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232 "pmullw %%mm6, %%mm4 \n\t" /* *18 */ \
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233 "psubw %%mm1, %%mm3 \n\t" /* 18,-3 */ \
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234 "psubw %%mm2, %%mm4 \n\t" /* 18,-3 */ \
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235 MOVQ "*0+"A4", %%mm1 \n\t" \
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236 MOVQ "*4+"A4", %%mm2 \n\t" \
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237 UNPACK("%%mm1") \
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238 UNPACK("%%mm2") \
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239 "psllw $2, %%mm1 \n\t" /* 4* */ \
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240 "psllw $2, %%mm2 \n\t" /* 4* */ \
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241 "psubw %%mm1, %%mm3 \n\t" /* -4,18,-3 */ \
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242 "psubw %%mm2, %%mm4 \n\t" /* -4,18,-3 */ \
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243 MOVQ "*0+"A3", %%mm1 \n\t" \
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244 MOVQ "*4+"A3", %%mm2 \n\t" \
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245 UNPACK("%%mm1") \
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246 UNPACK("%%mm2") \
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247 "pmullw %%mm5, %%mm1 \n\t" /* *53 */ \
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248 "pmullw %%mm5, %%mm2 \n\t" /* *53 */ \
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249 "paddw %%mm1, %%mm3 \n\t" /* 4,53,18,-3 */ \
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250 "paddw %%mm2, %%mm4 \n\t" /* 4,53,18,-3 */
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251
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252 /**
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253 * Macro to build the vertical 16bits version of vc1_put_shift[13].
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254 * Here, offset=src_stride. Parameters passed A1 to A4 must use
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255 * %3 (src_stride) and %4 (3*src_stride).
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256 *
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257 * @param NAME Either 1 or 3
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258 * @see MSPEL_FILTER13_CORE for information on A1->A4
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259 */
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260 #define MSPEL_FILTER13_VER_16B(NAME, A1, A2, A3, A4) \
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261 static void \
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262 vc1_put_ver_16b_ ## NAME ## _mmx(int16_t *dst, const uint8_t *src, \
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263 long int src_stride, \
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264 int rnd, int64_t shift) \
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265 { \
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266 int h = 8; \
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267 src -= src_stride; \
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268 asm volatile( \
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269 LOAD_ROUNDER_MMX("%5") \
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270 "movq %7, %%mm5 \n\t" \
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271 "movq %8, %%mm6 \n\t" \
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272 ASMALIGN(3) \
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273 "1: \n\t" \
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274 MSPEL_FILTER13_CORE(DO_UNPACK, "movd 1", A1, A2, A3, A4, "%9") \
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275 NORMALIZE_MMX("%6") \
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276 TRANSFER_DONT_PACK \
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277 /* Last 3 (in fact 4) bytes on the line */ \
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278 "movd 8+"A1", %%mm1 \n\t" \
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279 DO_UNPACK("%%mm1") \
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280 "movq %%mm1, %%mm3 \n\t" \
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281 "paddw %%mm1, %%mm1 \n\t" \
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282 "paddw %%mm3, %%mm1 \n\t" /* 3* */ \
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283 "movd 8+"A2", %%mm3 \n\t" \
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284 DO_UNPACK("%%mm3") \
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285 "pmullw %%mm6, %%mm3 \n\t" /* *18 */ \
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286 "psubw %%mm1, %%mm3 \n\t" /*18,-3 */ \
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287 "movd 8+"A3", %%mm1 \n\t" \
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288 DO_UNPACK("%%mm1") \
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289 "pmullw %%mm5, %%mm1 \n\t" /* *53 */ \
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290 "paddw %%mm1, %%mm3 \n\t" /*53,18,-3 */ \
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291 "movd 8+"A4", %%mm1 \n\t" \
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292 DO_UNPACK("%%mm1") \
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diff changeset
293 "psllw $2, %%mm1 \n\t" /* 4* */ \
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gpoirier
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diff changeset
294 "psubw %%mm1, %%mm3 \n\t" \
6ce8f15fc02b add VC-1 MMX DSP functions, under MIT license.
gpoirier
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diff changeset
295 "paddw %%mm7, %%mm3 \n\t" \
6ce8f15fc02b add VC-1 MMX DSP functions, under MIT license.
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diff changeset
296 "psraw %6, %%mm3 \n\t" \
6ce8f15fc02b add VC-1 MMX DSP functions, under MIT license.
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diff changeset
297 "movq %%mm3, 16(%2) \n\t" \
6ce8f15fc02b add VC-1 MMX DSP functions, under MIT license.
gpoirier
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diff changeset
298 "add %3, %1 \n\t" \
6ce8f15fc02b add VC-1 MMX DSP functions, under MIT license.
gpoirier
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diff changeset
299 "add $24, %2 \n\t" \
6ce8f15fc02b add VC-1 MMX DSP functions, under MIT license.
gpoirier
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diff changeset
300 "dec %0 \n\t" \
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gpoirier
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diff changeset
301 "jnz 1b \n\t" \
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302 : "+g"(h), "+r" (src), "+r" (dst) \
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303 : "r"(src_stride), "r"(3*src_stride), \
6ce8f15fc02b add VC-1 MMX DSP functions, under MIT license.
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304 "m"(rnd), "m"(shift), \
6ce8f15fc02b add VC-1 MMX DSP functions, under MIT license.
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305 "m"(fact_53), "m"(fact_18), "m"(ff_pw_3) \
6ce8f15fc02b add VC-1 MMX DSP functions, under MIT license.
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306 : "memory" \
6ce8f15fc02b add VC-1 MMX DSP functions, under MIT license.
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307 ); \
6ce8f15fc02b add VC-1 MMX DSP functions, under MIT license.
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308 }
6ce8f15fc02b add VC-1 MMX DSP functions, under MIT license.
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309
6ce8f15fc02b add VC-1 MMX DSP functions, under MIT license.
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310 /**
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311 * Macro to build the horizontal 16bits version of vc1_put_shift[13].
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312 * Here, offset=16bits, so parameters passed A1 to A4 should be simple.
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313 *
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314 * @param NAME Either 1 or 3
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315 * @see MSPEL_FILTER13_CORE for information on A1->A4
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316 */
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317 #define MSPEL_FILTER13_HOR_16B(NAME, A1, A2, A3, A4) \
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318 static void \
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319 vc1_put_hor_16b_ ## NAME ## _mmx(uint8_t *dst, long int stride, \
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320 const int16_t *src, int rnd) \
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321 { \
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322 int h = 8; \
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323 src -= 1; \
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324 rnd -= (-4+58+13-3)*256; /* Add -256 bias */ \
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325 asm volatile( \
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326 LOAD_ROUNDER_MMX("%4") \
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327 "movq %6, %%mm6 \n\t" \
6ce8f15fc02b add VC-1 MMX DSP functions, under MIT license.
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328 "movq %5, %%mm5 \n\t" \
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329 ASMALIGN(3) \
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330 "1: \n\t" \
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331 MSPEL_FILTER13_CORE(DONT_UNPACK, "movq 2", A1, A2, A3, A4, "%8")\
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332 NORMALIZE_MMX("$7") \
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333 /* Remove bias */ \
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334 "paddw %7, %%mm3 \n\t" \
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diff changeset
335 "paddw %7, %%mm4 \n\t" \
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336 TRANSFER_DO_PACK \
6ce8f15fc02b add VC-1 MMX DSP functions, under MIT license.
gpoirier
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diff changeset
337 "add $24, %1 \n\t" \
6ce8f15fc02b add VC-1 MMX DSP functions, under MIT license.
gpoirier
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diff changeset
338 "add %3, %2 \n\t" \
6ce8f15fc02b add VC-1 MMX DSP functions, under MIT license.
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diff changeset
339 "dec %0 \n\t" \
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340 "jnz 1b \n\t" \
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341 : "+g"(h), "+r" (src), "+r" (dst) \
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342 : "g"(stride), "m"(rnd), "m"(fact_53), "m"(fact_18), \
6ce8f15fc02b add VC-1 MMX DSP functions, under MIT license.
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343 "m"(ff_pw_128), "m"(ff_pw_3) \
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344 : "memory" \
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345 ); \
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346 }
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347
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348 /**
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349 * Macro to build the 8bits, any direction, version of vc1_put_shift[13].
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350 * Here, offset=src_stride. Parameters passed A1 to A4 must use
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351 * %3 (offset) and %4 (3*offset).
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352 *
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353 * @param NAME Either 1 or 3
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354 * @see MSPEL_FILTER13_CORE for information on A1->A4
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355 */
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356 #define MSPEL_FILTER13_8B(NAME, A1, A2, A3, A4) \
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357 static void \
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358 vc1_put_## NAME ## _mmx(uint8_t *dst, const uint8_t *src, \
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359 long int stride, int rnd, long int offset) \
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360 { \
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361 int h = 8; \
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362 src -= offset; \
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363 rnd = 32-rnd; \
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364 asm volatile ( \
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365 LOAD_ROUNDER_MMX("%6") \
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366 "movq %7, %%mm5 \n\t" \
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367 "movq %8, %%mm6 \n\t" \
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368 ASMALIGN(3) \
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369 "1: \n\t" \
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370 MSPEL_FILTER13_CORE(DO_UNPACK, "movd 1", A1, A2, A3, A4, "%9")\
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371 NORMALIZE_MMX("$6") \
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372 TRANSFER_DO_PACK \
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373 "add %5, %1 \n\t" \
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diff changeset
374 "add %5, %2 \n\t" \
6ce8f15fc02b add VC-1 MMX DSP functions, under MIT license.
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diff changeset
375 "dec %0 \n\t" \
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376 "jnz 1b \n\t" \
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377 : "+g"(h), "+r" (src), "+r" (dst) \
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378 : "r"(offset), "r"(3*offset), "g"(stride), "m"(rnd), \
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379 "m"(fact_53), "m"(fact_18), "m"(ff_pw_3) \
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380 : "memory" \
6ce8f15fc02b add VC-1 MMX DSP functions, under MIT license.
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381 ); \
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382 }
6ce8f15fc02b add VC-1 MMX DSP functions, under MIT license.
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383
6ce8f15fc02b add VC-1 MMX DSP functions, under MIT license.
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384 /** 1/4 shift bicubic interpolation */
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385 MSPEL_FILTER13_8B (shift1, "0(%1,%4 )", "0(%1,%3,2)", "0(%1,%3 )", "0(%1 )")
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386 MSPEL_FILTER13_VER_16B(shift1, "0(%1,%4 )", "0(%1,%3,2)", "0(%1,%3 )", "0(%1 )")
6ce8f15fc02b add VC-1 MMX DSP functions, under MIT license.
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387 MSPEL_FILTER13_HOR_16B(shift1, "2*3(%1)", "2*2(%1)", "2*1(%1)", "2*0(%1)")
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388
6ce8f15fc02b add VC-1 MMX DSP functions, under MIT license.
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diff changeset
389 /** 3/4 shift bicubic interpolation */
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390 MSPEL_FILTER13_8B (shift3, "0(%1 )", "0(%1,%3 )", "0(%1,%3,2)", "0(%1,%4 )")
6ce8f15fc02b add VC-1 MMX DSP functions, under MIT license.
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391 MSPEL_FILTER13_VER_16B(shift3, "0(%1 )", "0(%1,%3 )", "0(%1,%3,2)", "0(%1,%4 )")
6ce8f15fc02b add VC-1 MMX DSP functions, under MIT license.
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392 MSPEL_FILTER13_HOR_16B(shift3, "2*0(%1)", "2*1(%1)", "2*2(%1)", "2*3(%1)")
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393
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394 typedef void (*vc1_mspel_mc_filter_ver_16bits)(int16_t *dst, const uint8_t *src, long int src_stride, int rnd, int64_t shift);
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395 typedef void (*vc1_mspel_mc_filter_hor_16bits)(uint8_t *dst, long int dst_stride, const int16_t *src, int rnd);
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396 typedef void (*vc1_mspel_mc_filter_8bits)(uint8_t *dst, const uint8_t *src, long int stride, int rnd, long int offset);
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397
6ce8f15fc02b add VC-1 MMX DSP functions, under MIT license.
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398 /**
6ce8f15fc02b add VC-1 MMX DSP functions, under MIT license.
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399 * Interpolates fractional pel values by applying proper vertical then
6ce8f15fc02b add VC-1 MMX DSP functions, under MIT license.
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400 * horizontal filter.
6ce8f15fc02b add VC-1 MMX DSP functions, under MIT license.
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401 *
6ce8f15fc02b add VC-1 MMX DSP functions, under MIT license.
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402 * @param dst Destination buffer for interpolated pels.
6ce8f15fc02b add VC-1 MMX DSP functions, under MIT license.
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403 * @param src Source buffer.
6ce8f15fc02b add VC-1 MMX DSP functions, under MIT license.
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404 * @param stride Stride for both src and dst buffers.
6ce8f15fc02b add VC-1 MMX DSP functions, under MIT license.
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405 * @param hmode Horizontal filter (expressed in quarter pixels shift).
6ce8f15fc02b add VC-1 MMX DSP functions, under MIT license.
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406 * @param hmode Vertical filter.
6ce8f15fc02b add VC-1 MMX DSP functions, under MIT license.
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407 * @param rnd Rounding bias.
6ce8f15fc02b add VC-1 MMX DSP functions, under MIT license.
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408 */
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409 static void vc1_mspel_mc(uint8_t *dst, const uint8_t *src, int stride,
6ce8f15fc02b add VC-1 MMX DSP functions, under MIT license.
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410 int hmode, int vmode, int rnd)
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411 {
6ce8f15fc02b add VC-1 MMX DSP functions, under MIT license.
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412 static const vc1_mspel_mc_filter_ver_16bits vc1_put_shift_ver_16bits[] =
6ce8f15fc02b add VC-1 MMX DSP functions, under MIT license.
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413 { NULL, vc1_put_ver_16b_shift1_mmx, vc1_put_ver_16b_shift2_mmx, vc1_put_ver_16b_shift3_mmx };
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414 static const vc1_mspel_mc_filter_hor_16bits vc1_put_shift_hor_16bits[] =
6ce8f15fc02b add VC-1 MMX DSP functions, under MIT license.
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415 { NULL, vc1_put_hor_16b_shift1_mmx, vc1_put_hor_16b_shift2_mmx, vc1_put_hor_16b_shift3_mmx };
6ce8f15fc02b add VC-1 MMX DSP functions, under MIT license.
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416 static const vc1_mspel_mc_filter_8bits vc1_put_shift_8bits[] =
6ce8f15fc02b add VC-1 MMX DSP functions, under MIT license.
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417 { NULL, vc1_put_shift1_mmx, vc1_put_shift2_mmx, vc1_put_shift3_mmx };
6ce8f15fc02b add VC-1 MMX DSP functions, under MIT license.
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418
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419 asm volatile(
6ce8f15fc02b add VC-1 MMX DSP functions, under MIT license.
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420 "pxor %%mm0, %%mm0 \n\t"
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421 ::: "memory"
6ce8f15fc02b add VC-1 MMX DSP functions, under MIT license.
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422 );
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423
6ce8f15fc02b add VC-1 MMX DSP functions, under MIT license.
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424 if (vmode) { /* Vertical filter to apply */
6ce8f15fc02b add VC-1 MMX DSP functions, under MIT license.
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425 if (hmode) { /* Horizontal filter to apply, output to tmp */
6ce8f15fc02b add VC-1 MMX DSP functions, under MIT license.
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426 static const int shift_value[] = { 0, 5, 1, 5 };
6ce8f15fc02b add VC-1 MMX DSP functions, under MIT license.
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427 int shift = (shift_value[hmode]+shift_value[vmode])>>1;
6ce8f15fc02b add VC-1 MMX DSP functions, under MIT license.
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428 int r;
6ce8f15fc02b add VC-1 MMX DSP functions, under MIT license.
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429 DECLARE_ALIGNED_16(int16_t, tmp[12*8]);
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430
6ce8f15fc02b add VC-1 MMX DSP functions, under MIT license.
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431 r = (1<<(shift-1)) + rnd-1;
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432 vc1_put_shift_ver_16bits[vmode](tmp, src-1, stride, r, shift);
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433
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434 vc1_put_shift_hor_16bits[hmode](dst, stride, tmp+1, 64-rnd);
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435 return;
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436 }
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437 else { /* No horizontal filter, output 8 lines to dst */
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438 vc1_put_shift_8bits[vmode](dst, src, stride, 1-rnd, stride);
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439 return;
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440 }
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441 }
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442
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443 /* Horizontal mode with no vertical mode */
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444 vc1_put_shift_8bits[hmode](dst, src, stride, rnd, 1);
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445 }
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446
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447 void ff_put_vc1_mspel_mc00_mmx(uint8_t *dst, const uint8_t *src, int stride, int rnd);
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448
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449 /** Macro to ease bicubic filter interpolation functions declarations */
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450 #define DECLARE_FUNCTION(a, b) \
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451 static void put_vc1_mspel_mc ## a ## b ## _mmx(uint8_t *dst, const uint8_t *src, int stride, int rnd) { \
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452 vc1_mspel_mc(dst, src, stride, a, b, rnd); \
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453 }
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454
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455 DECLARE_FUNCTION(0, 1)
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456 DECLARE_FUNCTION(0, 2)
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457 DECLARE_FUNCTION(0, 3)
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458
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459 DECLARE_FUNCTION(1, 0)
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460 DECLARE_FUNCTION(1, 1)
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461 DECLARE_FUNCTION(1, 2)
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462 DECLARE_FUNCTION(1, 3)
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463
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464 DECLARE_FUNCTION(2, 0)
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465 DECLARE_FUNCTION(2, 1)
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466 DECLARE_FUNCTION(2, 2)
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467 DECLARE_FUNCTION(2, 3)
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468
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469 DECLARE_FUNCTION(3, 0)
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470 DECLARE_FUNCTION(3, 1)
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471 DECLARE_FUNCTION(3, 2)
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472 DECLARE_FUNCTION(3, 3)
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473
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474 void ff_vc1dsp_init_mmx(DSPContext* dsp, AVCodecContext *avctx) {
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475 dsp->put_vc1_mspel_pixels_tab[ 0] = ff_put_vc1_mspel_mc00_mmx;
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476 dsp->put_vc1_mspel_pixels_tab[ 4] = put_vc1_mspel_mc01_mmx;
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477 dsp->put_vc1_mspel_pixels_tab[ 8] = put_vc1_mspel_mc02_mmx;
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478 dsp->put_vc1_mspel_pixels_tab[12] = put_vc1_mspel_mc03_mmx;
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479
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480 dsp->put_vc1_mspel_pixels_tab[ 1] = put_vc1_mspel_mc10_mmx;
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481 dsp->put_vc1_mspel_pixels_tab[ 5] = put_vc1_mspel_mc11_mmx;
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482 dsp->put_vc1_mspel_pixels_tab[ 9] = put_vc1_mspel_mc12_mmx;
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483 dsp->put_vc1_mspel_pixels_tab[13] = put_vc1_mspel_mc13_mmx;
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484
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485 dsp->put_vc1_mspel_pixels_tab[ 2] = put_vc1_mspel_mc20_mmx;
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486 dsp->put_vc1_mspel_pixels_tab[ 6] = put_vc1_mspel_mc21_mmx;
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487 dsp->put_vc1_mspel_pixels_tab[10] = put_vc1_mspel_mc22_mmx;
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488 dsp->put_vc1_mspel_pixels_tab[14] = put_vc1_mspel_mc23_mmx;
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489
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490 dsp->put_vc1_mspel_pixels_tab[ 3] = put_vc1_mspel_mc30_mmx;
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491 dsp->put_vc1_mspel_pixels_tab[ 7] = put_vc1_mspel_mc31_mmx;
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492 dsp->put_vc1_mspel_pixels_tab[11] = put_vc1_mspel_mc32_mmx;
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493 dsp->put_vc1_mspel_pixels_tab[15] = put_vc1_mspel_mc33_mmx;
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494 }