annotate armv4l/jrevdct_arm.S @ 787:4914252c963a libavcodec

postprocessing cleanup: remove opendivx #ifdefs remove rk1 filter remove unused / obsolete stuff add -1,4,2,4,-1 deinterlacing filter (ffmpeg uses that) threadsafe / no more non-const globals some optimizations different strides for Y,U,V possible remove ebx usage (someone really should fix gcc, this is really lame) change the dering filter slightly (tell me if its worse for any files)
author michael
date Mon, 28 Oct 2002 19:30:58 +0000
parents fefaa96def6e
children ef2149182f1c
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61
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1 /*
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2 C-like prototype :
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3 void j_rev_dct_ARM(DCTBLOCK data)
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4
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5 With DCTBLOCK being a pointer to an array of 64 'signed shorts'
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6
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7 Copyright (c) 2001 Lionel Ulmer (lionel.ulmer@free.fr / bbrox@bbrox.org)
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8
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9 Permission is hereby granted, free of charge, to any person obtaining a copy
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10 of this software and associated documentation files (the "Software"), to deal
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11 in the Software without restriction, including without limitation the rights
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12 to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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13 copies of the Software, and to permit persons to whom the Software is
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14 furnished to do so, subject to the following conditions:
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15
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16 The above copyright notice and this permission notice shall be included in
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17 all copies or substantial portions of the Software.
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18
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19 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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20 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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21 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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22 COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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23 IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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24 CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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25
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26 */
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27 #define FIX_0_298631336 2446
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28 #define FIX_0_541196100 4433
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29 #define FIX_0_765366865 6270
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30 #define FIX_1_175875602 9633
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31 #define FIX_1_501321110 12299
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32 #define FIX_2_053119869 16819
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33 #define FIX_3_072711026 25172
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34 #define FIX_M_0_390180644 -3196
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35 #define FIX_M_0_899976223 -7373
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36 #define FIX_M_1_847759065 -15137
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37 #define FIX_M_1_961570560 -16069
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38 #define FIX_M_2_562915447 -20995
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39 #define FIX_0xFFFF 0xFFFF
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40
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41 #define FIX_0_298631336_ID 0
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42 #define FIX_0_541196100_ID 4
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43 #define FIX_0_765366865_ID 8
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44 #define FIX_1_175875602_ID 12
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45 #define FIX_1_501321110_ID 16
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46 #define FIX_2_053119869_ID 20
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47 #define FIX_3_072711026_ID 24
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48 #define FIX_M_0_390180644_ID 28
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49 #define FIX_M_0_899976223_ID 32
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50 #define FIX_M_1_847759065_ID 36
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51 #define FIX_M_1_961570560_ID 40
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52 #define FIX_M_2_562915447_ID 44
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53 #define FIX_0xFFFF_ID 48
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54 .text
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55 .align
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56
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57 .global j_rev_dct_ARM
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58 j_rev_dct_ARM:
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59 stmdb sp!, { r4 - r12, lr } @ all callee saved regs
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60
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61 sub sp, sp, #4 @ reserve some space on the stack
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62 str r0, [ sp ] @ save the DCT pointer to the stack
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63
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64 mov lr, r0 @ lr = pointer to the current row
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65 mov r12, #8 @ r12 = row-counter
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66 add r11, pc, #(const_array-.-8) @ r11 = base pointer to the constants array
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67 row_loop:
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68 ldrsh r0, [lr, # 0] @ r0 = 'd0'
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69 ldrsh r1, [lr, # 8] @ r1 = 'd1'
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70
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71 @ Optimization for row that have all items except the first set to 0
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72 @ (this works as the DCTELEMS are always 4-byte aligned)
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73 ldr r5, [lr, # 0]
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74 ldr r2, [lr, # 4]
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75 ldr r3, [lr, # 8]
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76 ldr r4, [lr, #12]
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77 orr r3, r3, r4
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78 orr r3, r3, r2
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79 orrs r5, r3, r5
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80 beq end_of_row_loop @ nothing to be done as ALL of them are '0'
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81 orrs r2, r3, r1
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82 beq empty_row
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83
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84 ldrsh r2, [lr, # 2] @ r2 = 'd2'
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85 ldrsh r4, [lr, # 4] @ r4 = 'd4'
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86 ldrsh r6, [lr, # 6] @ r6 = 'd6'
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87
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88 ldr r3, [r11, #FIX_0_541196100_ID]
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89 add r7, r2, r6
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90 ldr r5, [r11, #FIX_M_1_847759065_ID]
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91 mul r7, r3, r7 @ r7 = z1
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92 ldr r3, [r11, #FIX_0_765366865_ID]
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93 mla r6, r5, r6, r7 @ r6 = tmp2
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94 add r5, r0, r4 @ r5 = tmp0
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95 mla r2, r3, r2, r7 @ r2 = tmp3
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96 sub r3, r0, r4 @ r3 = tmp1
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97
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98 add r0, r2, r5, lsl #13 @ r0 = tmp10
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99 rsb r2, r2, r5, lsl #13 @ r2 = tmp13
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100 add r4, r6, r3, lsl #13 @ r4 = tmp11
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101 rsb r3, r6, r3, lsl #13 @ r3 = tmp12
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102
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103 stmdb sp!, { r0, r2, r3, r4 } @ save on the stack tmp10, tmp13, tmp12, tmp11
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104
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105 ldrsh r3, [lr, #10] @ r3 = 'd3'
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106 ldrsh r5, [lr, #12] @ r5 = 'd5'
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107 ldrsh r7, [lr, #14] @ r7 = 'd7'
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108
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109 add r0, r3, r5 @ r0 = 'z2'
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110 add r2, r1, r7 @ r2 = 'z1'
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111 add r4, r3, r7 @ r4 = 'z3'
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112 add r6, r1, r5 @ r6 = 'z4'
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113 ldr r9, [r11, #FIX_1_175875602_ID]
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114 add r8, r4, r6 @ r8 = z3 + z4
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115 ldr r10, [r11, #FIX_M_0_899976223_ID]
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116 mul r8, r9, r8 @ r8 = 'z5'
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117 ldr r9, [r11, #FIX_M_2_562915447_ID]
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118 mul r2, r10, r2 @ r2 = 'z1'
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119 ldr r10, [r11, #FIX_M_1_961570560_ID]
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120 mul r0, r9, r0 @ r0 = 'z2'
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121 ldr r9, [r11, #FIX_M_0_390180644_ID]
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122 mla r4, r10, r4, r8 @ r4 = 'z3'
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123 ldr r10, [r11, #FIX_0_298631336_ID]
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124 mla r6, r9, r6, r8 @ r6 = 'z4'
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125 ldr r9, [r11, #FIX_2_053119869_ID]
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126 mla r7, r10, r7, r2 @ r7 = tmp0 + z1
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127 ldr r10, [r11, #FIX_3_072711026_ID]
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128 mla r5, r9, r5, r0 @ r5 = tmp1 + z2
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129 ldr r9, [r11, #FIX_1_501321110_ID]
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130 mla r3, r10, r3, r0 @ r3 = tmp2 + z2
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131 add r7, r7, r4 @ r7 = tmp0
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132 mla r1, r9, r1, r2 @ r1 = tmp3 + z1
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133 add r5, r5, r6 @ r5 = tmp1
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134 add r3, r3, r4 @ r3 = tmp2
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135 add r1, r1, r6 @ r1 = tmp3
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136
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137 ldmia sp!, { r0, r2, r4, r6 } @ r0 = tmp10 / r2 = tmp13 / r4 = tmp12 / r6 = tmp11
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138 @ r1 = tmp3 / r3 = tmp2 / r5 = tmp1 / r7 = tmp0
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139
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140 @ Compute DESCALE(tmp10 + tmp3, CONST_BITS-PASS1_BITS)
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141 add r8, r0, r1
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142 add r8, r8, #(1<<10)
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143 mov r8, r8, asr #11
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144 strh r8, [lr, # 0]
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145
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146 @ Compute DESCALE(tmp10 - tmp3, CONST_BITS-PASS1_BITS)
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147 sub r8, r0, r1
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148 add r8, r8, #(1<<10)
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149 mov r8, r8, asr #11
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150 strh r8, [lr, #14]
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151
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152 @ Compute DESCALE(tmp11 + tmp2, CONST_BITS-PASS1_BITS)
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153 add r8, r6, r3
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154 add r8, r8, #(1<<10)
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155 mov r8, r8, asr #11
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156 strh r8, [lr, # 2]
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157
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158 @ Compute DESCALE(tmp11 - tmp2, CONST_BITS-PASS1_BITS)
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159 sub r8, r6, r3
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160 add r8, r8, #(1<<10)
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161 mov r8, r8, asr #11
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162 strh r8, [lr, #12]
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163
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164 @ Compute DESCALE(tmp12 + tmp1, CONST_BITS-PASS1_BITS)
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165 add r8, r4, r5
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166 add r8, r8, #(1<<10)
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167 mov r8, r8, asr #11
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168 strh r8, [lr, # 4]
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169
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170 @ Compute DESCALE(tmp12 - tmp1, CONST_BITS-PASS1_BITS)
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171 sub r8, r4, r5
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172 add r8, r8, #(1<<10)
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173 mov r8, r8, asr #11
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174 strh r8, [lr, #10]
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175
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176 @ Compute DESCALE(tmp13 + tmp0, CONST_BITS-PASS1_BITS)
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177 add r8, r2, r7
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178 add r8, r8, #(1<<10)
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179 mov r8, r8, asr #11
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180 strh r8, [lr, # 6]
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181
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182 @ Compute DESCALE(tmp13 - tmp0, CONST_BITS-PASS1_BITS)
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183 sub r8, r2, r7
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184 add r8, r8, #(1<<10)
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185 mov r8, r8, asr #11
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186 strh r8, [lr, # 8]
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187
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188 @ End of row loop
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189 add lr, lr, #16
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190 subs r12, r12, #1
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diff changeset
191 bne row_loop
fefaa96def6e arm specific code
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parents:
diff changeset
192 beq start_column_loop
fefaa96def6e arm specific code
glantau
parents:
diff changeset
193
fefaa96def6e arm specific code
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parents:
diff changeset
194 empty_row:
fefaa96def6e arm specific code
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parents:
diff changeset
195 ldr r1, [r11, #FIX_0xFFFF_ID]
fefaa96def6e arm specific code
glantau
parents:
diff changeset
196 mov r0, r0, lsl #2
fefaa96def6e arm specific code
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parents:
diff changeset
197 and r0, r0, r1
fefaa96def6e arm specific code
glantau
parents:
diff changeset
198 add r0, r0, r0, lsl #16
fefaa96def6e arm specific code
glantau
parents:
diff changeset
199 str r0, [lr, # 0]
fefaa96def6e arm specific code
glantau
parents:
diff changeset
200 str r0, [lr, # 4]
fefaa96def6e arm specific code
glantau
parents:
diff changeset
201 str r0, [lr, # 8]
fefaa96def6e arm specific code
glantau
parents:
diff changeset
202 str r0, [lr, #12]
fefaa96def6e arm specific code
glantau
parents:
diff changeset
203
fefaa96def6e arm specific code
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parents:
diff changeset
204 end_of_row_loop:
fefaa96def6e arm specific code
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parents:
diff changeset
205 @ End of loop
fefaa96def6e arm specific code
glantau
parents:
diff changeset
206 add lr, lr, #16
fefaa96def6e arm specific code
glantau
parents:
diff changeset
207 subs r12, r12, #1
fefaa96def6e arm specific code
glantau
parents:
diff changeset
208 bne row_loop
fefaa96def6e arm specific code
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parents:
diff changeset
209
fefaa96def6e arm specific code
glantau
parents:
diff changeset
210 start_column_loop:
fefaa96def6e arm specific code
glantau
parents:
diff changeset
211 @ Start of column loop
fefaa96def6e arm specific code
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parents:
diff changeset
212 ldr lr, [ sp ]
fefaa96def6e arm specific code
glantau
parents:
diff changeset
213 mov r12, #8
fefaa96def6e arm specific code
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parents:
diff changeset
214 column_loop:
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parents:
diff changeset
215 ldrsh r0, [lr, #( 0*8)] @ r0 = 'd0'
fefaa96def6e arm specific code
glantau
parents:
diff changeset
216 ldrsh r2, [lr, #( 4*8)] @ r2 = 'd2'
fefaa96def6e arm specific code
glantau
parents:
diff changeset
217 ldrsh r4, [lr, #( 8*8)] @ r4 = 'd4'
fefaa96def6e arm specific code
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parents:
diff changeset
218 ldrsh r6, [lr, #(12*8)] @ r6 = 'd6'
fefaa96def6e arm specific code
glantau
parents:
diff changeset
219
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parents:
diff changeset
220 ldr r3, [r11, #FIX_0_541196100_ID]
fefaa96def6e arm specific code
glantau
parents:
diff changeset
221 add r1, r2, r6
fefaa96def6e arm specific code
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parents:
diff changeset
222 ldr r5, [r11, #FIX_M_1_847759065_ID]
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glantau
parents:
diff changeset
223 mul r1, r3, r1 @ r1 = z1
fefaa96def6e arm specific code
glantau
parents:
diff changeset
224 ldr r3, [r11, #FIX_0_765366865_ID]
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glantau
parents:
diff changeset
225 mla r6, r5, r6, r1 @ r6 = tmp2
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glantau
parents:
diff changeset
226 add r5, r0, r4 @ r5 = tmp0
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glantau
parents:
diff changeset
227 mla r2, r3, r2, r1 @ r2 = tmp3
fefaa96def6e arm specific code
glantau
parents:
diff changeset
228 sub r3, r0, r4 @ r3 = tmp1
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glantau
parents:
diff changeset
229
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parents:
diff changeset
230 add r0, r2, r5, lsl #13 @ r0 = tmp10
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parents:
diff changeset
231 rsb r2, r2, r5, lsl #13 @ r2 = tmp13
fefaa96def6e arm specific code
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parents:
diff changeset
232 add r4, r6, r3, lsl #13 @ r4 = tmp11
fefaa96def6e arm specific code
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parents:
diff changeset
233 rsb r6, r6, r3, lsl #13 @ r6 = tmp12
fefaa96def6e arm specific code
glantau
parents:
diff changeset
234
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parents:
diff changeset
235 ldrsh r1, [lr, #( 2*8)] @ r1 = 'd1'
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glantau
parents:
diff changeset
236 ldrsh r3, [lr, #( 6*8)] @ r3 = 'd3'
fefaa96def6e arm specific code
glantau
parents:
diff changeset
237 ldrsh r5, [lr, #(10*8)] @ r5 = 'd5'
fefaa96def6e arm specific code
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parents:
diff changeset
238 ldrsh r7, [lr, #(14*8)] @ r7 = 'd7'
fefaa96def6e arm specific code
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parents:
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239
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parents:
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240 @ Check for empty odd column (happens about 20 to 25 % of the time according to my stats)
fefaa96def6e arm specific code
glantau
parents:
diff changeset
241 orr r9, r1, r3
fefaa96def6e arm specific code
glantau
parents:
diff changeset
242 orr r10, r5, r7
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glantau
parents:
diff changeset
243 orrs r10, r9, r10
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parents:
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244 beq empty_odd_column
fefaa96def6e arm specific code
glantau
parents:
diff changeset
245
fefaa96def6e arm specific code
glantau
parents:
diff changeset
246 stmdb sp!, { r0, r2, r4, r6 } @ save on the stack tmp10, tmp13, tmp12, tmp11
fefaa96def6e arm specific code
glantau
parents:
diff changeset
247
fefaa96def6e arm specific code
glantau
parents:
diff changeset
248 add r0, r3, r5 @ r0 = 'z2'
fefaa96def6e arm specific code
glantau
parents:
diff changeset
249 add r2, r1, r7 @ r2 = 'z1'
fefaa96def6e arm specific code
glantau
parents:
diff changeset
250 add r4, r3, r7 @ r4 = 'z3'
fefaa96def6e arm specific code
glantau
parents:
diff changeset
251 add r6, r1, r5 @ r6 = 'z4'
fefaa96def6e arm specific code
glantau
parents:
diff changeset
252 ldr r9, [r11, #FIX_1_175875602_ID]
fefaa96def6e arm specific code
glantau
parents:
diff changeset
253 add r8, r4, r6
fefaa96def6e arm specific code
glantau
parents:
diff changeset
254 ldr r10, [r11, #FIX_M_0_899976223_ID]
fefaa96def6e arm specific code
glantau
parents:
diff changeset
255 mul r8, r9, r8 @ r8 = 'z5'
fefaa96def6e arm specific code
glantau
parents:
diff changeset
256 ldr r9, [r11, #FIX_M_2_562915447_ID]
fefaa96def6e arm specific code
glantau
parents:
diff changeset
257 mul r2, r10, r2 @ r2 = 'z1'
fefaa96def6e arm specific code
glantau
parents:
diff changeset
258 ldr r10, [r11, #FIX_M_1_961570560_ID]
fefaa96def6e arm specific code
glantau
parents:
diff changeset
259 mul r0, r9, r0 @ r0 = 'z2'
fefaa96def6e arm specific code
glantau
parents:
diff changeset
260 ldr r9, [r11, #FIX_M_0_390180644_ID]
fefaa96def6e arm specific code
glantau
parents:
diff changeset
261 mla r4, r10, r4, r8 @ r4 = 'z3'
fefaa96def6e arm specific code
glantau
parents:
diff changeset
262 ldr r10, [r11, #FIX_0_298631336_ID]
fefaa96def6e arm specific code
glantau
parents:
diff changeset
263 mla r6, r9, r6, r8 @ r6 = 'z4'
fefaa96def6e arm specific code
glantau
parents:
diff changeset
264 ldr r9, [r11, #FIX_2_053119869_ID]
fefaa96def6e arm specific code
glantau
parents:
diff changeset
265 mla r7, r10, r7, r2 @ r7 = tmp0 + z1
fefaa96def6e arm specific code
glantau
parents:
diff changeset
266 ldr r10, [r11, #FIX_3_072711026_ID]
fefaa96def6e arm specific code
glantau
parents:
diff changeset
267 mla r5, r9, r5, r0 @ r5 = tmp1 + z2
fefaa96def6e arm specific code
glantau
parents:
diff changeset
268 ldr r9, [r11, #FIX_1_501321110_ID]
fefaa96def6e arm specific code
glantau
parents:
diff changeset
269 mla r3, r10, r3, r0 @ r3 = tmp2 + z2
fefaa96def6e arm specific code
glantau
parents:
diff changeset
270 add r7, r7, r4 @ r7 = tmp0
fefaa96def6e arm specific code
glantau
parents:
diff changeset
271 mla r1, r9, r1, r2 @ r1 = tmp3 + z1
fefaa96def6e arm specific code
glantau
parents:
diff changeset
272 add r5, r5, r6 @ r5 = tmp1
fefaa96def6e arm specific code
glantau
parents:
diff changeset
273 add r3, r3, r4 @ r3 = tmp2
fefaa96def6e arm specific code
glantau
parents:
diff changeset
274 add r1, r1, r6 @ r1 = tmp3
fefaa96def6e arm specific code
glantau
parents:
diff changeset
275
fefaa96def6e arm specific code
glantau
parents:
diff changeset
276 ldmia sp!, { r0, r2, r4, r6 } @ r0 = tmp10 / r2 = tmp13 / r4 = tmp11 / r6 = tmp12
fefaa96def6e arm specific code
glantau
parents:
diff changeset
277 @ r1 = tmp3 / r3 = tmp2 / r5 = tmp1 / r7 = tmp0
fefaa96def6e arm specific code
glantau
parents:
diff changeset
278
fefaa96def6e arm specific code
glantau
parents:
diff changeset
279 @ Compute DESCALE(tmp10 + tmp3, CONST_BITS+PASS1_BITS+3)
fefaa96def6e arm specific code
glantau
parents:
diff changeset
280 add r8, r0, r1
fefaa96def6e arm specific code
glantau
parents:
diff changeset
281 add r8, r8, #(1<<17)
fefaa96def6e arm specific code
glantau
parents:
diff changeset
282 mov r8, r8, asr #18
fefaa96def6e arm specific code
glantau
parents:
diff changeset
283 strh r8, [lr, #( 0*8)]
fefaa96def6e arm specific code
glantau
parents:
diff changeset
284
fefaa96def6e arm specific code
glantau
parents:
diff changeset
285 @ Compute DESCALE(tmp10 - tmp3, CONST_BITS+PASS1_BITS+3)
fefaa96def6e arm specific code
glantau
parents:
diff changeset
286 sub r8, r0, r1
fefaa96def6e arm specific code
glantau
parents:
diff changeset
287 add r8, r8, #(1<<17)
fefaa96def6e arm specific code
glantau
parents:
diff changeset
288 mov r8, r8, asr #18
fefaa96def6e arm specific code
glantau
parents:
diff changeset
289 strh r8, [lr, #(14*8)]
fefaa96def6e arm specific code
glantau
parents:
diff changeset
290
fefaa96def6e arm specific code
glantau
parents:
diff changeset
291 @ Compute DESCALE(tmp11 + tmp2, CONST_BITS+PASS1_BITS+3)
fefaa96def6e arm specific code
glantau
parents:
diff changeset
292 add r8, r4, r3
fefaa96def6e arm specific code
glantau
parents:
diff changeset
293 add r8, r8, #(1<<17)
fefaa96def6e arm specific code
glantau
parents:
diff changeset
294 mov r8, r8, asr #18
fefaa96def6e arm specific code
glantau
parents:
diff changeset
295 strh r8, [lr, #( 2*8)]
fefaa96def6e arm specific code
glantau
parents:
diff changeset
296
fefaa96def6e arm specific code
glantau
parents:
diff changeset
297 @ Compute DESCALE(tmp11 - tmp2, CONST_BITS+PASS1_BITS+3)
fefaa96def6e arm specific code
glantau
parents:
diff changeset
298 sub r8, r4, r3
fefaa96def6e arm specific code
glantau
parents:
diff changeset
299 add r8, r8, #(1<<17)
fefaa96def6e arm specific code
glantau
parents:
diff changeset
300 mov r8, r8, asr #18
fefaa96def6e arm specific code
glantau
parents:
diff changeset
301 strh r8, [lr, #(12*8)]
fefaa96def6e arm specific code
glantau
parents:
diff changeset
302
fefaa96def6e arm specific code
glantau
parents:
diff changeset
303 @ Compute DESCALE(tmp12 + tmp1, CONST_BITS+PASS1_BITS+3)
fefaa96def6e arm specific code
glantau
parents:
diff changeset
304 add r8, r6, r5
fefaa96def6e arm specific code
glantau
parents:
diff changeset
305 add r8, r8, #(1<<17)
fefaa96def6e arm specific code
glantau
parents:
diff changeset
306 mov r8, r8, asr #18
fefaa96def6e arm specific code
glantau
parents:
diff changeset
307 strh r8, [lr, #( 4*8)]
fefaa96def6e arm specific code
glantau
parents:
diff changeset
308
fefaa96def6e arm specific code
glantau
parents:
diff changeset
309 @ Compute DESCALE(tmp12 - tmp1, CONST_BITS+PASS1_BITS+3)
fefaa96def6e arm specific code
glantau
parents:
diff changeset
310 sub r8, r6, r5
fefaa96def6e arm specific code
glantau
parents:
diff changeset
311 add r8, r8, #(1<<17)
fefaa96def6e arm specific code
glantau
parents:
diff changeset
312 mov r8, r8, asr #18
fefaa96def6e arm specific code
glantau
parents:
diff changeset
313 strh r8, [lr, #(10*8)]
fefaa96def6e arm specific code
glantau
parents:
diff changeset
314
fefaa96def6e arm specific code
glantau
parents:
diff changeset
315 @ Compute DESCALE(tmp13 + tmp0, CONST_BITS+PASS1_BITS+3)
fefaa96def6e arm specific code
glantau
parents:
diff changeset
316 add r8, r2, r7
fefaa96def6e arm specific code
glantau
parents:
diff changeset
317 add r8, r8, #(1<<17)
fefaa96def6e arm specific code
glantau
parents:
diff changeset
318 mov r8, r8, asr #18
fefaa96def6e arm specific code
glantau
parents:
diff changeset
319 strh r8, [lr, #( 6*8)]
fefaa96def6e arm specific code
glantau
parents:
diff changeset
320
fefaa96def6e arm specific code
glantau
parents:
diff changeset
321 @ Compute DESCALE(tmp13 - tmp0, CONST_BITS+PASS1_BITS+3)
fefaa96def6e arm specific code
glantau
parents:
diff changeset
322 sub r8, r2, r7
fefaa96def6e arm specific code
glantau
parents:
diff changeset
323 add r8, r8, #(1<<17)
fefaa96def6e arm specific code
glantau
parents:
diff changeset
324 mov r8, r8, asr #18
fefaa96def6e arm specific code
glantau
parents:
diff changeset
325 strh r8, [lr, #( 8*8)]
fefaa96def6e arm specific code
glantau
parents:
diff changeset
326
fefaa96def6e arm specific code
glantau
parents:
diff changeset
327 @ End of row loop
fefaa96def6e arm specific code
glantau
parents:
diff changeset
328 add lr, lr, #2
fefaa96def6e arm specific code
glantau
parents:
diff changeset
329 subs r12, r12, #1
fefaa96def6e arm specific code
glantau
parents:
diff changeset
330 bne column_loop
fefaa96def6e arm specific code
glantau
parents:
diff changeset
331 beq the_end
fefaa96def6e arm specific code
glantau
parents:
diff changeset
332
fefaa96def6e arm specific code
glantau
parents:
diff changeset
333 empty_odd_column:
fefaa96def6e arm specific code
glantau
parents:
diff changeset
334 @ Compute DESCALE(tmp10 + tmp3, CONST_BITS+PASS1_BITS+3)
fefaa96def6e arm specific code
glantau
parents:
diff changeset
335 @ Compute DESCALE(tmp10 - tmp3, CONST_BITS+PASS1_BITS+3)
fefaa96def6e arm specific code
glantau
parents:
diff changeset
336 add r0, r0, #(1<<17)
fefaa96def6e arm specific code
glantau
parents:
diff changeset
337 mov r0, r0, asr #18
fefaa96def6e arm specific code
glantau
parents:
diff changeset
338 strh r0, [lr, #( 0*8)]
fefaa96def6e arm specific code
glantau
parents:
diff changeset
339 strh r0, [lr, #(14*8)]
fefaa96def6e arm specific code
glantau
parents:
diff changeset
340
fefaa96def6e arm specific code
glantau
parents:
diff changeset
341 @ Compute DESCALE(tmp11 + tmp2, CONST_BITS+PASS1_BITS+3)
fefaa96def6e arm specific code
glantau
parents:
diff changeset
342 @ Compute DESCALE(tmp11 - tmp2, CONST_BITS+PASS1_BITS+3)
fefaa96def6e arm specific code
glantau
parents:
diff changeset
343 add r4, r4, #(1<<17)
fefaa96def6e arm specific code
glantau
parents:
diff changeset
344 mov r4, r4, asr #18
fefaa96def6e arm specific code
glantau
parents:
diff changeset
345 strh r4, [lr, #( 2*8)]
fefaa96def6e arm specific code
glantau
parents:
diff changeset
346 strh r4, [lr, #(12*8)]
fefaa96def6e arm specific code
glantau
parents:
diff changeset
347
fefaa96def6e arm specific code
glantau
parents:
diff changeset
348 @ Compute DESCALE(tmp12 + tmp1, CONST_BITS+PASS1_BITS+3)
fefaa96def6e arm specific code
glantau
parents:
diff changeset
349 @ Compute DESCALE(tmp12 - tmp1, CONST_BITS+PASS1_BITS+3)
fefaa96def6e arm specific code
glantau
parents:
diff changeset
350 add r6, r6, #(1<<17)
fefaa96def6e arm specific code
glantau
parents:
diff changeset
351 mov r6, r6, asr #18
fefaa96def6e arm specific code
glantau
parents:
diff changeset
352 strh r6, [lr, #( 4*8)]
fefaa96def6e arm specific code
glantau
parents:
diff changeset
353 strh r6, [lr, #(10*8)]
fefaa96def6e arm specific code
glantau
parents:
diff changeset
354
fefaa96def6e arm specific code
glantau
parents:
diff changeset
355 @ Compute DESCALE(tmp13 + tmp0, CONST_BITS+PASS1_BITS+3)
fefaa96def6e arm specific code
glantau
parents:
diff changeset
356 @ Compute DESCALE(tmp13 - tmp0, CONST_BITS+PASS1_BITS+3)
fefaa96def6e arm specific code
glantau
parents:
diff changeset
357 add r2, r2, #(1<<17)
fefaa96def6e arm specific code
glantau
parents:
diff changeset
358 mov r2, r2, asr #18
fefaa96def6e arm specific code
glantau
parents:
diff changeset
359 strh r2, [lr, #( 6*8)]
fefaa96def6e arm specific code
glantau
parents:
diff changeset
360 strh r2, [lr, #( 8*8)]
fefaa96def6e arm specific code
glantau
parents:
diff changeset
361
fefaa96def6e arm specific code
glantau
parents:
diff changeset
362 @ End of row loop
fefaa96def6e arm specific code
glantau
parents:
diff changeset
363 add lr, lr, #2
fefaa96def6e arm specific code
glantau
parents:
diff changeset
364 subs r12, r12, #1
fefaa96def6e arm specific code
glantau
parents:
diff changeset
365 bne column_loop
fefaa96def6e arm specific code
glantau
parents:
diff changeset
366
fefaa96def6e arm specific code
glantau
parents:
diff changeset
367 the_end:
fefaa96def6e arm specific code
glantau
parents:
diff changeset
368 @ The end....
fefaa96def6e arm specific code
glantau
parents:
diff changeset
369 add sp, sp, #4
fefaa96def6e arm specific code
glantau
parents:
diff changeset
370 ldmia sp!, { r4 - r12, pc } @ restore callee saved regs and return
fefaa96def6e arm specific code
glantau
parents:
diff changeset
371
fefaa96def6e arm specific code
glantau
parents:
diff changeset
372 const_array:
fefaa96def6e arm specific code
glantau
parents:
diff changeset
373 .align
fefaa96def6e arm specific code
glantau
parents:
diff changeset
374 .word FIX_0_298631336
fefaa96def6e arm specific code
glantau
parents:
diff changeset
375 .word FIX_0_541196100
fefaa96def6e arm specific code
glantau
parents:
diff changeset
376 .word FIX_0_765366865
fefaa96def6e arm specific code
glantau
parents:
diff changeset
377 .word FIX_1_175875602
fefaa96def6e arm specific code
glantau
parents:
diff changeset
378 .word FIX_1_501321110
fefaa96def6e arm specific code
glantau
parents:
diff changeset
379 .word FIX_2_053119869
fefaa96def6e arm specific code
glantau
parents:
diff changeset
380 .word FIX_3_072711026
fefaa96def6e arm specific code
glantau
parents:
diff changeset
381 .word FIX_M_0_390180644
fefaa96def6e arm specific code
glantau
parents:
diff changeset
382 .word FIX_M_0_899976223
fefaa96def6e arm specific code
glantau
parents:
diff changeset
383 .word FIX_M_1_847759065
fefaa96def6e arm specific code
glantau
parents:
diff changeset
384 .word FIX_M_1_961570560
fefaa96def6e arm specific code
glantau
parents:
diff changeset
385 .word FIX_M_2_562915447
fefaa96def6e arm specific code
glantau
parents:
diff changeset
386 .word FIX_0xFFFF