annotate i386/vp3dsp_sse2.c @ 8246:75ae6859ac73 libavcodec

Trivial, Cosmetics, mostly brace placement changes
author reynaldo
date Tue, 02 Dec 2008 18:25:17 +0000
parents eebc7209c47f
children
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51c098b1f404 SSE2-optimized variant of VP3 IDCT
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1 /*
51c098b1f404 SSE2-optimized variant of VP3 IDCT
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2 * Copyright (C) 2004 the ffmpeg project
51c098b1f404 SSE2-optimized variant of VP3 IDCT
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3 *
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4 * This file is part of FFmpeg.
c8c591fe26f8 Change license headers to say 'FFmpeg' instead of 'this program/this library'
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5 *
c8c591fe26f8 Change license headers to say 'FFmpeg' instead of 'this program/this library'
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6 * FFmpeg is free software; you can redistribute it and/or
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51c098b1f404 SSE2-optimized variant of VP3 IDCT
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7 * modify it under the terms of the GNU Lesser General Public
51c098b1f404 SSE2-optimized variant of VP3 IDCT
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8 * License as published by the Free Software Foundation; either
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9 * version 2.1 of the License, or (at your option) any later version.
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51c098b1f404 SSE2-optimized variant of VP3 IDCT
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10 *
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11 * FFmpeg is distributed in the hope that it will be useful,
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51c098b1f404 SSE2-optimized variant of VP3 IDCT
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12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
51c098b1f404 SSE2-optimized variant of VP3 IDCT
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13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
51c098b1f404 SSE2-optimized variant of VP3 IDCT
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14 * Lesser General Public License for more details.
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15 *
51c098b1f404 SSE2-optimized variant of VP3 IDCT
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16 * You should have received a copy of the GNU Lesser General Public
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17 * License along with FFmpeg; if not, write to the Free Software
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18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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51c098b1f404 SSE2-optimized variant of VP3 IDCT
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19 */
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20
51c098b1f404 SSE2-optimized variant of VP3 IDCT
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21 /**
51c098b1f404 SSE2-optimized variant of VP3 IDCT
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22 * @file vp3dsp_sse2.c
51c098b1f404 SSE2-optimized variant of VP3 IDCT
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23 * SSE2-optimized functions cribbed from the original VP3 source code.
51c098b1f404 SSE2-optimized variant of VP3 IDCT
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24 */
51c098b1f404 SSE2-optimized variant of VP3 IDCT
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25
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26 #include "libavcodec/dsputil.h"
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27 #include "dsputil_mmx.h"
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51c098b1f404 SSE2-optimized variant of VP3 IDCT
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28
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29 DECLARE_ALIGNED_16(const uint16_t, ff_vp3_idct_data[7 * 8]) =
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51c098b1f404 SSE2-optimized variant of VP3 IDCT
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30 {
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31 64277,64277,64277,64277,64277,64277,64277,64277,
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32 60547,60547,60547,60547,60547,60547,60547,60547,
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33 54491,54491,54491,54491,54491,54491,54491,54491,
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34 46341,46341,46341,46341,46341,46341,46341,46341,
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35 36410,36410,36410,36410,36410,36410,36410,36410,
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36 25080,25080,25080,25080,25080,25080,25080,25080,
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51c098b1f404 SSE2-optimized variant of VP3 IDCT
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37 12785,12785,12785,12785,12785,12785,12785,12785
51c098b1f404 SSE2-optimized variant of VP3 IDCT
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38 };
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39
51c098b1f404 SSE2-optimized variant of VP3 IDCT
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40
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41 #define VP3_1D_IDCT_SSE2(ADD, SHIFT) \
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42 "movdqa "I(3)", %%xmm2 \n\t" /* xmm2 = i3 */ \
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43 "movdqa "C(3)", %%xmm6 \n\t" /* xmm6 = c3 */ \
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44 "movdqa %%xmm2, %%xmm4 \n\t" /* xmm4 = i3 */ \
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45 "movdqa "I(5)", %%xmm7 \n\t" /* xmm7 = i5 */ \
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46 "pmulhw %%xmm6, %%xmm4 \n\t" /* xmm4 = c3 * i3 - i3 */ \
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47 "movdqa "C(5)", %%xmm1 \n\t" /* xmm1 = c5 */ \
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48 "pmulhw %%xmm7, %%xmm6 \n\t" /* xmm6 = c3 * i5 - i5 */ \
4ab419106cb1 Rewrite SSE2 VP3 IDCT in inline asm
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49 "movdqa %%xmm1, %%xmm5 \n\t" /* xmm5 = c5 */ \
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50 "pmulhw %%xmm2, %%xmm1 \n\t" /* xmm1 = c5 * i3 - i3 */ \
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51 "movdqa "I(1)", %%xmm3 \n\t" /* xmm3 = i1 */ \
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52 "pmulhw %%xmm7, %%xmm5 \n\t" /* xmm5 = c5 * i5 - i5 */ \
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53 "movdqa "C(1)", %%xmm0 \n\t" /* xmm0 = c1 */ \
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54 "paddw %%xmm2, %%xmm4 \n\t" /* xmm4 = c3 * i3 */ \
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55 "paddw %%xmm7, %%xmm6 \n\t" /* xmm6 = c3 * i5 */ \
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56 "paddw %%xmm1, %%xmm2 \n\t" /* xmm2 = c5 * i3 */ \
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57 "movdqa "I(7)", %%xmm1 \n\t" /* xmm1 = i7 */ \
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58 "paddw %%xmm5, %%xmm7 \n\t" /* xmm7 = c5 * i5 */ \
4ab419106cb1 Rewrite SSE2 VP3 IDCT in inline asm
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59 "movdqa %%xmm0, %%xmm5 \n\t" /* xmm5 = c1 */ \
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60 "pmulhw %%xmm3, %%xmm0 \n\t" /* xmm0 = c1 * i1 - i1 */ \
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61 "paddsw %%xmm7, %%xmm4 \n\t" /* xmm4 = c3 * i3 + c5 * i5 = C */ \
4ab419106cb1 Rewrite SSE2 VP3 IDCT in inline asm
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62 "pmulhw %%xmm1, %%xmm5 \n\t" /* xmm5 = c1 * i7 - i7 */ \
4ab419106cb1 Rewrite SSE2 VP3 IDCT in inline asm
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63 "movdqa "C(7)", %%xmm7 \n\t" /* xmm7 = c7 */ \
4ab419106cb1 Rewrite SSE2 VP3 IDCT in inline asm
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64 "psubsw %%xmm2, %%xmm6 \n\t" /* xmm6 = c3 * i5 - c5 * i3 = D */ \
4ab419106cb1 Rewrite SSE2 VP3 IDCT in inline asm
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65 "paddw %%xmm3, %%xmm0 \n\t" /* xmm0 = c1 * i1 */ \
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66 "pmulhw %%xmm7, %%xmm3 \n\t" /* xmm3 = c7 * i1 */ \
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67 "movdqa "I(2)", %%xmm2 \n\t" /* xmm2 = i2 */ \
4ab419106cb1 Rewrite SSE2 VP3 IDCT in inline asm
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68 "pmulhw %%xmm1, %%xmm7 \n\t" /* xmm7 = c7 * i7 */ \
4ab419106cb1 Rewrite SSE2 VP3 IDCT in inline asm
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69 "paddw %%xmm1, %%xmm5 \n\t" /* xmm5 = c1 * i7 */ \
4ab419106cb1 Rewrite SSE2 VP3 IDCT in inline asm
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70 "movdqa %%xmm2, %%xmm1 \n\t" /* xmm1 = i2 */ \
4ab419106cb1 Rewrite SSE2 VP3 IDCT in inline asm
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71 "pmulhw "C(2)", %%xmm2 \n\t" /* xmm2 = i2 * c2 -i2 */ \
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72 "psubsw %%xmm5, %%xmm3 \n\t" /* xmm3 = c7 * i1 - c1 * i7 = B */ \
4ab419106cb1 Rewrite SSE2 VP3 IDCT in inline asm
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73 "movdqa "I(6)", %%xmm5 \n\t" /* xmm5 = i6 */ \
4ab419106cb1 Rewrite SSE2 VP3 IDCT in inline asm
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74 "paddsw %%xmm7, %%xmm0 \n\t" /* xmm0 = c1 * i1 + c7 * i7 = A */ \
4ab419106cb1 Rewrite SSE2 VP3 IDCT in inline asm
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75 "movdqa %%xmm5, %%xmm7 \n\t" /* xmm7 = i6 */ \
4ab419106cb1 Rewrite SSE2 VP3 IDCT in inline asm
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76 "psubsw %%xmm4, %%xmm0 \n\t" /* xmm0 = A - C */ \
4ab419106cb1 Rewrite SSE2 VP3 IDCT in inline asm
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77 "pmulhw "C(2)", %%xmm5 \n\t" /* xmm5 = c2 * i6 - i6 */ \
4ab419106cb1 Rewrite SSE2 VP3 IDCT in inline asm
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78 "paddw %%xmm1, %%xmm2 \n\t" /* xmm2 = i2 * c2 */ \
4ab419106cb1 Rewrite SSE2 VP3 IDCT in inline asm
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79 "pmulhw "C(6)", %%xmm1 \n\t" /* xmm1 = c6 * i2 */ \
4ab419106cb1 Rewrite SSE2 VP3 IDCT in inline asm
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80 "paddsw %%xmm4, %%xmm4 \n\t" /* xmm4 = C + C */ \
4ab419106cb1 Rewrite SSE2 VP3 IDCT in inline asm
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81 "paddsw %%xmm0, %%xmm4 \n\t" /* xmm4 = A + C = C. */ \
4ab419106cb1 Rewrite SSE2 VP3 IDCT in inline asm
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82 "psubsw %%xmm6, %%xmm3 \n\t" /* xmm3 = B - D */ \
4ab419106cb1 Rewrite SSE2 VP3 IDCT in inline asm
conrad
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83 "paddw %%xmm7, %%xmm5 \n\t" /* xmm5 = c2 * i6 */ \
4ab419106cb1 Rewrite SSE2 VP3 IDCT in inline asm
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84 "paddsw %%xmm6, %%xmm6 \n\t" /* xmm6 = D + D */ \
4ab419106cb1 Rewrite SSE2 VP3 IDCT in inline asm
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85 "pmulhw "C(6)", %%xmm7 \n\t" /* xmm7 = c6 * i6 */ \
4ab419106cb1 Rewrite SSE2 VP3 IDCT in inline asm
conrad
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86 "paddsw %%xmm3, %%xmm6 \n\t" /* xmm6 = B + D = D. */ \
4ab419106cb1 Rewrite SSE2 VP3 IDCT in inline asm
conrad
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87 "movdqa %%xmm4, "I(1)" \n\t" /* Save C. at I(1) */ \
4ab419106cb1 Rewrite SSE2 VP3 IDCT in inline asm
conrad
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88 "psubsw %%xmm5, %%xmm1 \n\t" /* xmm1 = c6 * i2 - c2 * i6 = H */ \
4ab419106cb1 Rewrite SSE2 VP3 IDCT in inline asm
conrad
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89 "movdqa "C(4)", %%xmm4 \n\t" /* xmm4 = c4 */ \
4ab419106cb1 Rewrite SSE2 VP3 IDCT in inline asm
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90 "movdqa %%xmm3, %%xmm5 \n\t" /* xmm5 = B - D */ \
4ab419106cb1 Rewrite SSE2 VP3 IDCT in inline asm
conrad
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91 "pmulhw %%xmm4, %%xmm3 \n\t" /* xmm3 = ( c4 -1 ) * ( B - D ) */ \
4ab419106cb1 Rewrite SSE2 VP3 IDCT in inline asm
conrad
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92 "paddsw %%xmm2, %%xmm7 \n\t" /* xmm7 = c2 * i2 + c6 * i6 = G */ \
4ab419106cb1 Rewrite SSE2 VP3 IDCT in inline asm
conrad
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93 "movdqa %%xmm6, "I(2)" \n\t" /* Save D. at I(2) */ \
4ab419106cb1 Rewrite SSE2 VP3 IDCT in inline asm
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94 "movdqa %%xmm0, %%xmm2 \n\t" /* xmm2 = A - C */ \
4ab419106cb1 Rewrite SSE2 VP3 IDCT in inline asm
conrad
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95 "movdqa "I(0)", %%xmm6 \n\t" /* xmm6 = i0 */ \
4ab419106cb1 Rewrite SSE2 VP3 IDCT in inline asm
conrad
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96 "pmulhw %%xmm4, %%xmm0 \n\t" /* xmm0 = ( c4 - 1 ) * ( A - C ) = A. */ \
4ab419106cb1 Rewrite SSE2 VP3 IDCT in inline asm
conrad
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97 "paddw %%xmm3, %%xmm5 \n\t" /* xmm5 = c4 * ( B - D ) = B. */ \
4ab419106cb1 Rewrite SSE2 VP3 IDCT in inline asm
conrad
parents: 7758
diff changeset
98 "movdqa "I(4)", %%xmm3 \n\t" /* xmm3 = i4 */ \
4ab419106cb1 Rewrite SSE2 VP3 IDCT in inline asm
conrad
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99 "psubsw %%xmm1, %%xmm5 \n\t" /* xmm5 = B. - H = B.. */ \
4ab419106cb1 Rewrite SSE2 VP3 IDCT in inline asm
conrad
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100 "paddw %%xmm0, %%xmm2 \n\t" /* xmm2 = c4 * ( A - C) = A. */ \
4ab419106cb1 Rewrite SSE2 VP3 IDCT in inline asm
conrad
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101 "psubsw %%xmm3, %%xmm6 \n\t" /* xmm6 = i0 - i4 */ \
4ab419106cb1 Rewrite SSE2 VP3 IDCT in inline asm
conrad
parents: 7758
diff changeset
102 "movdqa %%xmm6, %%xmm0 \n\t" /* xmm0 = i0 - i4 */ \
4ab419106cb1 Rewrite SSE2 VP3 IDCT in inline asm
conrad
parents: 7758
diff changeset
103 "pmulhw %%xmm4, %%xmm6 \n\t" /* xmm6 = (c4 - 1) * (i0 - i4) = F */ \
4ab419106cb1 Rewrite SSE2 VP3 IDCT in inline asm
conrad
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diff changeset
104 "paddsw %%xmm3, %%xmm3 \n\t" /* xmm3 = i4 + i4 */ \
4ab419106cb1 Rewrite SSE2 VP3 IDCT in inline asm
conrad
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diff changeset
105 "paddsw %%xmm1, %%xmm1 \n\t" /* xmm1 = H + H */ \
4ab419106cb1 Rewrite SSE2 VP3 IDCT in inline asm
conrad
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diff changeset
106 "paddsw %%xmm0, %%xmm3 \n\t" /* xmm3 = i0 + i4 */ \
4ab419106cb1 Rewrite SSE2 VP3 IDCT in inline asm
conrad
parents: 7758
diff changeset
107 "paddsw %%xmm5, %%xmm1 \n\t" /* xmm1 = B. + H = H. */ \
4ab419106cb1 Rewrite SSE2 VP3 IDCT in inline asm
conrad
parents: 7758
diff changeset
108 "pmulhw %%xmm3, %%xmm4 \n\t" /* xmm4 = ( c4 - 1 ) * ( i0 + i4 ) */ \
4ab419106cb1 Rewrite SSE2 VP3 IDCT in inline asm
conrad
parents: 7758
diff changeset
109 "paddw %%xmm0, %%xmm6 \n\t" /* xmm6 = c4 * ( i0 - i4 ) */ \
4ab419106cb1 Rewrite SSE2 VP3 IDCT in inline asm
conrad
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110 "psubsw %%xmm2, %%xmm6 \n\t" /* xmm6 = F - A. = F. */ \
4ab419106cb1 Rewrite SSE2 VP3 IDCT in inline asm
conrad
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111 "paddsw %%xmm2, %%xmm2 \n\t" /* xmm2 = A. + A. */ \
4ab419106cb1 Rewrite SSE2 VP3 IDCT in inline asm
conrad
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diff changeset
112 "movdqa "I(1)", %%xmm0 \n\t" /* Load C. from I(1) */ \
4ab419106cb1 Rewrite SSE2 VP3 IDCT in inline asm
conrad
parents: 7758
diff changeset
113 "paddsw %%xmm6, %%xmm2 \n\t" /* xmm2 = F + A. = A.. */ \
4ab419106cb1 Rewrite SSE2 VP3 IDCT in inline asm
conrad
parents: 7758
diff changeset
114 "paddw %%xmm3, %%xmm4 \n\t" /* xmm4 = c4 * ( i0 + i4 ) = 3 */ \
4ab419106cb1 Rewrite SSE2 VP3 IDCT in inline asm
conrad
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diff changeset
115 "psubsw %%xmm1, %%xmm2 \n\t" /* xmm2 = A.. - H. = R2 */ \
7882
1a684e0e6420 Factorize SSE2_(Row|Column)_IDCT into one macro
conrad
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116 ADD(%%xmm2) /* Adjust R2 and R1 before shifting */ \
7878
4ab419106cb1 Rewrite SSE2 VP3 IDCT in inline asm
conrad
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117 "paddsw %%xmm1, %%xmm1 \n\t" /* xmm1 = H. + H. */ \
4ab419106cb1 Rewrite SSE2 VP3 IDCT in inline asm
conrad
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diff changeset
118 "paddsw %%xmm2, %%xmm1 \n\t" /* xmm1 = A.. + H. = R1 */ \
7882
1a684e0e6420 Factorize SSE2_(Row|Column)_IDCT into one macro
conrad
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119 SHIFT(%%xmm2) /* xmm2 = op2 */ \
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4ab419106cb1 Rewrite SSE2 VP3 IDCT in inline asm
conrad
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120 "psubsw %%xmm7, %%xmm4 \n\t" /* xmm4 = E - G = E. */ \
7882
1a684e0e6420 Factorize SSE2_(Row|Column)_IDCT into one macro
conrad
parents: 7881
diff changeset
121 SHIFT(%%xmm1) /* xmm1 = op1 */ \
7878
4ab419106cb1 Rewrite SSE2 VP3 IDCT in inline asm
conrad
parents: 7758
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122 "movdqa "I(2)", %%xmm3 \n\t" /* Load D. from I(2) */ \
4ab419106cb1 Rewrite SSE2 VP3 IDCT in inline asm
conrad
parents: 7758
diff changeset
123 "paddsw %%xmm7, %%xmm7 \n\t" /* xmm7 = G + G */ \
4ab419106cb1 Rewrite SSE2 VP3 IDCT in inline asm
conrad
parents: 7758
diff changeset
124 "paddsw %%xmm4, %%xmm7 \n\t" /* xmm7 = E + G = G. */ \
4ab419106cb1 Rewrite SSE2 VP3 IDCT in inline asm
conrad
parents: 7758
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125 "psubsw %%xmm3, %%xmm4 \n\t" /* xmm4 = E. - D. = R4 */ \
7882
1a684e0e6420 Factorize SSE2_(Row|Column)_IDCT into one macro
conrad
parents: 7881
diff changeset
126 ADD(%%xmm4) /* Adjust R4 and R3 before shifting */ \
7878
4ab419106cb1 Rewrite SSE2 VP3 IDCT in inline asm
conrad
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127 "paddsw %%xmm3, %%xmm3 \n\t" /* xmm3 = D. + D. */ \
4ab419106cb1 Rewrite SSE2 VP3 IDCT in inline asm
conrad
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128 "paddsw %%xmm4, %%xmm3 \n\t" /* xmm3 = E. + D. = R3 */ \
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129 SHIFT(%%xmm4) /* xmm4 = op4 */ \
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130 "psubsw %%xmm5, %%xmm6 \n\t" /* xmm6 = F. - B..= R6 */ \
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131 SHIFT(%%xmm3) /* xmm3 = op3 */ \
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132 ADD(%%xmm6) /* Adjust R6 and R5 before shifting */ \
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133 "paddsw %%xmm5, %%xmm5 \n\t" /* xmm5 = B.. + B.. */ \
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134 "paddsw %%xmm6, %%xmm5 \n\t" /* xmm5 = F. + B.. = R5 */ \
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135 SHIFT(%%xmm6) /* xmm6 = op6 */ \
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136 SHIFT(%%xmm5) /* xmm5 = op5 */ \
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137 "psubsw %%xmm0, %%xmm7 \n\t" /* xmm7 = G. - C. = R7 */ \
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138 ADD(%%xmm7) /* Adjust R7 and R0 before shifting */ \
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139 "paddsw %%xmm0, %%xmm0 \n\t" /* xmm0 = C. + C. */ \
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140 "paddsw %%xmm7, %%xmm0 \n\t" /* xmm0 = G. + C. */ \
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141 SHIFT(%%xmm7) /* xmm7 = op7 */ \
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142 SHIFT(%%xmm0) /* xmm0 = op0 */
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143
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144 #define PUT_BLOCK(r0, r1, r2, r3, r4, r5, r6, r7) \
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145 "movdqa " #r0 ", " O(0) "\n\t" \
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146 "movdqa " #r1 ", " O(1) "\n\t" \
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147 "movdqa " #r2 ", " O(2) "\n\t" \
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148 "movdqa " #r3 ", " O(3) "\n\t" \
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149 "movdqa " #r4 ", " O(4) "\n\t" \
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150 "movdqa " #r5 ", " O(5) "\n\t" \
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151 "movdqa " #r6 ", " O(6) "\n\t" \
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152 "movdqa " #r7 ", " O(7) "\n\t"
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153
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154 #define NOP(xmm)
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155 #define SHIFT4(xmm) "psraw $4, "#xmm"\n\t"
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156 #define ADD8(xmm) "paddsw %2, "#xmm"\n\t"
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157
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158 void ff_vp3_idct_sse2(int16_t *input_data)
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159 {
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160 #define I(x) AV_STRINGIFY(16*x)"(%0)"
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161 #define O(x) I(x)
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162 #define C(x) AV_STRINGIFY(16*(x-1))"(%1)"
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163
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164 __asm__ volatile (
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165 VP3_1D_IDCT_SSE2(NOP, NOP)
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166
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167 TRANSPOSE8(%%xmm0, %%xmm1, %%xmm2, %%xmm3, %%xmm4, %%xmm5, %%xmm6, %%xmm7, (%0))
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168 PUT_BLOCK(%%xmm0, %%xmm5, %%xmm7, %%xmm3, %%xmm6, %%xmm4, %%xmm2, %%xmm1)
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169
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170 VP3_1D_IDCT_SSE2(ADD8, SHIFT4)
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171 PUT_BLOCK(%%xmm0, %%xmm1, %%xmm2, %%xmm3, %%xmm4, %%xmm5, %%xmm6, %%xmm7)
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172 :: "r"(input_data), "r"(ff_vp3_idct_data), "m"(ff_pw_8)
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173 );
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174 }
5014
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175
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176 void ff_vp3_idct_put_sse2(uint8_t *dest, int line_size, DCTELEM *block)
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177 {
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178 ff_vp3_idct_sse2(block);
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179 put_signed_pixels_clamped_mmx(block, dest, line_size);
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180 }
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181
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182 void ff_vp3_idct_add_sse2(uint8_t *dest, int line_size, DCTELEM *block)
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183 {
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184 ff_vp3_idct_sse2(block);
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185 add_pixels_clamped_mmx(block, dest, line_size);
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186 }