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8071
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1 /*
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2 * Copyright (c) 2008 Siarhei Siamashka <ssvb@users.sourceforge.net>
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3 *
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4 * This file is part of FFmpeg.
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5 *
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6 * FFmpeg is free software; you can redistribute it and/or
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7 * modify it under the terms of the GNU Lesser General Public
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8 * License as published by the Free Software Foundation; either
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9 * version 2.1 of the License, or (at your option) any later version.
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10 *
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11 * FFmpeg is distributed in the hope that it will be useful,
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12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 * Lesser General Public License for more details.
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15 *
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16 * You should have received a copy of the GNU Lesser General Public
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17 * License along with FFmpeg; if not, write to the Free Software
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18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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19 */
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20
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21 #include "config.h"
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22 #include "asm.S"
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23
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8252
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24 .fpu neon @ required for gas to accept UAL syntax
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8071
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25 /*
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26 * VFP is a floating point coprocessor used in some ARM cores. VFP11 has 1 cycle
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27 * throughput for almost all the instructions (except for double precision
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28 * arithmetics), but rather high latency. Latency is 4 cycles for loads and 8 cycles
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29 * for arithmetic operations. Scheduling code to avoid pipeline stalls is very
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30 * important for performance. One more interesting feature is that VFP has
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31 * independent load/store and arithmetics pipelines, so it is possible to make
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32 * them work simultaneously and get more than 1 operation per cycle. Load/store
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33 * pipeline can process 2 single precision floating point values per cycle and
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34 * supports bulk loads and stores for large sets of registers. Arithmetic operations
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35 * can be done on vectors, which allows to keep the arithmetics pipeline busy,
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36 * while the processor may issue and execute other instructions. Detailed
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37 * optimization manuals can be found at http://www.arm.com
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38 */
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39
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40 /**
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41 * ARM VFP optimized implementation of 'vector_fmul_c' function.
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42 * Assume that len is a positive number and is multiple of 8
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43 */
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44 @ void ff_vector_fmul_vfp(float *dst, const float *src, int len)
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45 function ff_vector_fmul_vfp, export=1
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46 vpush {d8-d15}
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47 mov r3, r0
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48 fmrx r12, fpscr
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49 orr r12, r12, #(3 << 16) /* set vector size to 4 */
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50 fmxr fpscr, r12
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51
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8252
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52 vldmia r3!, {s0-s3}
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53 vldmia r1!, {s8-s11}
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54 vldmia r3!, {s4-s7}
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55 vldmia r1!, {s12-s15}
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56 vmul.f32 s8, s0, s8
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8071
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57 1:
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58 subs r2, r2, #16
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8252
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59 vmul.f32 s12, s4, s12
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60 vldmiage r3!, {s16-s19}
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61 vldmiage r1!, {s24-s27}
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62 vldmiage r3!, {s20-s23}
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63 vldmiage r1!, {s28-s31}
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64 vmulge.f32 s24, s16, s24
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65 vstmia r0!, {s8-s11}
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66 vstmia r0!, {s12-s15}
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67 vmulge.f32 s28, s20, s28
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68 vldmiagt r3!, {s0-s3}
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69 vldmiagt r1!, {s8-s11}
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70 vldmiagt r3!, {s4-s7}
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71 vldmiagt r1!, {s12-s15}
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72 vmulge.f32 s8, s0, s8
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73 vstmiage r0!, {s24-s27}
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74 vstmiage r0!, {s28-s31}
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8071
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75 bgt 1b
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76
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77 bic r12, r12, #(7 << 16) /* set vector size back to 1 */
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78 fmxr fpscr, r12
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79 vpop {d8-d15}
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80 bx lr
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81 .endfunc
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82
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83 /**
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84 * ARM VFP optimized implementation of 'vector_fmul_reverse_c' function.
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85 * Assume that len is a positive number and is multiple of 8
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86 */
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87 @ void ff_vector_fmul_reverse_vfp(float *dst, const float *src0,
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88 @ const float *src1, int len)
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89 function ff_vector_fmul_reverse_vfp, export=1
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90 vpush {d8-d15}
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91 add r2, r2, r3, lsl #2
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8252
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92 vldmdb r2!, {s0-s3}
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93 vldmia r1!, {s8-s11}
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94 vldmdb r2!, {s4-s7}
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95 vldmia r1!, {s12-s15}
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96 vmul.f32 s8, s3, s8
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97 vmul.f32 s9, s2, s9
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98 vmul.f32 s10, s1, s10
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99 vmul.f32 s11, s0, s11
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100 1:
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101 subs r3, r3, #16
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8252
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102 vldmdbge r2!, {s16-s19}
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103 vmul.f32 s12, s7, s12
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104 vldmiage r1!, {s24-s27}
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105 vmul.f32 s13, s6, s13
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106 vldmdbge r2!, {s20-s23}
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107 vmul.f32 s14, s5, s14
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108 vldmiage r1!, {s28-s31}
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109 vmul.f32 s15, s4, s15
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110 vmulge.f32 s24, s19, s24
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111 vldmdbgt r2!, {s0-s3}
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112 vmulge.f32 s25, s18, s25
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113 vstmia r0!, {s8-s13}
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114 vmulge.f32 s26, s17, s26
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115 vldmiagt r1!, {s8-s11}
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116 vmulge.f32 s27, s16, s27
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117 vmulge.f32 s28, s23, s28
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118 vldmdbgt r2!, {s4-s7}
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119 vmulge.f32 s29, s22, s29
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120 vstmia r0!, {s14-s15}
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121 vmulge.f32 s30, s21, s30
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122 vmulge.f32 s31, s20, s31
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123 vmulge.f32 s8, s3, s8
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124 vldmiagt r1!, {s12-s15}
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125 vmulge.f32 s9, s2, s9
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126 vmulge.f32 s10, s1, s10
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127 vstmiage r0!, {s24-s27}
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128 vmulge.f32 s11, s0, s11
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129 vstmiage r0!, {s28-s31}
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130 bgt 1b
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131
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132 vpop {d8-d15}
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133 bx lr
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134 .endfunc
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135
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136 #ifdef HAVE_ARMV6
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137 /**
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138 * ARM VFP optimized float to int16 conversion.
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139 * Assume that len is a positive number and is multiple of 8, destination
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140 * buffer is at least 4 bytes aligned (8 bytes alignment is better for
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141 * performance), little endian byte sex
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142 */
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143 @ void ff_float_to_int16_vfp(int16_t *dst, const float *src, int len)
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144 function ff_float_to_int16_vfp, export=1
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145 push {r4-r8,lr}
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146 vpush {d8-d11}
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8252
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147 vldmia r1!, {s16-s23}
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148 vcvt.s32.f32 s0, s16
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149 vcvt.s32.f32 s1, s17
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150 vcvt.s32.f32 s2, s18
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151 vcvt.s32.f32 s3, s19
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152 vcvt.s32.f32 s4, s20
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153 vcvt.s32.f32 s5, s21
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154 vcvt.s32.f32 s6, s22
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155 vcvt.s32.f32 s7, s23
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156 1:
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157 subs r2, r2, #8
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158 vmov r3, r4, s0, s1
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159 vmov r5, r6, s2, s3
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160 vmov r7, r8, s4, s5
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161 vmov ip, lr, s6, s7
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162 vldmiagt r1!, {s16-s23}
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8071
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163 ssat r4, #16, r4
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164 ssat r3, #16, r3
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165 ssat r6, #16, r6
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166 ssat r5, #16, r5
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167 pkhbt r3, r3, r4, lsl #16
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168 pkhbt r4, r5, r6, lsl #16
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8252
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169 vcvtgt.s32.f32 s0, s16
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170 vcvtgt.s32.f32 s1, s17
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171 vcvtgt.s32.f32 s2, s18
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172 vcvtgt.s32.f32 s3, s19
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173 vcvtgt.s32.f32 s4, s20
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174 vcvtgt.s32.f32 s5, s21
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175 vcvtgt.s32.f32 s6, s22
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176 vcvtgt.s32.f32 s7, s23
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177 ssat r8, #16, r8
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178 ssat r7, #16, r7
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179 ssat lr, #16, lr
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180 ssat ip, #16, ip
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181 pkhbt r5, r7, r8, lsl #16
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182 pkhbt r6, ip, lr, lsl #16
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183 stmia r0!, {r3-r6}
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184 bgt 1b
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185
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186 vpop {d8-d11}
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187 pop {r4-r8,pc}
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188 .endfunc
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189 #endif
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