annotate alpha/motion_est_mvi_asm.S @ 6066:a82931915c54 libavcodec

Minor fix
author lu_zero
date Sun, 23 Dec 2007 19:06:33 +0000
parents 12fc192bc2bd
children 7a463923ecd1
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
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1 /*
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2 * Alpha optimized DSP utils
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3 * Copyright (c) 2002 Falk Hueffner <falk@debian.org>
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4 *
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5 * This file is part of FFmpeg.
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6 *
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7 * FFmpeg is free software; you can redistribute it and/or
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8 * modify it under the terms of the GNU Lesser General Public
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9 * License as published by the Free Software Foundation; either
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10 * version 2.1 of the License, or (at your option) any later version.
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11 *
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12 * FFmpeg is distributed in the hope that it will be useful,
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13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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15 * Lesser General Public License for more details.
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16 *
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17 * You should have received a copy of the GNU Lesser General Public
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18 * License along with FFmpeg; if not, write to the Free Software
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19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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20 */
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21
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22 #include "regdef.h"
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23
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24 /* Some nicer register names. */
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25 #define ta t10
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26 #define tb t11
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27 #define tc t12
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28 #define td AT
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29 /* Danger: these overlap with the argument list and the return value */
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30 #define te a5
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31 #define tf a4
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32 #define tg a3
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33 #define th v0
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34
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35 .set noat
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36 .set noreorder
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37 .arch pca56
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38 .text
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39
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40 /*****************************************************************************
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41 * int pix_abs16x16_mvi_asm(uint8_t *pix1, uint8_t *pix2, int line_size)
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42 *
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43 * This code is written with a pca56 in mind. For ev6, one should
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44 * really take the increased latency of 3 cycles for MVI instructions
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45 * into account.
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46 *
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47 * It is important to keep the loading and first use of a register as
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48 * far apart as possible, because if a register is accessed before it
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49 * has been fetched from memory, the CPU will stall.
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50 */
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51 .align 4
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52 .globl pix_abs16x16_mvi_asm
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53 .ent pix_abs16x16_mvi_asm
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54 pix_abs16x16_mvi_asm:
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55 .frame sp, 0, ra, 0
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56 .prologue 0
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57
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58 #ifdef CONFIG_GPROF
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59 lda AT, _mcount
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60 jsr AT, (AT), _mcount
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61 #endif
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62
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63 and a1, 7, t0
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64 clr v0
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65 lda a3, 16
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66 beq t0, $aligned
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67 .align 4
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68 $unaligned:
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69 /* Registers:
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70 line 0:
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71 t0: left_u -> left lo -> left
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72 t1: mid
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73 t2: right_u -> right hi -> right
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74 t3: ref left
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75 t4: ref right
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76 line 1:
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77 t5: left_u -> left lo -> left
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78 t6: mid
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79 t7: right_u -> right hi -> right
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80 t8: ref left
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81 t9: ref right
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82 temp:
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83 ta: left hi
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84 tb: right lo
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85 tc: error left
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86 td: error right */
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87
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88 /* load line 0 */
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89 ldq_u t0, 0(a1) # left_u
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90 ldq_u t1, 8(a1) # mid
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91 ldq_u t2, 16(a1) # right_u
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92 ldq t3, 0(a0) # ref left
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93 ldq t4, 8(a0) # ref right
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94 addq a0, a2, a0 # pix1
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95 addq a1, a2, a1 # pix2
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96 /* load line 1 */
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97 ldq_u t5, 0(a1) # left_u
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98 ldq_u t6, 8(a1) # mid
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99 ldq_u t7, 16(a1) # right_u
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100 ldq t8, 0(a0) # ref left
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101 ldq t9, 8(a0) # ref right
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102 addq a0, a2, a0 # pix1
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103 addq a1, a2, a1 # pix2
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104 /* calc line 0 */
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105 extql t0, a1, t0 # left lo
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106 extqh t1, a1, ta # left hi
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107 extql t1, a1, tb # right lo
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108 or t0, ta, t0 # left
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109 extqh t2, a1, t2 # right hi
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110 perr t3, t0, tc # error left
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111 or t2, tb, t2 # right
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112 perr t4, t2, td # error right
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113 addq v0, tc, v0 # add error left
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114 addq v0, td, v0 # add error left
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115 /* calc line 1 */
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116 extql t5, a1, t5 # left lo
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117 extqh t6, a1, ta # left hi
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118 extql t6, a1, tb # right lo
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119 or t5, ta, t5 # left
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120 extqh t7, a1, t7 # right hi
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121 perr t8, t5, tc # error left
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122 or t7, tb, t7 # right
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123 perr t9, t7, td # error right
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124 addq v0, tc, v0 # add error left
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125 addq v0, td, v0 # add error left
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126 /* loop */
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127 subq a3, 2, a3 # h -= 2
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128 bne a3, $unaligned
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129 ret
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130
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131 .align 4
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132 $aligned:
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133 /* load line 0 */
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134 ldq t0, 0(a1) # left
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135 ldq t1, 8(a1) # right
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136 addq a1, a2, a1 # pix2
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137 ldq t2, 0(a0) # ref left
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138 ldq t3, 8(a0) # ref right
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139 addq a0, a2, a0 # pix1
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140 /* load line 1 */
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141 ldq t4, 0(a1) # left
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142 ldq t5, 8(a1) # right
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143 addq a1, a2, a1 # pix2
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144 ldq t6, 0(a0) # ref left
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145 ldq t7, 8(a0) # ref right
107a56aa74f5 Add Alpha assembly for pix_abs16x16. Optimized for pca56, no large win
mellum
parents:
diff changeset
146 addq a0, a2, a0 # pix1
107a56aa74f5 Add Alpha assembly for pix_abs16x16. Optimized for pca56, no large win
mellum
parents:
diff changeset
147 /* load line 2 */
107a56aa74f5 Add Alpha assembly for pix_abs16x16. Optimized for pca56, no large win
mellum
parents:
diff changeset
148 ldq t8, 0(a1) # left
107a56aa74f5 Add Alpha assembly for pix_abs16x16. Optimized for pca56, no large win
mellum
parents:
diff changeset
149 ldq t9, 8(a1) # right
107a56aa74f5 Add Alpha assembly for pix_abs16x16. Optimized for pca56, no large win
mellum
parents:
diff changeset
150 addq a1, a2, a1 # pix2
107a56aa74f5 Add Alpha assembly for pix_abs16x16. Optimized for pca56, no large win
mellum
parents:
diff changeset
151 ldq ta, 0(a0) # ref left
107a56aa74f5 Add Alpha assembly for pix_abs16x16. Optimized for pca56, no large win
mellum
parents:
diff changeset
152 ldq tb, 8(a0) # ref right
107a56aa74f5 Add Alpha assembly for pix_abs16x16. Optimized for pca56, no large win
mellum
parents:
diff changeset
153 addq a0, a2, a0 # pix1
107a56aa74f5 Add Alpha assembly for pix_abs16x16. Optimized for pca56, no large win
mellum
parents:
diff changeset
154 /* load line 3 */
107a56aa74f5 Add Alpha assembly for pix_abs16x16. Optimized for pca56, no large win
mellum
parents:
diff changeset
155 ldq tc, 0(a1) # left
107a56aa74f5 Add Alpha assembly for pix_abs16x16. Optimized for pca56, no large win
mellum
parents:
diff changeset
156 ldq td, 8(a1) # right
107a56aa74f5 Add Alpha assembly for pix_abs16x16. Optimized for pca56, no large win
mellum
parents:
diff changeset
157 addq a1, a2, a1 # pix2
107a56aa74f5 Add Alpha assembly for pix_abs16x16. Optimized for pca56, no large win
mellum
parents:
diff changeset
158 ldq te, 0(a0) # ref left
107a56aa74f5 Add Alpha assembly for pix_abs16x16. Optimized for pca56, no large win
mellum
parents:
diff changeset
159 ldq tf, 8(a0) # ref right
107a56aa74f5 Add Alpha assembly for pix_abs16x16. Optimized for pca56, no large win
mellum
parents:
diff changeset
160 /* calc line 0 */
107a56aa74f5 Add Alpha assembly for pix_abs16x16. Optimized for pca56, no large win
mellum
parents:
diff changeset
161 perr t0, t2, t0 # error left
107a56aa74f5 Add Alpha assembly for pix_abs16x16. Optimized for pca56, no large win
mellum
parents:
diff changeset
162 addq a0, a2, a0 # pix1
107a56aa74f5 Add Alpha assembly for pix_abs16x16. Optimized for pca56, no large win
mellum
parents:
diff changeset
163 perr t1, t3, t1 # error right
107a56aa74f5 Add Alpha assembly for pix_abs16x16. Optimized for pca56, no large win
mellum
parents:
diff changeset
164 addq v0, t0, v0 # add error left
107a56aa74f5 Add Alpha assembly for pix_abs16x16. Optimized for pca56, no large win
mellum
parents:
diff changeset
165 /* calc line 1 */
107a56aa74f5 Add Alpha assembly for pix_abs16x16. Optimized for pca56, no large win
mellum
parents:
diff changeset
166 perr t4, t6, t0 # error left
107a56aa74f5 Add Alpha assembly for pix_abs16x16. Optimized for pca56, no large win
mellum
parents:
diff changeset
167 addq v0, t1, v0 # add error right
107a56aa74f5 Add Alpha assembly for pix_abs16x16. Optimized for pca56, no large win
mellum
parents:
diff changeset
168 perr t5, t7, t1 # error right
107a56aa74f5 Add Alpha assembly for pix_abs16x16. Optimized for pca56, no large win
mellum
parents:
diff changeset
169 addq v0, t0, v0 # add error left
107a56aa74f5 Add Alpha assembly for pix_abs16x16. Optimized for pca56, no large win
mellum
parents:
diff changeset
170 /* calc line 2 */
107a56aa74f5 Add Alpha assembly for pix_abs16x16. Optimized for pca56, no large win
mellum
parents:
diff changeset
171 perr t8, ta, t0 # error left
107a56aa74f5 Add Alpha assembly for pix_abs16x16. Optimized for pca56, no large win
mellum
parents:
diff changeset
172 addq v0, t1, v0 # add error right
107a56aa74f5 Add Alpha assembly for pix_abs16x16. Optimized for pca56, no large win
mellum
parents:
diff changeset
173 perr t9, tb, t1 # error right
107a56aa74f5 Add Alpha assembly for pix_abs16x16. Optimized for pca56, no large win
mellum
parents:
diff changeset
174 addq v0, t0, v0 # add error left
107a56aa74f5 Add Alpha assembly for pix_abs16x16. Optimized for pca56, no large win
mellum
parents:
diff changeset
175 /* calc line 3 */
107a56aa74f5 Add Alpha assembly for pix_abs16x16. Optimized for pca56, no large win
mellum
parents:
diff changeset
176 perr tc, te, t0 # error left
107a56aa74f5 Add Alpha assembly for pix_abs16x16. Optimized for pca56, no large win
mellum
parents:
diff changeset
177 addq v0, t1, v0 # add error right
107a56aa74f5 Add Alpha assembly for pix_abs16x16. Optimized for pca56, no large win
mellum
parents:
diff changeset
178 perr td, tf, t1 # error right
107a56aa74f5 Add Alpha assembly for pix_abs16x16. Optimized for pca56, no large win
mellum
parents:
diff changeset
179 addq v0, t0, v0 # add error left
107a56aa74f5 Add Alpha assembly for pix_abs16x16. Optimized for pca56, no large win
mellum
parents:
diff changeset
180 addq v0, t1, v0 # add error right
107a56aa74f5 Add Alpha assembly for pix_abs16x16. Optimized for pca56, no large win
mellum
parents:
diff changeset
181 /* loop */
107a56aa74f5 Add Alpha assembly for pix_abs16x16. Optimized for pca56, no large win
mellum
parents:
diff changeset
182 subq a3, 4, a3 # h -= 4
107a56aa74f5 Add Alpha assembly for pix_abs16x16. Optimized for pca56, no large win
mellum
parents:
diff changeset
183 bne a3, $aligned
107a56aa74f5 Add Alpha assembly for pix_abs16x16. Optimized for pca56, no large win
mellum
parents:
diff changeset
184 ret
107a56aa74f5 Add Alpha assembly for pix_abs16x16. Optimized for pca56, no large win
mellum
parents:
diff changeset
185 .end pix_abs16x16_mvi_asm