annotate sparc/vis.h @ 4851:ba6fd4b884b6 libavcodec

correct another possible buffer overflow where interlaced would get stuck to 1 but then width/height would change and interlaced wouldnt be reset ...
author michael
date Sat, 14 Apr 2007 22:05:12 +0000
parents 2c54309fef91
children 9ecbfc0c82bf
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1 /*
55b7435c59b8 VIS optimized motion compensation code. by (David S. Miller <davem at redhat dot com>)
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2 * vis.h
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3 * Copyright (C) 2003 David S. Miller <davem@redhat.com>
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4 *
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5 * This file is part of FFmpeg.
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6 *
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7 * FFmpeg is free software; you can redistribute it and/or
2c54309fef91 Switch to the LGPL as agreed to by the author according to the
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8 * modify it under the terms of the GNU Lesser General Public
2c54309fef91 Switch to the LGPL as agreed to by the author according to the
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9 * License as published by the Free Software Foundation; either
2c54309fef91 Switch to the LGPL as agreed to by the author according to the
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10 * version 2.1 of the License, or (at your option) any later version.
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11 *
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12 * FFmpeg is distributed in the hope that it will be useful,
1959
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13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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15 * Lesser General Public License for more details.
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16 *
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17 * You should have received a copy of the GNU Lesser General Public
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18 * License along with FFmpeg; if not, write to the Free Software
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19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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20 */
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21
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22 /* You may be asking why I hard-code the instruction opcodes and don't
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23 * use the normal VIS assembler mnenomics for the VIS instructions.
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24 *
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25 * The reason is that Sun, in their infinite wisdom, decided that a binary
55b7435c59b8 VIS optimized motion compensation code. by (David S. Miller <davem at redhat dot com>)
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26 * using a VIS instruction will cause it to be marked (in the ELF headers)
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27 * as doing so, and this prevents the OS from loading such binaries if the
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28 * current cpu doesn't have VIS. There is no way to easily override this
55b7435c59b8 VIS optimized motion compensation code. by (David S. Miller <davem at redhat dot com>)
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29 * behavior of the assembler that I am aware of.
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30 *
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31 * This totally defeats what libmpeg2 is trying to do which is allow a
55b7435c59b8 VIS optimized motion compensation code. by (David S. Miller <davem at redhat dot com>)
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32 * single binary to be created, and then detect the availability of VIS
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33 * at runtime.
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34 *
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35 * I'm not saying that tainting the binary by default is bad, rather I'm
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36 * saying that not providing a way to override this easily unnecessarily
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37 * ties people's hands.
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38 *
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39 * Thus, we do the opcode encoding by hand and output 32-bit words in
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40 * the assembler to keep the binary from becoming tainted.
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41 */
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42
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43 #define vis_opc_base ((0x1 << 31) | (0x36 << 19))
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44 #define vis_opf(X) ((X) << 5)
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45 #define vis_sreg(X) (X)
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46 #define vis_dreg(X) (((X)&0x1f)|((X)>>5))
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47 #define vis_rs1_s(X) (vis_sreg(X) << 14)
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48 #define vis_rs1_d(X) (vis_dreg(X) << 14)
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49 #define vis_rs2_s(X) (vis_sreg(X) << 0)
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50 #define vis_rs2_d(X) (vis_dreg(X) << 0)
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51 #define vis_rd_s(X) (vis_sreg(X) << 25)
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52 #define vis_rd_d(X) (vis_dreg(X) << 25)
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53
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54 #define vis_ss2s(opf,rs1,rs2,rd) \
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55 __asm__ __volatile__ (".word %0" \
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56 : : "i" (vis_opc_base | vis_opf(opf) | \
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57 vis_rs1_s(rs1) | \
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58 vis_rs2_s(rs2) | \
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59 vis_rd_s(rd)))
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60
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61 #define vis_dd2d(opf,rs1,rs2,rd) \
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62 __asm__ __volatile__ (".word %0" \
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63 : : "i" (vis_opc_base | vis_opf(opf) | \
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64 vis_rs1_d(rs1) | \
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65 vis_rs2_d(rs2) | \
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66 vis_rd_d(rd)))
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67
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68 #define vis_ss2d(opf,rs1,rs2,rd) \
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69 __asm__ __volatile__ (".word %0" \
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70 : : "i" (vis_opc_base | vis_opf(opf) | \
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71 vis_rs1_s(rs1) | \
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72 vis_rs2_s(rs2) | \
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73 vis_rd_d(rd)))
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74
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75 #define vis_sd2d(opf,rs1,rs2,rd) \
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76 __asm__ __volatile__ (".word %0" \
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77 : : "i" (vis_opc_base | vis_opf(opf) | \
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78 vis_rs1_s(rs1) | \
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79 vis_rs2_d(rs2) | \
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80 vis_rd_d(rd)))
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81
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82 #define vis_d2s(opf,rs2,rd) \
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83 __asm__ __volatile__ (".word %0" \
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84 : : "i" (vis_opc_base | vis_opf(opf) | \
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85 vis_rs2_d(rs2) | \
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86 vis_rd_s(rd)))
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87
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88 #define vis_s2d(opf,rs2,rd) \
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89 __asm__ __volatile__ (".word %0" \
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90 : : "i" (vis_opc_base | vis_opf(opf) | \
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91 vis_rs2_s(rs2) | \
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92 vis_rd_d(rd)))
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93
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94 #define vis_d12d(opf,rs1,rd) \
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95 __asm__ __volatile__ (".word %0" \
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96 : : "i" (vis_opc_base | vis_opf(opf) | \
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97 vis_rs1_d(rs1) | \
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98 vis_rd_d(rd)))
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99
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100 #define vis_d22d(opf,rs2,rd) \
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101 __asm__ __volatile__ (".word %0" \
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102 : : "i" (vis_opc_base | vis_opf(opf) | \
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103 vis_rs2_d(rs2) | \
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104 vis_rd_d(rd)))
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105
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106 #define vis_s12s(opf,rs1,rd) \
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107 __asm__ __volatile__ (".word %0" \
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108 : : "i" (vis_opc_base | vis_opf(opf) | \
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109 vis_rs1_s(rs1) | \
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110 vis_rd_s(rd)))
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111
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112 #define vis_s22s(opf,rs2,rd) \
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113 __asm__ __volatile__ (".word %0" \
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114 : : "i" (vis_opc_base | vis_opf(opf) | \
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115 vis_rs2_s(rs2) | \
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116 vis_rd_s(rd)))
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117
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118 #define vis_s(opf,rd) \
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119 __asm__ __volatile__ (".word %0" \
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120 : : "i" (vis_opc_base | vis_opf(opf) | \
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121 vis_rd_s(rd)))
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122
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123 #define vis_d(opf,rd) \
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124 __asm__ __volatile__ (".word %0" \
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125 : : "i" (vis_opc_base | vis_opf(opf) | \
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126 vis_rd_d(rd)))
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127
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128 #define vis_r2m(op,rd,mem) \
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129 __asm__ __volatile__ (#op "\t%%f" #rd ", [%0]" : : "r" (&(mem)) )
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130
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131 #define vis_r2m_2(op,rd,mem1,mem2) \
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132 __asm__ __volatile__ (#op "\t%%f" #rd ", [%0 + %1]" : : "r" (mem1), "r" (mem2) )
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133
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134 #define vis_m2r(op,mem,rd) \
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135 __asm__ __volatile__ (#op "\t[%0], %%f" #rd : : "r" (&(mem)) )
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136
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137 #define vis_m2r_2(op,mem1,mem2,rd) \
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138 __asm__ __volatile__ (#op "\t[%0 + %1], %%f" #rd : : "r" (mem1), "r" (mem2) )
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139
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140 static inline void vis_set_gsr(unsigned int _val)
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141 {
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142 register unsigned int val asm("g1");
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143
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144 val = _val;
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145 __asm__ __volatile__(".word 0xa7804000"
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146 : : "r" (val));
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147 }
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148
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149 #define VIS_GSR_ALIGNADDR_MASK 0x0000007
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150 #define VIS_GSR_ALIGNADDR_SHIFT 0
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151 #define VIS_GSR_SCALEFACT_MASK 0x0000078
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152 #define VIS_GSR_SCALEFACT_SHIFT 3
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153
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154 #define vis_ld32(mem,rs1) vis_m2r(ld, mem, rs1)
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155 #define vis_ld32_2(mem1,mem2,rs1) vis_m2r_2(ld, mem1, mem2, rs1)
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156 #define vis_st32(rs1,mem) vis_r2m(st, rs1, mem)
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157 #define vis_st32_2(rs1,mem1,mem2) vis_r2m_2(st, rs1, mem1, mem2)
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158 #define vis_ld64(mem,rs1) vis_m2r(ldd, mem, rs1)
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159 #define vis_ld64_2(mem1,mem2,rs1) vis_m2r_2(ldd, mem1, mem2, rs1)
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160 #define vis_st64(rs1,mem) vis_r2m(std, rs1, mem)
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161 #define vis_st64_2(rs1,mem1,mem2) vis_r2m_2(std, rs1, mem1, mem2)
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162
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163 #define vis_ldblk(mem, rd) \
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164 do { register void *__mem asm("g1"); \
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165 __mem = &(mem); \
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166 __asm__ __volatile__(".word 0xc1985e00 | %1" \
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167 : \
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168 : "r" (__mem), \
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169 "i" (vis_rd_d(rd)) \
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170 : "memory"); \
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171 } while (0)
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172
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173 #define vis_stblk(rd, mem) \
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174 do { register void *__mem asm("g1"); \
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175 __mem = &(mem); \
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176 __asm__ __volatile__(".word 0xc1b85e00 | %1" \
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177 : \
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178 : "r" (__mem), \
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179 "i" (vis_rd_d(rd)) \
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180 : "memory"); \
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181 } while (0)
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182
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183 #define vis_membar_storestore() \
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184 __asm__ __volatile__(".word 0x8143e008" : : : "memory")
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185
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186 #define vis_membar_sync() \
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187 __asm__ __volatile__(".word 0x8143e040" : : : "memory")
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188
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189 /* 16 and 32 bit partitioned addition and subtraction. The normal
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190 * versions perform 4 16-bit or 2 32-bit additions or subtractions.
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191 * The 's' versions perform 2 16-bit or 1 32-bit additions or
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192 * subtractions.
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193 */
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194
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195 #define vis_padd16(rs1,rs2,rd) vis_dd2d(0x50, rs1, rs2, rd)
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196 #define vis_padd16s(rs1,rs2,rd) vis_ss2s(0x51, rs1, rs2, rd)
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197 #define vis_padd32(rs1,rs2,rd) vis_dd2d(0x52, rs1, rs2, rd)
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198 #define vis_padd32s(rs1,rs2,rd) vis_ss2s(0x53, rs1, rs2, rd)
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199 #define vis_psub16(rs1,rs2,rd) vis_dd2d(0x54, rs1, rs2, rd)
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200 #define vis_psub16s(rs1,rs2,rd) vis_ss2s(0x55, rs1, rs2, rd)
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201 #define vis_psub32(rs1,rs2,rd) vis_dd2d(0x56, rs1, rs2, rd)
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202 #define vis_psub32s(rs1,rs2,rd) vis_ss2s(0x57, rs1, rs2, rd)
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203
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204 /* Pixel formatting instructions. */
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205
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206 #define vis_pack16(rs2,rd) vis_d2s( 0x3b, rs2, rd)
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207 #define vis_pack32(rs1,rs2,rd) vis_dd2d(0x3a, rs1, rs2, rd)
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208 #define vis_packfix(rs2,rd) vis_d2s( 0x3d, rs2, rd)
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209 #define vis_expand(rs2,rd) vis_s2d( 0x4d, rs2, rd)
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210 #define vis_pmerge(rs1,rs2,rd) vis_ss2d(0x4b, rs1, rs2, rd)
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211
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212 /* Partitioned multiply instructions. */
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213
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214 #define vis_mul8x16(rs1,rs2,rd) vis_sd2d(0x31, rs1, rs2, rd)
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215 #define vis_mul8x16au(rs1,rs2,rd) vis_ss2d(0x33, rs1, rs2, rd)
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216 #define vis_mul8x16al(rs1,rs2,rd) vis_ss2d(0x35, rs1, rs2, rd)
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217 #define vis_mul8sux16(rs1,rs2,rd) vis_dd2d(0x36, rs1, rs2, rd)
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218 #define vis_mul8ulx16(rs1,rs2,rd) vis_dd2d(0x37, rs1, rs2, rd)
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219 #define vis_muld8sux16(rs1,rs2,rd) vis_ss2d(0x38, rs1, rs2, rd)
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220 #define vis_muld8ulx16(rs1,rs2,rd) vis_ss2d(0x39, rs1, rs2, rd)
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221
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222 /* Alignment instructions. */
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223
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224 static inline void *vis_alignaddr(void *_ptr)
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225 {
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226 register void *ptr asm("g1");
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227
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228 ptr = _ptr;
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229
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230 __asm__ __volatile__(".word %2"
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231 : "=&r" (ptr)
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232 : "0" (ptr),
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233 "i" (vis_opc_base | vis_opf(0x18) |
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234 vis_rs1_s(1) |
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235 vis_rs2_s(0) |
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236 vis_rd_s(1)));
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237
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238 return ptr;
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239 }
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240
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241 static inline void vis_alignaddr_g0(void *_ptr)
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242 {
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243 register void *ptr asm("g1");
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244
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245 ptr = _ptr;
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246
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247 __asm__ __volatile__(".word %2"
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248 : "=&r" (ptr)
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249 : "0" (ptr),
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250 "i" (vis_opc_base | vis_opf(0x18) |
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251 vis_rs1_s(1) |
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252 vis_rs2_s(0) |
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253 vis_rd_s(0)));
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254 }
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255
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256 static inline void *vis_alignaddrl(void *_ptr)
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257 {
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258 register void *ptr asm("g1");
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259
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260 ptr = _ptr;
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261
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262 __asm__ __volatile__(".word %2"
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263 : "=&r" (ptr)
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264 : "0" (ptr),
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265 "i" (vis_opc_base | vis_opf(0x19) |
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266 vis_rs1_s(1) |
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267 vis_rs2_s(0) |
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268 vis_rd_s(1)));
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269
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270 return ptr;
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271 }
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272
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273 static inline void vis_alignaddrl_g0(void *_ptr)
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274 {
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275 register void *ptr asm("g1");
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276
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277 ptr = _ptr;
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278
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279 __asm__ __volatile__(".word %2"
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280 : "=&r" (ptr)
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281 : "0" (ptr),
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282 "i" (vis_opc_base | vis_opf(0x19) |
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283 vis_rs1_s(1) |
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284 vis_rs2_s(0) |
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285 vis_rd_s(0)));
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286 }
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287
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288 #define vis_faligndata(rs1,rs2,rd) vis_dd2d(0x48, rs1, rs2, rd)
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289
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290 /* Logical operate instructions. */
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291
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292 #define vis_fzero(rd) vis_d( 0x60, rd)
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293 #define vis_fzeros(rd) vis_s( 0x61, rd)
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294 #define vis_fone(rd) vis_d( 0x7e, rd)
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295 #define vis_fones(rd) vis_s( 0x7f, rd)
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296 #define vis_src1(rs1,rd) vis_d12d(0x74, rs1, rd)
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297 #define vis_src1s(rs1,rd) vis_s12s(0x75, rs1, rd)
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298 #define vis_src2(rs2,rd) vis_d22d(0x78, rs2, rd)
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299 #define vis_src2s(rs2,rd) vis_s22s(0x79, rs2, rd)
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300 #define vis_not1(rs1,rd) vis_d12d(0x6a, rs1, rd)
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301 #define vis_not1s(rs1,rd) vis_s12s(0x6b, rs1, rd)
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302 #define vis_not2(rs2,rd) vis_d22d(0x66, rs2, rd)
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303 #define vis_not2s(rs2,rd) vis_s22s(0x67, rs2, rd)
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304 #define vis_or(rs1,rs2,rd) vis_dd2d(0x7c, rs1, rs2, rd)
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305 #define vis_ors(rs1,rs2,rd) vis_ss2s(0x7d, rs1, rs2, rd)
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306 #define vis_nor(rs1,rs2,rd) vis_dd2d(0x62, rs1, rs2, rd)
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307 #define vis_nors(rs1,rs2,rd) vis_ss2s(0x63, rs1, rs2, rd)
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308 #define vis_and(rs1,rs2,rd) vis_dd2d(0x70, rs1, rs2, rd)
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309 #define vis_ands(rs1,rs2,rd) vis_ss2s(0x71, rs1, rs2, rd)
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310 #define vis_nand(rs1,rs2,rd) vis_dd2d(0x6e, rs1, rs2, rd)
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311 #define vis_nands(rs1,rs2,rd) vis_ss2s(0x6f, rs1, rs2, rd)
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312 #define vis_xor(rs1,rs2,rd) vis_dd2d(0x6c, rs1, rs2, rd)
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313 #define vis_xors(rs1,rs2,rd) vis_ss2s(0x6d, rs1, rs2, rd)
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314 #define vis_xnor(rs1,rs2,rd) vis_dd2d(0x72, rs1, rs2, rd)
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315 #define vis_xnors(rs1,rs2,rd) vis_ss2s(0x73, rs1, rs2, rd)
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316 #define vis_ornot1(rs1,rs2,rd) vis_dd2d(0x7a, rs1, rs2, rd)
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317 #define vis_ornot1s(rs1,rs2,rd) vis_ss2s(0x7b, rs1, rs2, rd)
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318 #define vis_ornot2(rs1,rs2,rd) vis_dd2d(0x76, rs1, rs2, rd)
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319 #define vis_ornot2s(rs1,rs2,rd) vis_ss2s(0x77, rs1, rs2, rd)
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320 #define vis_andnot1(rs1,rs2,rd) vis_dd2d(0x68, rs1, rs2, rd)
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321 #define vis_andnot1s(rs1,rs2,rd) vis_ss2s(0x69, rs1, rs2, rd)
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322 #define vis_andnot2(rs1,rs2,rd) vis_dd2d(0x64, rs1, rs2, rd)
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323 #define vis_andnot2s(rs1,rs2,rd) vis_ss2s(0x65, rs1, rs2, rd)
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324
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325 /* Pixel component distance. */
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326
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327 #define vis_pdist(rs1,rs2,rd) vis_dd2d(0x3e, rs1, rs2, rd)