Mercurial > libavcodec.hg
annotate alpha/motion_est_mvi_asm.S @ 11887:c432b63b345e libavcodec
psdec: Factorize iid/icc/ipd/opd parameter bitstream reading.
author | alexc |
---|---|
date | Sat, 19 Jun 2010 23:53:21 +0000 |
parents | 6f1b210e58d1 |
children | 58c2da0a371b |
rev | line source |
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1 /* |
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2 * Alpha optimized DSP utils |
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3 * Copyright (c) 2002 Falk Hueffner <falk@debian.org> |
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4 * |
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5 * This file is part of FFmpeg. |
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6 * |
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7 * FFmpeg is free software; you can redistribute it and/or |
3130 | 8 * modify it under the terms of the GNU Lesser General Public |
9 * License as published by the Free Software Foundation; either | |
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10 * version 2.1 of the License, or (at your option) any later version. |
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11 * |
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12 * FFmpeg is distributed in the hope that it will be useful, |
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13 * but WITHOUT ANY WARRANTY; without even the implied warranty of |
3130 | 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
15 * Lesser General Public License for more details. | |
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16 * |
3130 | 17 * You should have received a copy of the GNU Lesser General Public |
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18 * License along with FFmpeg; if not, write to the Free Software |
3130 | 19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA |
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20 */ |
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21 |
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22 #include "regdef.h" |
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23 |
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24 /* Some nicer register names. */ |
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25 #define ta t10 |
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26 #define tb t11 |
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27 #define tc t12 |
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28 #define td AT |
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29 /* Danger: these overlap with the argument list and the return value */ |
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30 #define te a5 |
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31 #define tf a4 |
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32 #define tg a3 |
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33 #define th v0 |
2967 | 34 |
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35 .set noat |
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36 .set noreorder |
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37 .arch pca56 |
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38 .text |
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39 |
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40 /***************************************************************************** |
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41 * int pix_abs16x16_mvi_asm(uint8_t *pix1, uint8_t *pix2, int line_size) |
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42 * |
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43 * This code is written with a pca56 in mind. For ev6, one should |
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44 * really take the increased latency of 3 cycles for MVI instructions |
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45 * into account. |
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46 * |
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47 * It is important to keep the loading and first use of a register as |
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48 * far apart as possible, because if a register is accessed before it |
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49 * has been fetched from memory, the CPU will stall. |
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50 */ |
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51 .align 4 |
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52 .globl pix_abs16x16_mvi_asm |
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53 .ent pix_abs16x16_mvi_asm |
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54 pix_abs16x16_mvi_asm: |
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55 .frame sp, 0, ra, 0 |
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56 .prologue 0 |
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57 |
8590 | 58 #if CONFIG_GPROF |
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59 lda AT, _mcount |
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60 jsr AT, (AT), _mcount |
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61 #endif |
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62 |
8625 | 63 and a2, 7, t0 |
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64 clr v0 |
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65 beq t0, $aligned |
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66 .align 4 |
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67 $unaligned: |
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68 /* Registers: |
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69 line 0: |
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70 t0: left_u -> left lo -> left |
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71 t1: mid |
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72 t2: right_u -> right hi -> right |
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73 t3: ref left |
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74 t4: ref right |
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75 line 1: |
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76 t5: left_u -> left lo -> left |
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77 t6: mid |
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78 t7: right_u -> right hi -> right |
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79 t8: ref left |
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80 t9: ref right |
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81 temp: |
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82 ta: left hi |
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83 tb: right lo |
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84 tc: error left |
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85 td: error right */ |
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86 |
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87 /* load line 0 */ |
8625 | 88 ldq_u t0, 0(a2) # left_u |
89 ldq_u t1, 8(a2) # mid | |
90 ldq_u t2, 16(a2) # right_u | |
91 ldq t3, 0(a1) # ref left | |
92 ldq t4, 8(a1) # ref right | |
93 addq a1, a3, a1 # pix1 | |
94 addq a2, a3, a2 # pix2 | |
2967 | 95 /* load line 1 */ |
8625 | 96 ldq_u t5, 0(a2) # left_u |
97 ldq_u t6, 8(a2) # mid | |
98 ldq_u t7, 16(a2) # right_u | |
99 ldq t8, 0(a1) # ref left | |
100 ldq t9, 8(a1) # ref right | |
101 addq a1, a3, a1 # pix1 | |
102 addq a2, a3, a2 # pix2 | |
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103 /* calc line 0 */ |
8625 | 104 extql t0, a2, t0 # left lo |
105 extqh t1, a2, ta # left hi | |
106 extql t1, a2, tb # right lo | |
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107 or t0, ta, t0 # left |
8625 | 108 extqh t2, a2, t2 # right hi |
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109 perr t3, t0, tc # error left |
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110 or t2, tb, t2 # right |
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111 perr t4, t2, td # error right |
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112 addq v0, tc, v0 # add error left |
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113 addq v0, td, v0 # add error left |
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114 /* calc line 1 */ |
8625 | 115 extql t5, a2, t5 # left lo |
116 extqh t6, a2, ta # left hi | |
117 extql t6, a2, tb # right lo | |
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118 or t5, ta, t5 # left |
8625 | 119 extqh t7, a2, t7 # right hi |
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120 perr t8, t5, tc # error left |
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121 or t7, tb, t7 # right |
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122 perr t9, t7, td # error right |
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123 addq v0, tc, v0 # add error left |
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124 addq v0, td, v0 # add error left |
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125 /* loop */ |
8625 | 126 subq a4, 2, a4 # h -= 2 |
127 bne a4, $unaligned | |
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128 ret |
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129 |
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130 .align 4 |
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131 $aligned: |
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132 /* load line 0 */ |
8625 | 133 ldq t0, 0(a2) # left |
134 ldq t1, 8(a2) # right | |
135 addq a2, a3, a2 # pix2 | |
136 ldq t2, 0(a1) # ref left | |
137 ldq t3, 8(a1) # ref right | |
138 addq a1, a3, a1 # pix1 | |
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139 /* load line 1 */ |
8625 | 140 ldq t4, 0(a2) # left |
141 ldq t5, 8(a2) # right | |
142 addq a2, a3, a2 # pix2 | |
143 ldq t6, 0(a1) # ref left | |
144 ldq t7, 8(a1) # ref right | |
145 addq a1, a3, a1 # pix1 | |
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146 /* load line 2 */ |
8625 | 147 ldq t8, 0(a2) # left |
148 ldq t9, 8(a2) # right | |
149 addq a2, a3, a2 # pix2 | |
150 ldq ta, 0(a1) # ref left | |
151 ldq tb, 8(a1) # ref right | |
152 addq a1, a3, a1 # pix1 | |
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153 /* load line 3 */ |
8625 | 154 ldq tc, 0(a2) # left |
155 ldq td, 8(a2) # right | |
156 addq a2, a3, a2 # pix2 | |
157 ldq te, 0(a1) # ref left | |
158 ldq a0, 8(a1) # ref right | |
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159 /* calc line 0 */ |
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160 perr t0, t2, t0 # error left |
8625 | 161 addq a1, a3, a1 # pix1 |
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162 perr t1, t3, t1 # error right |
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163 addq v0, t0, v0 # add error left |
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164 /* calc line 1 */ |
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165 perr t4, t6, t0 # error left |
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166 addq v0, t1, v0 # add error right |
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167 perr t5, t7, t1 # error right |
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168 addq v0, t0, v0 # add error left |
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169 /* calc line 2 */ |
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170 perr t8, ta, t0 # error left |
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171 addq v0, t1, v0 # add error right |
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172 perr t9, tb, t1 # error right |
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173 addq v0, t0, v0 # add error left |
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174 /* calc line 3 */ |
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175 perr tc, te, t0 # error left |
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176 addq v0, t1, v0 # add error right |
8625 | 177 perr td, a0, t1 # error right |
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178 addq v0, t0, v0 # add error left |
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179 addq v0, t1, v0 # add error right |
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180 /* loop */ |
8625 | 181 subq a4, 4, a4 # h -= 4 |
182 bne a4, $aligned | |
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183 ret |
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184 .end pix_abs16x16_mvi_asm |