annotate arm/dsputil_armv6.S @ 11229:d53e56a6228b libavcodec

Simplify determing whether fragments are coded No measurable speed difference
author conrad
date Sun, 21 Feb 2010 00:11:01 +0000
parents ad6d17b36a3a
children cbf3161706f4
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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e55d957ef1a2 ARM: ARMv6 optimised add_pixels_clamped()
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1 /*
e55d957ef1a2 ARM: ARMv6 optimised add_pixels_clamped()
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2 * Copyright (c) 2009 Mans Rullgard <mans@mansr.com>
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3 *
e55d957ef1a2 ARM: ARMv6 optimised add_pixels_clamped()
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4 * This file is part of FFmpeg.
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5 *
e55d957ef1a2 ARM: ARMv6 optimised add_pixels_clamped()
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6 * FFmpeg is free software; you can redistribute it and/or
e55d957ef1a2 ARM: ARMv6 optimised add_pixels_clamped()
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7 * modify it under the terms of the GNU Lesser General Public
e55d957ef1a2 ARM: ARMv6 optimised add_pixels_clamped()
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8 * License as published by the Free Software Foundation; either
e55d957ef1a2 ARM: ARMv6 optimised add_pixels_clamped()
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9 * version 2.1 of the License, or (at your option) any later version.
e55d957ef1a2 ARM: ARMv6 optimised add_pixels_clamped()
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10 *
e55d957ef1a2 ARM: ARMv6 optimised add_pixels_clamped()
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11 * FFmpeg is distributed in the hope that it will be useful,
e55d957ef1a2 ARM: ARMv6 optimised add_pixels_clamped()
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12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
e55d957ef1a2 ARM: ARMv6 optimised add_pixels_clamped()
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13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
e55d957ef1a2 ARM: ARMv6 optimised add_pixels_clamped()
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14 * Lesser General Public License for more details.
e55d957ef1a2 ARM: ARMv6 optimised add_pixels_clamped()
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15 *
e55d957ef1a2 ARM: ARMv6 optimised add_pixels_clamped()
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16 * You should have received a copy of the GNU Lesser General Public
e55d957ef1a2 ARM: ARMv6 optimised add_pixels_clamped()
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17 * License along with FFmpeg; if not, write to the Free Software
e55d957ef1a2 ARM: ARMv6 optimised add_pixels_clamped()
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18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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19 */
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20
e55d957ef1a2 ARM: ARMv6 optimised add_pixels_clamped()
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21 #include "asm.S"
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22
e55d957ef1a2 ARM: ARMv6 optimised add_pixels_clamped()
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23 .text
e55d957ef1a2 ARM: ARMv6 optimised add_pixels_clamped()
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24
11108
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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25 .macro call_2x_pixels type, subp
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26 function ff_\type\()_pixels16\subp\()_armv6, export=1
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27 push {r0-r3, lr}
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28 bl ff_\type\()_pixels8\subp\()_armv6
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29 pop {r0-r3, lr}
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30 add r0, r0, #8
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31 add r1, r1, #8
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32 b ff_\type\()_pixels8\subp\()_armv6
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33 .endfunc
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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34 .endm
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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35
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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36 call_2x_pixels avg
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37 call_2x_pixels put, _x2
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38 call_2x_pixels put, _y2
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39 call_2x_pixels put, _x2_no_rnd
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40 call_2x_pixels put, _y2_no_rnd
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41
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42 function ff_put_pixels16_armv6, export=1
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43 push {r4-r11}
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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44 1:
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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45 ldr r5, [r1, #4]
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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46 ldr r6, [r1, #8]
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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47 ldr r7, [r1, #12]
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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48 ldr r4, [r1], r2
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49 strd r6, r7, [r0, #8]
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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50 ldr r9, [r1, #4]
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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51 strd r4, r5, [r0], r2
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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52 ldr r10, [r1, #8]
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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53 ldr r11, [r1, #12]
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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54 ldr r8, [r1], r2
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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55 strd r10, r11, [r0, #8]
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56 subs r3, r3, #2
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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57 strd r8, r9, [r0], r2
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58 bne 1b
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59
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60 pop {r4-r11}
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61 bx lr
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62 .endfunc
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63
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64 function ff_put_pixels8_armv6, export=1
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65 push {r4-r7}
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66 1:
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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67 ldr r5, [r1, #4]
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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68 ldr r4, [r1], r2
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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69 ldr r7, [r1, #4]
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70 strd r4, r5, [r0], r2
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71 ldr r6, [r1], r2
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72 subs r3, r3, #2
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73 strd r6, r7, [r0], r2
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74 bne 1b
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75
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76 pop {r4-r7}
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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77 bx lr
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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78 .endfunc
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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79
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80 function ff_put_pixels8_x2_armv6, export=1
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81 push {r4-r11, lr}
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82 mov r12, #1
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83 orr r12, r12, r12, lsl #8
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84 orr r12, r12, r12, lsl #16
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85 1:
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86 ldr r4, [r1]
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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87 subs r3, r3, #2
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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88 ldr r5, [r1, #4]
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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89 ldr r7, [r1, #5]
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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90 lsr r6, r4, #8
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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91 ldr r8, [r1, r2]!
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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92 orr r6, r6, r5, lsl #24
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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93 ldr r9, [r1, #4]
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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94 ldr r11, [r1, #5]
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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95 lsr r10, r8, #8
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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96 add r1, r1, r2
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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97 orr r10, r10, r9, lsl #24
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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98 eor r14, r4, r6
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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99 uhadd8 r4, r4, r6
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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100 eor r6, r5, r7
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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101 uhadd8 r5, r5, r7
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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102 and r14, r14, r12
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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103 and r6, r6, r12
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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104 uadd8 r4, r4, r14
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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105 eor r14, r8, r10
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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106 uadd8 r5, r5, r6
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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107 eor r6, r9, r11
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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108 uhadd8 r8, r8, r10
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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109 and r14, r14, r12
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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110 uhadd8 r9, r9, r11
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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111 and r6, r6, r12
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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112 uadd8 r8, r8, r14
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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113 strd r4, r5, [r0], r2
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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114 uadd8 r9, r9, r6
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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115 strd r8, r9, [r0], r2
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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116 bne 1b
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117
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118 pop {r4-r11, pc}
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119 .endfunc
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120
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121 function ff_put_pixels8_y2_armv6, export=1
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122 push {r4-r11}
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123 mov r12, #1
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124 orr r12, r12, r12, lsl #8
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125 orr r12, r12, r12, lsl #16
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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126 ldr r4, [r1]
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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127 ldr r5, [r1, #4]
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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128 ldr r6, [r1, r2]!
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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129 ldr r7, [r1, #4]
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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130 1:
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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131 subs r3, r3, #2
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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132 uhadd8 r8, r4, r6
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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133 eor r10, r4, r6
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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134 uhadd8 r9, r5, r7
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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135 eor r11, r5, r7
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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136 and r10, r10, r12
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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137 ldr r4, [r1, r2]!
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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138 uadd8 r8, r8, r10
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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139 and r11, r11, r12
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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140 uadd8 r9, r9, r11
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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141 ldr r5, [r1, #4]
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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142 uhadd8 r10, r4, r6
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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143 eor r6, r4, r6
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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144 uhadd8 r11, r5, r7
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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145 and r6, r6, r12
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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146 eor r7, r5, r7
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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147 uadd8 r10, r10, r6
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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148 and r7, r7, r12
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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149 ldr r6, [r1, r2]!
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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150 uadd8 r11, r11, r7
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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151 strd r8, r9, [r0], r2
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
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152 ldr r7, [r1, #4]
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153 strd r10, r11, [r0], r2
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diff changeset
154 bne 1b
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
155
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
156 pop {r4-r11}
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
157 bx lr
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
158 .endfunc
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
159
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
160 function ff_put_pixels8_x2_no_rnd_armv6, export=1
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
161 push {r4-r9, lr}
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
162 1:
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
163 subs r3, r3, #2
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
164 ldr r4, [r1]
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
165 ldr r5, [r1, #4]
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
166 ldr r7, [r1, #5]
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
167 ldr r8, [r1, r2]!
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
168 ldr r9, [r1, #4]
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
169 ldr r14, [r1, #5]
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
170 add r1, r1, r2
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
171 lsr r6, r4, #8
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
172 orr r6, r6, r5, lsl #24
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
173 lsr r12, r8, #8
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
174 orr r12, r12, r9, lsl #24
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
175 uhadd8 r4, r4, r6
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
176 uhadd8 r5, r5, r7
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
177 uhadd8 r8, r8, r12
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
178 uhadd8 r9, r9, r14
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
179 stm r0, {r4,r5}
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
180 add r0, r0, r2
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
181 stm r0, {r8,r9}
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
182 add r0, r0, r2
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
183 bne 1b
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
184
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
185 pop {r4-r9, pc}
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
186 .endfunc
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
187
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
188 function ff_put_pixels8_y2_no_rnd_armv6, export=1
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
189 push {r4-r9, lr}
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
190 ldr r4, [r1]
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
191 ldr r5, [r1, #4]
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
192 ldr r6, [r1, r2]!
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
193 ldr r7, [r1, #4]
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
194 1:
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
195 subs r3, r3, #2
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
196 uhadd8 r8, r4, r6
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
197 ldr r4, [r1, r2]!
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
198 uhadd8 r9, r5, r7
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
199 ldr r5, [r1, #4]
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
200 uhadd8 r12, r4, r6
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
201 ldr r6, [r1, r2]!
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
202 uhadd8 r14, r5, r7
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
203 ldr r7, [r1, #4]
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
204 stm r0, {r8,r9}
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
205 add r0, r0, r2
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
206 stm r0, {r12,r14}
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
207 add r0, r0, r2
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
208 bne 1b
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
209
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
210 pop {r4-r9, pc}
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
211 .endfunc
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
212
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
213 function ff_avg_pixels8_armv6, export=1
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
214 pld [r1, r2]
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
215 push {r4-r10, lr}
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
216 mov lr, #1
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
217 orr lr, lr, lr, lsl #8
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
218 orr lr, lr, lr, lsl #16
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
219 ldrd r4, r5, [r0]
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
220 ldr r10, [r1, #4]
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
221 ldr r9, [r1], r2
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
222 subs r3, r3, #2
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
223 1:
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
224 pld [r1, r2]
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
225 eor r8, r4, r9
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
226 uhadd8 r4, r4, r9
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
227 eor r12, r5, r10
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
228 ldrd r6, r7, [r0, r2]
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
229 uhadd8 r5, r5, r10
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
230 and r8, r8, lr
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
231 ldr r10, [r1, #4]
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
232 and r12, r12, lr
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
233 uadd8 r4, r4, r8
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
234 ldr r9, [r1], r2
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
235 eor r8, r6, r9
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
236 uadd8 r5, r5, r12
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
237 pld [r1, r2, lsl #1]
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
238 eor r12, r7, r10
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
239 uhadd8 r6, r6, r9
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
240 strd r4, r5, [r0], r2
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
241 uhadd8 r7, r7, r10
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
242 beq 2f
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
243 and r8, r8, lr
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
244 ldrd r4, r5, [r0, r2]
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
245 uadd8 r6, r6, r8
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
246 ldr r10, [r1, #4]
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
247 and r12, r12, lr
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
248 subs r3, r3, #2
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
249 uadd8 r7, r7, r12
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
250 ldr r9, [r1], r2
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
251 strd r6, r7, [r0], r2
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
252 b 1b
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
253 2:
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
254 and r8, r8, lr
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
255 and r12, r12, lr
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
256 uadd8 r6, r6, r8
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
257 uadd8 r7, r7, r12
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
258 strd r6, r7, [r0], r2
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
259
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
260 pop {r4-r10, pc}
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
261 .endfunc
0f845e20982a ARMv6 optimised put_pixels functions except xy2 variants
mru
parents: 10372
diff changeset
262
10372
e55d957ef1a2 ARM: ARMv6 optimised add_pixels_clamped()
mru
parents:
diff changeset
263 function ff_add_pixels_clamped_armv6, export=1
e55d957ef1a2 ARM: ARMv6 optimised add_pixels_clamped()
mru
parents:
diff changeset
264 push {r4-r8,lr}
e55d957ef1a2 ARM: ARMv6 optimised add_pixels_clamped()
mru
parents:
diff changeset
265 mov r3, #8
e55d957ef1a2 ARM: ARMv6 optimised add_pixels_clamped()
mru
parents:
diff changeset
266 1:
e55d957ef1a2 ARM: ARMv6 optimised add_pixels_clamped()
mru
parents:
diff changeset
267 ldm r0!, {r4,r5,r12,lr}
e55d957ef1a2 ARM: ARMv6 optimised add_pixels_clamped()
mru
parents:
diff changeset
268 ldrd r6, r7, [r1]
e55d957ef1a2 ARM: ARMv6 optimised add_pixels_clamped()
mru
parents:
diff changeset
269 pkhbt r8, r4, r5, lsl #16
e55d957ef1a2 ARM: ARMv6 optimised add_pixels_clamped()
mru
parents:
diff changeset
270 pkhtb r5, r5, r4, asr #16
e55d957ef1a2 ARM: ARMv6 optimised add_pixels_clamped()
mru
parents:
diff changeset
271 pkhbt r4, r12, lr, lsl #16
e55d957ef1a2 ARM: ARMv6 optimised add_pixels_clamped()
mru
parents:
diff changeset
272 pkhtb lr, lr, r12, asr #16
e55d957ef1a2 ARM: ARMv6 optimised add_pixels_clamped()
mru
parents:
diff changeset
273 pld [r1, r2]
e55d957ef1a2 ARM: ARMv6 optimised add_pixels_clamped()
mru
parents:
diff changeset
274 uxtab16 r8, r8, r6
e55d957ef1a2 ARM: ARMv6 optimised add_pixels_clamped()
mru
parents:
diff changeset
275 uxtab16 r5, r5, r6, ror #8
e55d957ef1a2 ARM: ARMv6 optimised add_pixels_clamped()
mru
parents:
diff changeset
276 uxtab16 r4, r4, r7
e55d957ef1a2 ARM: ARMv6 optimised add_pixels_clamped()
mru
parents:
diff changeset
277 uxtab16 lr, lr, r7, ror #8
e55d957ef1a2 ARM: ARMv6 optimised add_pixels_clamped()
mru
parents:
diff changeset
278 usat16 r8, #8, r8
e55d957ef1a2 ARM: ARMv6 optimised add_pixels_clamped()
mru
parents:
diff changeset
279 usat16 r5, #8, r5
e55d957ef1a2 ARM: ARMv6 optimised add_pixels_clamped()
mru
parents:
diff changeset
280 usat16 r4, #8, r4
e55d957ef1a2 ARM: ARMv6 optimised add_pixels_clamped()
mru
parents:
diff changeset
281 usat16 lr, #8, lr
e55d957ef1a2 ARM: ARMv6 optimised add_pixels_clamped()
mru
parents:
diff changeset
282 orr r6, r8, r5, lsl #8
e55d957ef1a2 ARM: ARMv6 optimised add_pixels_clamped()
mru
parents:
diff changeset
283 orr r7, r4, lr, lsl #8
e55d957ef1a2 ARM: ARMv6 optimised add_pixels_clamped()
mru
parents:
diff changeset
284 subs r3, r3, #1
e55d957ef1a2 ARM: ARMv6 optimised add_pixels_clamped()
mru
parents:
diff changeset
285 strd r6, r7, [r1], r2
e55d957ef1a2 ARM: ARMv6 optimised add_pixels_clamped()
mru
parents:
diff changeset
286 bgt 1b
e55d957ef1a2 ARM: ARMv6 optimised add_pixels_clamped()
mru
parents:
diff changeset
287 pop {r4-r8,pc}
e55d957ef1a2 ARM: ARMv6 optimised add_pixels_clamped()
mru
parents:
diff changeset
288 .endfunc
11109
9f00412b0bc8 ARMv6 optimised pix_abs16
mru
parents: 11108
diff changeset
289
11113
b529129c4563 ARMv6 optimised get_pixels
mru
parents: 11112
diff changeset
290 function ff_get_pixels_armv6, export=1
b529129c4563 ARMv6 optimised get_pixels
mru
parents: 11112
diff changeset
291 pld [r1, r2]
b529129c4563 ARMv6 optimised get_pixels
mru
parents: 11112
diff changeset
292 push {r4-r8, lr}
b529129c4563 ARMv6 optimised get_pixels
mru
parents: 11112
diff changeset
293 mov lr, #8
b529129c4563 ARMv6 optimised get_pixels
mru
parents: 11112
diff changeset
294 1:
b529129c4563 ARMv6 optimised get_pixels
mru
parents: 11112
diff changeset
295 ldrd r4, r5, [r1], r2
b529129c4563 ARMv6 optimised get_pixels
mru
parents: 11112
diff changeset
296 subs lr, lr, #1
b529129c4563 ARMv6 optimised get_pixels
mru
parents: 11112
diff changeset
297 uxtb16 r6, r4
b529129c4563 ARMv6 optimised get_pixels
mru
parents: 11112
diff changeset
298 uxtb16 r4, r4, ror #8
b529129c4563 ARMv6 optimised get_pixels
mru
parents: 11112
diff changeset
299 uxtb16 r12, r5
b529129c4563 ARMv6 optimised get_pixels
mru
parents: 11112
diff changeset
300 uxtb16 r8, r5, ror #8
b529129c4563 ARMv6 optimised get_pixels
mru
parents: 11112
diff changeset
301 pld [r1, r2]
b529129c4563 ARMv6 optimised get_pixels
mru
parents: 11112
diff changeset
302 pkhbt r5, r6, r4, lsl #16
b529129c4563 ARMv6 optimised get_pixels
mru
parents: 11112
diff changeset
303 pkhtb r6, r4, r6, asr #16
b529129c4563 ARMv6 optimised get_pixels
mru
parents: 11112
diff changeset
304 pkhbt r7, r12, r8, lsl #16
b529129c4563 ARMv6 optimised get_pixels
mru
parents: 11112
diff changeset
305 pkhtb r12, r8, r12, asr #16
b529129c4563 ARMv6 optimised get_pixels
mru
parents: 11112
diff changeset
306 stm r0!, {r5,r6,r7,r12}
b529129c4563 ARMv6 optimised get_pixels
mru
parents: 11112
diff changeset
307 bgt 1b
b529129c4563 ARMv6 optimised get_pixels
mru
parents: 11112
diff changeset
308
b529129c4563 ARMv6 optimised get_pixels
mru
parents: 11112
diff changeset
309 pop {r4-r8, pc}
b529129c4563 ARMv6 optimised get_pixels
mru
parents: 11112
diff changeset
310 .endfunc
b529129c4563 ARMv6 optimised get_pixels
mru
parents: 11112
diff changeset
311
11114
852772c36cc6 ARMv6 optimised diff_pixels
mru
parents: 11113
diff changeset
312 function ff_diff_pixels_armv6, export=1
852772c36cc6 ARMv6 optimised diff_pixels
mru
parents: 11113
diff changeset
313 pld [r1, r3]
852772c36cc6 ARMv6 optimised diff_pixels
mru
parents: 11113
diff changeset
314 pld [r2, r3]
852772c36cc6 ARMv6 optimised diff_pixels
mru
parents: 11113
diff changeset
315 push {r4-r9, lr}
852772c36cc6 ARMv6 optimised diff_pixels
mru
parents: 11113
diff changeset
316 mov lr, #8
852772c36cc6 ARMv6 optimised diff_pixels
mru
parents: 11113
diff changeset
317 1:
852772c36cc6 ARMv6 optimised diff_pixels
mru
parents: 11113
diff changeset
318 ldrd r4, r5, [r1], r3
852772c36cc6 ARMv6 optimised diff_pixels
mru
parents: 11113
diff changeset
319 ldrd r6, r7, [r2], r3
852772c36cc6 ARMv6 optimised diff_pixels
mru
parents: 11113
diff changeset
320 uxtb16 r8, r4
852772c36cc6 ARMv6 optimised diff_pixels
mru
parents: 11113
diff changeset
321 uxtb16 r4, r4, ror #8
852772c36cc6 ARMv6 optimised diff_pixels
mru
parents: 11113
diff changeset
322 uxtb16 r9, r6
852772c36cc6 ARMv6 optimised diff_pixels
mru
parents: 11113
diff changeset
323 uxtb16 r6, r6, ror #8
852772c36cc6 ARMv6 optimised diff_pixels
mru
parents: 11113
diff changeset
324 pld [r1, r3]
852772c36cc6 ARMv6 optimised diff_pixels
mru
parents: 11113
diff changeset
325 ssub16 r9, r8, r9
852772c36cc6 ARMv6 optimised diff_pixels
mru
parents: 11113
diff changeset
326 ssub16 r6, r4, r6
852772c36cc6 ARMv6 optimised diff_pixels
mru
parents: 11113
diff changeset
327 uxtb16 r8, r5
852772c36cc6 ARMv6 optimised diff_pixels
mru
parents: 11113
diff changeset
328 uxtb16 r5, r5, ror #8
852772c36cc6 ARMv6 optimised diff_pixels
mru
parents: 11113
diff changeset
329 pld [r2, r3]
852772c36cc6 ARMv6 optimised diff_pixels
mru
parents: 11113
diff changeset
330 pkhbt r4, r9, r6, lsl #16
852772c36cc6 ARMv6 optimised diff_pixels
mru
parents: 11113
diff changeset
331 pkhtb r6, r6, r9, asr #16
852772c36cc6 ARMv6 optimised diff_pixels
mru
parents: 11113
diff changeset
332 uxtb16 r9, r7
852772c36cc6 ARMv6 optimised diff_pixels
mru
parents: 11113
diff changeset
333 uxtb16 r7, r7, ror #8
852772c36cc6 ARMv6 optimised diff_pixels
mru
parents: 11113
diff changeset
334 ssub16 r9, r8, r9
852772c36cc6 ARMv6 optimised diff_pixels
mru
parents: 11113
diff changeset
335 ssub16 r5, r5, r7
852772c36cc6 ARMv6 optimised diff_pixels
mru
parents: 11113
diff changeset
336 subs lr, lr, #1
852772c36cc6 ARMv6 optimised diff_pixels
mru
parents: 11113
diff changeset
337 pkhbt r8, r9, r5, lsl #16
852772c36cc6 ARMv6 optimised diff_pixels
mru
parents: 11113
diff changeset
338 pkhtb r9, r5, r9, asr #16
852772c36cc6 ARMv6 optimised diff_pixels
mru
parents: 11113
diff changeset
339 stm r0!, {r4,r6,r8,r9}
852772c36cc6 ARMv6 optimised diff_pixels
mru
parents: 11113
diff changeset
340 bgt 1b
852772c36cc6 ARMv6 optimised diff_pixels
mru
parents: 11113
diff changeset
341
852772c36cc6 ARMv6 optimised diff_pixels
mru
parents: 11113
diff changeset
342 pop {r4-r9, pc}
852772c36cc6 ARMv6 optimised diff_pixels
mru
parents: 11113
diff changeset
343 .endfunc
852772c36cc6 ARMv6 optimised diff_pixels
mru
parents: 11113
diff changeset
344
11109
9f00412b0bc8 ARMv6 optimised pix_abs16
mru
parents: 11108
diff changeset
345 function ff_pix_abs16_armv6, export=1
9f00412b0bc8 ARMv6 optimised pix_abs16
mru
parents: 11108
diff changeset
346 ldr r0, [sp]
9f00412b0bc8 ARMv6 optimised pix_abs16
mru
parents: 11108
diff changeset
347 push {r4-r9, lr}
9f00412b0bc8 ARMv6 optimised pix_abs16
mru
parents: 11108
diff changeset
348 mov r12, #0
9f00412b0bc8 ARMv6 optimised pix_abs16
mru
parents: 11108
diff changeset
349 mov lr, #0
9f00412b0bc8 ARMv6 optimised pix_abs16
mru
parents: 11108
diff changeset
350 ldm r1, {r4-r7}
9f00412b0bc8 ARMv6 optimised pix_abs16
mru
parents: 11108
diff changeset
351 ldr r8, [r2]
9f00412b0bc8 ARMv6 optimised pix_abs16
mru
parents: 11108
diff changeset
352 1:
9f00412b0bc8 ARMv6 optimised pix_abs16
mru
parents: 11108
diff changeset
353 ldr r9, [r2, #4]
9f00412b0bc8 ARMv6 optimised pix_abs16
mru
parents: 11108
diff changeset
354 pld [r1, r3]
9f00412b0bc8 ARMv6 optimised pix_abs16
mru
parents: 11108
diff changeset
355 usada8 r12, r4, r8, r12
9f00412b0bc8 ARMv6 optimised pix_abs16
mru
parents: 11108
diff changeset
356 ldr r8, [r2, #8]
9f00412b0bc8 ARMv6 optimised pix_abs16
mru
parents: 11108
diff changeset
357 pld [r2, r3]
9f00412b0bc8 ARMv6 optimised pix_abs16
mru
parents: 11108
diff changeset
358 usada8 lr, r5, r9, lr
9f00412b0bc8 ARMv6 optimised pix_abs16
mru
parents: 11108
diff changeset
359 ldr r9, [r2, #12]
9f00412b0bc8 ARMv6 optimised pix_abs16
mru
parents: 11108
diff changeset
360 usada8 r12, r6, r8, r12
9f00412b0bc8 ARMv6 optimised pix_abs16
mru
parents: 11108
diff changeset
361 subs r0, r0, #1
9f00412b0bc8 ARMv6 optimised pix_abs16
mru
parents: 11108
diff changeset
362 usada8 lr, r7, r9, lr
9f00412b0bc8 ARMv6 optimised pix_abs16
mru
parents: 11108
diff changeset
363 beq 2f
9f00412b0bc8 ARMv6 optimised pix_abs16
mru
parents: 11108
diff changeset
364 add r1, r1, r3
9f00412b0bc8 ARMv6 optimised pix_abs16
mru
parents: 11108
diff changeset
365 ldm r1, {r4-r7}
9f00412b0bc8 ARMv6 optimised pix_abs16
mru
parents: 11108
diff changeset
366 add r2, r2, r3
9f00412b0bc8 ARMv6 optimised pix_abs16
mru
parents: 11108
diff changeset
367 ldr r8, [r2]
9f00412b0bc8 ARMv6 optimised pix_abs16
mru
parents: 11108
diff changeset
368 b 1b
9f00412b0bc8 ARMv6 optimised pix_abs16
mru
parents: 11108
diff changeset
369 2:
9f00412b0bc8 ARMv6 optimised pix_abs16
mru
parents: 11108
diff changeset
370 add r0, r12, lr
9f00412b0bc8 ARMv6 optimised pix_abs16
mru
parents: 11108
diff changeset
371 pop {r4-r9, pc}
9f00412b0bc8 ARMv6 optimised pix_abs16
mru
parents: 11108
diff changeset
372 .endfunc
11110
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
373
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
374 function ff_pix_abs16_x2_armv6, export=1
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
375 ldr r12, [sp]
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
376 push {r4-r11, lr}
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
377 mov r0, #0
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
378 mov lr, #1
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
379 orr lr, lr, lr, lsl #8
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
380 orr lr, lr, lr, lsl #16
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
381 1:
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
382 ldr r8, [r2]
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
383 ldr r9, [r2, #4]
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
384 lsr r10, r8, #8
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
385 ldr r4, [r1]
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
386 lsr r6, r9, #8
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
387 orr r10, r10, r9, lsl #24
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
388 ldr r5, [r2, #8]
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
389 eor r11, r8, r10
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
390 uhadd8 r7, r8, r10
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
391 orr r6, r6, r5, lsl #24
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
392 and r11, r11, lr
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
393 uadd8 r7, r7, r11
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
394 ldr r8, [r1, #4]
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
395 usada8 r0, r4, r7, r0
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
396 eor r7, r9, r6
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
397 lsr r10, r5, #8
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
398 and r7, r7, lr
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
399 uhadd8 r4, r9, r6
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
400 ldr r6, [r2, #12]
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
401 uadd8 r4, r4, r7
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
402 pld [r1, r3]
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
403 orr r10, r10, r6, lsl #24
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
404 usada8 r0, r8, r4, r0
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
405 ldr r4, [r1, #8]
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
406 eor r11, r5, r10
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
407 ldrb r7, [r2, #16]
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
408 and r11, r11, lr
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
409 uhadd8 r8, r5, r10
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
410 ldr r5, [r1, #12]
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
411 uadd8 r8, r8, r11
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
412 pld [r2, r3]
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
413 lsr r10, r6, #8
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
414 usada8 r0, r4, r8, r0
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
415 orr r10, r10, r7, lsl #24
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
416 subs r12, r12, #1
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
417 eor r11, r6, r10
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
418 add r1, r1, r3
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
419 uhadd8 r9, r6, r10
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
420 and r11, r11, lr
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
421 uadd8 r9, r9, r11
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
422 add r2, r2, r3
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
423 usada8 r0, r5, r9, r0
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
424 bgt 1b
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
425
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
426 pop {r4-r11, pc}
45de2da90eaf ARMv6 optimised pix_abs16_x2
mru
parents: 11109
diff changeset
427 .endfunc
11111
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
428
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
429 .macro usad_y2 p0, p1, p2, p3, n0, n1, n2, n3
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
430 ldr \n0, [r2]
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
431 eor \n1, \p0, \n0
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
432 uhadd8 \p0, \p0, \n0
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
433 and \n1, \n1, lr
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
434 ldr \n2, [r1]
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
435 uadd8 \p0, \p0, \n1
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
436 ldr \n1, [r2, #4]
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
437 usada8 r0, \p0, \n2, r0
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
438 pld [r1, r3]
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
439 eor \n3, \p1, \n1
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
440 uhadd8 \p1, \p1, \n1
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
441 and \n3, \n3, lr
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
442 ldr \p0, [r1, #4]
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
443 uadd8 \p1, \p1, \n3
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
444 ldr \n2, [r2, #8]
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
445 usada8 r0, \p1, \p0, r0
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
446 pld [r2, r3]
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
447 eor \p0, \p2, \n2
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
448 uhadd8 \p2, \p2, \n2
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
449 and \p0, \p0, lr
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
450 ldr \p1, [r1, #8]
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
451 uadd8 \p2, \p2, \p0
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
452 ldr \n3, [r2, #12]
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
453 usada8 r0, \p2, \p1, r0
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
454 eor \p1, \p3, \n3
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
455 uhadd8 \p3, \p3, \n3
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
456 and \p1, \p1, lr
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
457 ldr \p0, [r1, #12]
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
458 uadd8 \p3, \p3, \p1
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
459 add r1, r1, r3
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
460 usada8 r0, \p3, \p0, r0
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
461 add r2, r2, r3
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
462 .endm
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
463
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
464 function ff_pix_abs16_y2_armv6, export=1
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
465 pld [r1]
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
466 pld [r2]
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
467 ldr r12, [sp]
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
468 push {r4-r11, lr}
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
469 mov r0, #0
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
470 mov lr, #1
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
471 orr lr, lr, lr, lsl #8
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
472 orr lr, lr, lr, lsl #16
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
473 ldr r4, [r2]
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
474 ldr r5, [r2, #4]
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
475 ldr r6, [r2, #8]
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
476 ldr r7, [r2, #12]
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
477 add r2, r2, r3
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
478 1:
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
479 usad_y2 r4, r5, r6, r7, r8, r9, r10, r11
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
480 subs r12, r12, #2
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
481 usad_y2 r8, r9, r10, r11, r4, r5, r6, r7
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
482 bgt 1b
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
483
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
484 pop {r4-r11, pc}
95b1fd6057d3 ARMv6 optimised pix_abs16_y2
mru
parents: 11110
diff changeset
485 .endfunc
11112
ffe1ea72ea29 ARMv6 optimised pix_abs8
mru
parents: 11111
diff changeset
486
ffe1ea72ea29 ARMv6 optimised pix_abs8
mru
parents: 11111
diff changeset
487 function ff_pix_abs8_armv6, export=1
ffe1ea72ea29 ARMv6 optimised pix_abs8
mru
parents: 11111
diff changeset
488 pld [r2, r3]
ffe1ea72ea29 ARMv6 optimised pix_abs8
mru
parents: 11111
diff changeset
489 ldr r12, [sp]
ffe1ea72ea29 ARMv6 optimised pix_abs8
mru
parents: 11111
diff changeset
490 push {r4-r9, lr}
ffe1ea72ea29 ARMv6 optimised pix_abs8
mru
parents: 11111
diff changeset
491 mov r0, #0
ffe1ea72ea29 ARMv6 optimised pix_abs8
mru
parents: 11111
diff changeset
492 mov lr, #0
ffe1ea72ea29 ARMv6 optimised pix_abs8
mru
parents: 11111
diff changeset
493 ldrd r4, r5, [r1], r3
ffe1ea72ea29 ARMv6 optimised pix_abs8
mru
parents: 11111
diff changeset
494 1:
ffe1ea72ea29 ARMv6 optimised pix_abs8
mru
parents: 11111
diff changeset
495 subs r12, r12, #2
ffe1ea72ea29 ARMv6 optimised pix_abs8
mru
parents: 11111
diff changeset
496 ldr r7, [r2, #4]
ffe1ea72ea29 ARMv6 optimised pix_abs8
mru
parents: 11111
diff changeset
497 ldr r6, [r2], r3
ffe1ea72ea29 ARMv6 optimised pix_abs8
mru
parents: 11111
diff changeset
498 ldrd r8, r9, [r1], r3
ffe1ea72ea29 ARMv6 optimised pix_abs8
mru
parents: 11111
diff changeset
499 usada8 r0, r4, r6, r0
ffe1ea72ea29 ARMv6 optimised pix_abs8
mru
parents: 11111
diff changeset
500 pld [r2, r3]
ffe1ea72ea29 ARMv6 optimised pix_abs8
mru
parents: 11111
diff changeset
501 usada8 lr, r5, r7, lr
ffe1ea72ea29 ARMv6 optimised pix_abs8
mru
parents: 11111
diff changeset
502 ldr r7, [r2, #4]
ffe1ea72ea29 ARMv6 optimised pix_abs8
mru
parents: 11111
diff changeset
503 ldr r6, [r2], r3
ffe1ea72ea29 ARMv6 optimised pix_abs8
mru
parents: 11111
diff changeset
504 beq 2f
ffe1ea72ea29 ARMv6 optimised pix_abs8
mru
parents: 11111
diff changeset
505 ldrd r4, r5, [r1], r3
ffe1ea72ea29 ARMv6 optimised pix_abs8
mru
parents: 11111
diff changeset
506 usada8 r0, r8, r6, r0
ffe1ea72ea29 ARMv6 optimised pix_abs8
mru
parents: 11111
diff changeset
507 pld [r2, r3]
ffe1ea72ea29 ARMv6 optimised pix_abs8
mru
parents: 11111
diff changeset
508 usada8 lr, r9, r7, lr
ffe1ea72ea29 ARMv6 optimised pix_abs8
mru
parents: 11111
diff changeset
509 b 1b
ffe1ea72ea29 ARMv6 optimised pix_abs8
mru
parents: 11111
diff changeset
510 2:
ffe1ea72ea29 ARMv6 optimised pix_abs8
mru
parents: 11111
diff changeset
511 usada8 r0, r8, r6, r0
ffe1ea72ea29 ARMv6 optimised pix_abs8
mru
parents: 11111
diff changeset
512 usada8 lr, r9, r7, lr
ffe1ea72ea29 ARMv6 optimised pix_abs8
mru
parents: 11111
diff changeset
513 add r0, r0, lr
ffe1ea72ea29 ARMv6 optimised pix_abs8
mru
parents: 11111
diff changeset
514 pop {r4-r9, pc}
ffe1ea72ea29 ARMv6 optimised pix_abs8
mru
parents: 11111
diff changeset
515 .endfunc
11115
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
516
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
517 function ff_sse16_armv6, export=1
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
518 ldr r12, [sp]
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
519 push {r4-r9, lr}
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
520 mov r0, #0
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
521 1:
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
522 ldrd r4, r5, [r1]
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
523 ldr r8, [r2]
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
524 uxtb16 lr, r4
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
525 uxtb16 r4, r4, ror #8
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
526 uxtb16 r9, r8
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
527 uxtb16 r8, r8, ror #8
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
528 ldr r7, [r2, #4]
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
529 usub16 lr, lr, r9
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
530 usub16 r4, r4, r8
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
531 smlad r0, lr, lr, r0
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
532 uxtb16 r6, r5
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
533 uxtb16 lr, r5, ror #8
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
534 uxtb16 r8, r7
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
535 uxtb16 r9, r7, ror #8
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
536 smlad r0, r4, r4, r0
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
537 ldrd r4, r5, [r1, #8]
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
538 usub16 r6, r6, r8
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
539 usub16 r8, lr, r9
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
540 ldr r7, [r2, #8]
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
541 smlad r0, r6, r6, r0
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
542 uxtb16 lr, r4
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
543 uxtb16 r4, r4, ror #8
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
544 uxtb16 r9, r7
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
545 uxtb16 r7, r7, ror #8
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
546 smlad r0, r8, r8, r0
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
547 ldr r8, [r2, #12]
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
548 usub16 lr, lr, r9
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
549 usub16 r4, r4, r7
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
550 smlad r0, lr, lr, r0
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
551 uxtb16 r6, r5
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
552 uxtb16 r5, r5, ror #8
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
553 uxtb16 r9, r8
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
554 uxtb16 r8, r8, ror #8
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
555 smlad r0, r4, r4, r0
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
556 usub16 r6, r6, r9
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
557 usub16 r5, r5, r8
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
558 smlad r0, r6, r6, r0
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
559 add r1, r1, r3
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
560 add r2, r2, r3
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
561 subs r12, r12, #1
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
562 smlad r0, r5, r5, r0
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
563 bgt 1b
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
564
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
565 pop {r4-r9, pc}
3fba8a5c6288 ARMv6 optimised sse16
mru
parents: 11114
diff changeset
566 .endfunc
11116
0198e3582544 ARMv6 optimised pix_norm1
mru
parents: 11115
diff changeset
567
0198e3582544 ARMv6 optimised pix_norm1
mru
parents: 11115
diff changeset
568 function ff_pix_norm1_armv6, export=1
0198e3582544 ARMv6 optimised pix_norm1
mru
parents: 11115
diff changeset
569 push {r4-r6, lr}
0198e3582544 ARMv6 optimised pix_norm1
mru
parents: 11115
diff changeset
570 mov r12, #16
0198e3582544 ARMv6 optimised pix_norm1
mru
parents: 11115
diff changeset
571 mov lr, #0
0198e3582544 ARMv6 optimised pix_norm1
mru
parents: 11115
diff changeset
572 1:
0198e3582544 ARMv6 optimised pix_norm1
mru
parents: 11115
diff changeset
573 ldm r0, {r2-r5}
0198e3582544 ARMv6 optimised pix_norm1
mru
parents: 11115
diff changeset
574 uxtb16 r6, r2
0198e3582544 ARMv6 optimised pix_norm1
mru
parents: 11115
diff changeset
575 uxtb16 r2, r2, ror #8
0198e3582544 ARMv6 optimised pix_norm1
mru
parents: 11115
diff changeset
576 smlad lr, r6, r6, lr
0198e3582544 ARMv6 optimised pix_norm1
mru
parents: 11115
diff changeset
577 uxtb16 r6, r3
0198e3582544 ARMv6 optimised pix_norm1
mru
parents: 11115
diff changeset
578 smlad lr, r2, r2, lr
0198e3582544 ARMv6 optimised pix_norm1
mru
parents: 11115
diff changeset
579 uxtb16 r3, r3, ror #8
0198e3582544 ARMv6 optimised pix_norm1
mru
parents: 11115
diff changeset
580 smlad lr, r6, r6, lr
0198e3582544 ARMv6 optimised pix_norm1
mru
parents: 11115
diff changeset
581 uxtb16 r6, r4
0198e3582544 ARMv6 optimised pix_norm1
mru
parents: 11115
diff changeset
582 smlad lr, r3, r3, lr
0198e3582544 ARMv6 optimised pix_norm1
mru
parents: 11115
diff changeset
583 uxtb16 r4, r4, ror #8
0198e3582544 ARMv6 optimised pix_norm1
mru
parents: 11115
diff changeset
584 smlad lr, r6, r6, lr
0198e3582544 ARMv6 optimised pix_norm1
mru
parents: 11115
diff changeset
585 uxtb16 r6, r5
0198e3582544 ARMv6 optimised pix_norm1
mru
parents: 11115
diff changeset
586 smlad lr, r4, r4, lr
0198e3582544 ARMv6 optimised pix_norm1
mru
parents: 11115
diff changeset
587 uxtb16 r5, r5, ror #8
0198e3582544 ARMv6 optimised pix_norm1
mru
parents: 11115
diff changeset
588 smlad lr, r6, r6, lr
0198e3582544 ARMv6 optimised pix_norm1
mru
parents: 11115
diff changeset
589 subs r12, r12, #1
0198e3582544 ARMv6 optimised pix_norm1
mru
parents: 11115
diff changeset
590 add r0, r0, r1
0198e3582544 ARMv6 optimised pix_norm1
mru
parents: 11115
diff changeset
591 smlad lr, r5, r5, lr
0198e3582544 ARMv6 optimised pix_norm1
mru
parents: 11115
diff changeset
592 bgt 1b
0198e3582544 ARMv6 optimised pix_norm1
mru
parents: 11115
diff changeset
593
0198e3582544 ARMv6 optimised pix_norm1
mru
parents: 11115
diff changeset
594 mov r0, lr
0198e3582544 ARMv6 optimised pix_norm1
mru
parents: 11115
diff changeset
595 pop {r4-r6, pc}
0198e3582544 ARMv6 optimised pix_norm1
mru
parents: 11115
diff changeset
596 .endfunc
11117
ad6d17b36a3a ARMv6 optimised pix_sum
mru
parents: 11116
diff changeset
597
ad6d17b36a3a ARMv6 optimised pix_sum
mru
parents: 11116
diff changeset
598 function ff_pix_sum_armv6, export=1
ad6d17b36a3a ARMv6 optimised pix_sum
mru
parents: 11116
diff changeset
599 push {r4-r7, lr}
ad6d17b36a3a ARMv6 optimised pix_sum
mru
parents: 11116
diff changeset
600 mov r12, #16
ad6d17b36a3a ARMv6 optimised pix_sum
mru
parents: 11116
diff changeset
601 mov r2, #0
ad6d17b36a3a ARMv6 optimised pix_sum
mru
parents: 11116
diff changeset
602 mov r3, #0
ad6d17b36a3a ARMv6 optimised pix_sum
mru
parents: 11116
diff changeset
603 mov lr, #0
ad6d17b36a3a ARMv6 optimised pix_sum
mru
parents: 11116
diff changeset
604 ldr r4, [r0]
ad6d17b36a3a ARMv6 optimised pix_sum
mru
parents: 11116
diff changeset
605 1:
ad6d17b36a3a ARMv6 optimised pix_sum
mru
parents: 11116
diff changeset
606 subs r12, r12, #1
ad6d17b36a3a ARMv6 optimised pix_sum
mru
parents: 11116
diff changeset
607 ldr r5, [r0, #4]
ad6d17b36a3a ARMv6 optimised pix_sum
mru
parents: 11116
diff changeset
608 usada8 r2, r4, lr, r2
ad6d17b36a3a ARMv6 optimised pix_sum
mru
parents: 11116
diff changeset
609 ldr r6, [r0, #8]
ad6d17b36a3a ARMv6 optimised pix_sum
mru
parents: 11116
diff changeset
610 usada8 r3, r5, lr, r3
ad6d17b36a3a ARMv6 optimised pix_sum
mru
parents: 11116
diff changeset
611 ldr r7, [r0, #12]
ad6d17b36a3a ARMv6 optimised pix_sum
mru
parents: 11116
diff changeset
612 usada8 r2, r6, lr, r2
ad6d17b36a3a ARMv6 optimised pix_sum
mru
parents: 11116
diff changeset
613 beq 2f
ad6d17b36a3a ARMv6 optimised pix_sum
mru
parents: 11116
diff changeset
614 ldr r4, [r0, r1]!
ad6d17b36a3a ARMv6 optimised pix_sum
mru
parents: 11116
diff changeset
615 usada8 r3, r7, lr, r3
ad6d17b36a3a ARMv6 optimised pix_sum
mru
parents: 11116
diff changeset
616 bgt 1b
ad6d17b36a3a ARMv6 optimised pix_sum
mru
parents: 11116
diff changeset
617 2:
ad6d17b36a3a ARMv6 optimised pix_sum
mru
parents: 11116
diff changeset
618 usada8 r3, r7, lr, r3
ad6d17b36a3a ARMv6 optimised pix_sum
mru
parents: 11116
diff changeset
619 add r0, r2, r3
ad6d17b36a3a ARMv6 optimised pix_sum
mru
parents: 11116
diff changeset
620 pop {r4-r7, pc}
ad6d17b36a3a ARMv6 optimised pix_sum
mru
parents: 11116
diff changeset
621 .endfunc