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comparison x86/dsputil_mmx.c @ 11369:98970e51365a libavcodec

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Remove DECLARE_ALIGNED_{8,16} macros These macros are redundant. All uses are replaced with the generic DECLARE_ALIGNED macro instead.
author mru
date Sat, 06 Mar 2010 14:24:59 +0000
parents 001eb7e3e2d3
children f5ccf2e590d6
comparison
equal deleted inserted replaced
11368:3d4f64b8fb10 11369:98970e51365a
37 //#include <assert.h> 37 //#include <assert.h>
38 38
39 int mm_flags; /* multimedia extension flags */ 39 int mm_flags; /* multimedia extension flags */
40 40
41 /* pixel operations */ 41 /* pixel operations */
42 DECLARE_ALIGNED_8 (const uint64_t, ff_bone) = 0x0101010101010101ULL; 42 DECLARE_ALIGNED(8, const uint64_t, ff_bone) = 0x0101010101010101ULL;
43 DECLARE_ALIGNED_8 (const uint64_t, ff_wtwo) = 0x0002000200020002ULL; 43 DECLARE_ALIGNED(8, const uint64_t, ff_wtwo) = 0x0002000200020002ULL;
44 44
45 DECLARE_ALIGNED_16(const uint64_t, ff_pdw_80000000)[2] = 45 DECLARE_ALIGNED(16, const uint64_t, ff_pdw_80000000)[2] =
46 {0x8000000080000000ULL, 0x8000000080000000ULL}; 46 {0x8000000080000000ULL, 0x8000000080000000ULL};
47 47
48 DECLARE_ALIGNED_8 (const uint64_t, ff_pw_3 ) = 0x0003000300030003ULL; 48 DECLARE_ALIGNED(8, const uint64_t, ff_pw_3 ) = 0x0003000300030003ULL;
49 DECLARE_ALIGNED_8 (const uint64_t, ff_pw_4 ) = 0x0004000400040004ULL; 49 DECLARE_ALIGNED(8, const uint64_t, ff_pw_4 ) = 0x0004000400040004ULL;
50 DECLARE_ALIGNED_16(const xmm_reg, ff_pw_5 ) = {0x0005000500050005ULL, 0x0005000500050005ULL}; 50 DECLARE_ALIGNED(16, const xmm_reg, ff_pw_5 ) = {0x0005000500050005ULL, 0x0005000500050005ULL};
51 DECLARE_ALIGNED_16(const xmm_reg, ff_pw_8 ) = {0x0008000800080008ULL, 0x0008000800080008ULL}; 51 DECLARE_ALIGNED(16, const xmm_reg, ff_pw_8 ) = {0x0008000800080008ULL, 0x0008000800080008ULL};
52 DECLARE_ALIGNED_8 (const uint64_t, ff_pw_15 ) = 0x000F000F000F000FULL; 52 DECLARE_ALIGNED(8, const uint64_t, ff_pw_15 ) = 0x000F000F000F000FULL;
53 DECLARE_ALIGNED_16(const xmm_reg, ff_pw_16 ) = {0x0010001000100010ULL, 0x0010001000100010ULL}; 53 DECLARE_ALIGNED(16, const xmm_reg, ff_pw_16 ) = {0x0010001000100010ULL, 0x0010001000100010ULL};
54 DECLARE_ALIGNED_8 (const uint64_t, ff_pw_20 ) = 0x0014001400140014ULL; 54 DECLARE_ALIGNED(8, const uint64_t, ff_pw_20 ) = 0x0014001400140014ULL;
55 DECLARE_ALIGNED_16(const xmm_reg, ff_pw_28 ) = {0x001C001C001C001CULL, 0x001C001C001C001CULL}; 55 DECLARE_ALIGNED(16, const xmm_reg, ff_pw_28 ) = {0x001C001C001C001CULL, 0x001C001C001C001CULL};
56 DECLARE_ALIGNED_16(const xmm_reg, ff_pw_32 ) = {0x0020002000200020ULL, 0x0020002000200020ULL}; 56 DECLARE_ALIGNED(16, const xmm_reg, ff_pw_32 ) = {0x0020002000200020ULL, 0x0020002000200020ULL};
57 DECLARE_ALIGNED_8 (const uint64_t, ff_pw_42 ) = 0x002A002A002A002AULL; 57 DECLARE_ALIGNED(8, const uint64_t, ff_pw_42 ) = 0x002A002A002A002AULL;
58 DECLARE_ALIGNED_16(const xmm_reg, ff_pw_64 ) = {0x0040004000400040ULL, 0x0040004000400040ULL}; 58 DECLARE_ALIGNED(16, const xmm_reg, ff_pw_64 ) = {0x0040004000400040ULL, 0x0040004000400040ULL};
59 DECLARE_ALIGNED_8 (const uint64_t, ff_pw_96 ) = 0x0060006000600060ULL; 59 DECLARE_ALIGNED(8, const uint64_t, ff_pw_96 ) = 0x0060006000600060ULL;
60 DECLARE_ALIGNED_8 (const uint64_t, ff_pw_128) = 0x0080008000800080ULL; 60 DECLARE_ALIGNED(8, const uint64_t, ff_pw_128) = 0x0080008000800080ULL;
61 DECLARE_ALIGNED_8 (const uint64_t, ff_pw_255) = 0x00ff00ff00ff00ffULL; 61 DECLARE_ALIGNED(8, const uint64_t, ff_pw_255) = 0x00ff00ff00ff00ffULL;
62 62
63 DECLARE_ALIGNED_8 (const uint64_t, ff_pb_1 ) = 0x0101010101010101ULL; 63 DECLARE_ALIGNED(8, const uint64_t, ff_pb_1 ) = 0x0101010101010101ULL;
64 DECLARE_ALIGNED_8 (const uint64_t, ff_pb_3 ) = 0x0303030303030303ULL; 64 DECLARE_ALIGNED(8, const uint64_t, ff_pb_3 ) = 0x0303030303030303ULL;
65 DECLARE_ALIGNED_8 (const uint64_t, ff_pb_7 ) = 0x0707070707070707ULL; 65 DECLARE_ALIGNED(8, const uint64_t, ff_pb_7 ) = 0x0707070707070707ULL;
66 DECLARE_ALIGNED_8 (const uint64_t, ff_pb_1F ) = 0x1F1F1F1F1F1F1F1FULL; 66 DECLARE_ALIGNED(8, const uint64_t, ff_pb_1F ) = 0x1F1F1F1F1F1F1F1FULL;
67 DECLARE_ALIGNED_8 (const uint64_t, ff_pb_3F ) = 0x3F3F3F3F3F3F3F3FULL; 67 DECLARE_ALIGNED(8, const uint64_t, ff_pb_3F ) = 0x3F3F3F3F3F3F3F3FULL;
68 DECLARE_ALIGNED_8 (const uint64_t, ff_pb_81 ) = 0x8181818181818181ULL; 68 DECLARE_ALIGNED(8, const uint64_t, ff_pb_81 ) = 0x8181818181818181ULL;
69 DECLARE_ALIGNED_8 (const uint64_t, ff_pb_A1 ) = 0xA1A1A1A1A1A1A1A1ULL; 69 DECLARE_ALIGNED(8, const uint64_t, ff_pb_A1 ) = 0xA1A1A1A1A1A1A1A1ULL;
70 DECLARE_ALIGNED_8 (const uint64_t, ff_pb_FC ) = 0xFCFCFCFCFCFCFCFCULL; 70 DECLARE_ALIGNED(8, const uint64_t, ff_pb_FC ) = 0xFCFCFCFCFCFCFCFCULL;
71 71
72 DECLARE_ALIGNED_16(const double, ff_pd_1)[2] = { 1.0, 1.0 }; 72 DECLARE_ALIGNED(16, const double, ff_pd_1)[2] = { 1.0, 1.0 };
73 DECLARE_ALIGNED_16(const double, ff_pd_2)[2] = { 2.0, 2.0 }; 73 DECLARE_ALIGNED(16, const double, ff_pd_2)[2] = { 2.0, 2.0 };
74 74
75 #define JUMPALIGN() __asm__ volatile (ASMALIGN(3)::) 75 #define JUMPALIGN() __asm__ volatile (ASMALIGN(3)::)
76 #define MOVQ_ZERO(regd) __asm__ volatile ("pxor %%" #regd ", %%" #regd ::) 76 #define MOVQ_ZERO(regd) __asm__ volatile ("pxor %%" #regd ", %%" #regd ::)
77 77
78 #define MOVQ_BFE(regd) \ 78 #define MOVQ_BFE(regd) \
2024 if(in_ch == 5 && out_ch == 2 && !(matrix_cmp[0][1]|matrix_cmp[2][0]|matrix_cmp[3][1]|matrix_cmp[4][0]|(matrix_cmp[1][0]^matrix_cmp[1][1])|(matrix_cmp[0][0]^matrix_cmp[2][1]))) { 2024 if(in_ch == 5 && out_ch == 2 && !(matrix_cmp[0][1]|matrix_cmp[2][0]|matrix_cmp[3][1]|matrix_cmp[4][0]|(matrix_cmp[1][0]^matrix_cmp[1][1])|(matrix_cmp[0][0]^matrix_cmp[2][1]))) {
2025 MIX5(IF0,IF1); 2025 MIX5(IF0,IF1);
2026 } else if(in_ch == 5 && out_ch == 1 && matrix_cmp[0][0]==matrix_cmp[2][0] && matrix_cmp[3][0]==matrix_cmp[4][0]) { 2026 } else if(in_ch == 5 && out_ch == 1 && matrix_cmp[0][0]==matrix_cmp[2][0] && matrix_cmp[3][0]==matrix_cmp[4][0]) {
2027 MIX5(IF1,IF0); 2027 MIX5(IF1,IF0);
2028 } else { 2028 } else {
2029 DECLARE_ALIGNED_16(float, matrix_simd)[in_ch][2][4]; 2029 DECLARE_ALIGNED(16, float, matrix_simd)[in_ch][2][4];
2030 j = 2*in_ch*sizeof(float); 2030 j = 2*in_ch*sizeof(float);
2031 __asm__ volatile( 2031 __asm__ volatile(
2032 "1: \n" 2032 "1: \n"
2033 "sub $8, %0 \n" 2033 "sub $8, %0 \n"
2034 "movss (%2,%0), %%xmm6 \n" 2034 "movss (%2,%0), %%xmm6 \n"
2411 #define ff_float_to_int16_interleave6_sse2 ff_float_to_int16_interleave6_sse 2411 #define ff_float_to_int16_interleave6_sse2 ff_float_to_int16_interleave6_sse
2412 2412
2413 #define FLOAT_TO_INT16_INTERLEAVE(cpu, body) \ 2413 #define FLOAT_TO_INT16_INTERLEAVE(cpu, body) \
2414 /* gcc pessimizes register allocation if this is in the same function as float_to_int16_interleave_sse2*/\ 2414 /* gcc pessimizes register allocation if this is in the same function as float_to_int16_interleave_sse2*/\
2415 static av_noinline void float_to_int16_interleave_misc_##cpu(int16_t *dst, const float **src, long len, int channels){\ 2415 static av_noinline void float_to_int16_interleave_misc_##cpu(int16_t *dst, const float **src, long len, int channels){\
2416 DECLARE_ALIGNED_16(int16_t, tmp)[len];\ 2416 DECLARE_ALIGNED(16, int16_t, tmp)[len];\
2417 int i,j,c;\ 2417 int i,j,c;\
2418 for(c=0; c<channels; c++){\ 2418 for(c=0; c<channels; c++){\
2419 float_to_int16_##cpu(tmp, src[c], len);\ 2419 float_to_int16_##cpu(tmp, src[c], len);\
2420 for(i=0, j=c; i<len; i++, j+=channels)\ 2420 for(i=0, j=c; i<len; i++, j+=channels)\
2421 dst[j] = tmp[i];\ 2421 dst[j] = tmp[i];\