diff ppc/dsputil_ppc.c @ 1334:80c46c310a91 libavcodec

PPC970 patch + cpu-specific tuning support by (Romain Dolbeau <dolbeau at irisa dot fr>)

--- a/ppc/dsputil_ppc.c	Sun Jun 29 00:23:30 2003 +0000
+++ b/ppc/dsputil_ppc.c	Sun Jun 29 00:39:57 2003 +0000
@@ -57,7 +57,8 @@
   "put_no_rnd_pixels8_xy2_altivec",
   "put_pixels16_xy2_altivec",
   "put_no_rnd_pixels16_xy2_altivec",
-  "clear_blocks_dcbz32_ppc"
+  "clear_blocks_dcbz32_ppc",
+  "clear_blocks_dcbz128_ppc"
 };
 #ifdef POWERPC_PERF_USE_PMC
 unsigned long long perfdata_miss[powerpc_perf_total][powerpc_data_total];
@@ -110,6 +111,18 @@
   It simply clear to zero a single cache line,
   so you need to know the cache line size to use it !
   It's absurd, but it's fast...
+
+  update 24/06/2003 : Apple released yesterday the G5,
+  with a PPC970. cache line size : 128 bytes. Oups.
+  The semantic of dcbz was changed, it always clear
+  32 bytes. so the function below will work, but will
+  be slow. So I fixed check_dcbz_effect to use dcbzl,
+  which is defined to clear a cache line (as dcbz before).
+  So we still can distinguish, and use dcbz (32 bytes)
+  or dcbzl (one cache line) as required.
+
+  see <http://developer.apple.com/technotes/tn/tn2087.html>
+  and <http://developer.apple.com/technotes/tn/tn2086.html>
 */
 void clear_blocks_dcbz32_ppc(DCTELEM *blocks)
 {
@@ -126,7 +139,7 @@
       i += 16;
     }
     for ( ; i < sizeof(DCTELEM)*6*64 ; i += 32) {
-      asm volatile("dcbz %0,%1" : : "r" (blocks), "r" (i) : "memory");
+      asm volatile("dcbz %0,%1" : : "r" (i), "r" (blocks) : "memory");
     }
     if (misal) {
       ((unsigned long*)blocks)[188] = 0L;
@@ -141,8 +154,45 @@
 POWERPC_TBL_STOP_COUNT(powerpc_clear_blocks_dcbz32, 1);
 }
 
+/* same as above, when dcbzl clear a whole 128B cache line
+   i.e. the PPC970 aka G5 */
+#ifndef NO_DCBZL
+void clear_blocks_dcbz128_ppc(DCTELEM *blocks)
+{
+POWERPC_TBL_DECLARE(powerpc_clear_blocks_dcbz128, 1);
+    register int misal = ((unsigned long)blocks & 0x0000007f);
+    register int i = 0;
+POWERPC_TBL_START_COUNT(powerpc_clear_blocks_dcbz128, 1);
+#if 1
+ if (misal) {
+   // we could probably also optimize this case,
+   // but there's not much point as the machines
+   // aren't available yet (2003-06-26)
+      memset(blocks, 0, sizeof(DCTELEM)*6*64);
+    }
+    else
+      for ( ; i < sizeof(DCTELEM)*6*64 ; i += 128) {
+	asm volatile("dcbzl %0,%1" : : "r" (i), "r" (blocks) : "memory");
+      }
+#else
+    memset(blocks, 0, sizeof(DCTELEM)*6*64);
+#endif
+POWERPC_TBL_STOP_COUNT(powerpc_clear_blocks_dcbz128, 1);
+}
+#else
+void clear_blocks_dcbz128_ppc(DCTELEM *blocks)
+{
+  memset(blocks, 0, sizeof(DCTELEM)*6*64);
+}
+#endif
+
+#ifndef NO_DCBZL
 /* check dcbz report how many bytes are set to 0 by dcbz */
-long check_dcbz_effect(void)
+/* update 24/06/2003 : replace dcbz by dcbzl to get
+   the intended effect (Apple "fixed" dcbz)
+   unfortunately this cannot be used unless the assembler
+   knows about dcbzl ... */
+long check_dcbzl_effect(void)
 {
   register char *fakedata = (char*)av_malloc(1024);
   register char *fakedata_middle;
@@ -159,7 +209,7 @@
 
   memset(fakedata, 0xFF, 1024);
 
-  asm volatile("dcbz %0, %1" : : "r" (fakedata_middle), "r" (zero));
+  asm volatile("dcbzl %0, %1" : : "r" (fakedata_middle), "r" (zero));
 
   for (i = 0; i < 1024 ; i ++)
   {
@@ -171,15 +221,24 @@
   
   return count;
 }
+#else
+long check_dcbzl_effect(void)
+{
+  return 0;
+}
+#endif
 
 void dsputil_init_ppc(DSPContext* c, AVCodecContext *avctx)
 {
-    // Common optimisations whether Altivec or not
+    // Common optimizations whether Altivec is available or not
 
-  switch (check_dcbz_effect()) {
+  switch (check_dcbzl_effect()) {
   case 32:
     c->clear_blocks = clear_blocks_dcbz32_ppc;
     break;
+  case 128:
+    c->clear_blocks = clear_blocks_dcbz128_ppc;
+    break;
   default:
     break;
   }