# HG changeset patch
# User mru
# Date 1265732025 0
# Node ID 3fba8a5c62881314a5fcf01063071adf14036629
# Parent  852772c36cc63feaf4a5fcfbc7051b25d79252e7
ARMv6 optimised sse16

diff -r 852772c36cc6 -r 3fba8a5c6288 arm/dsputil_armv6.S
--- a/arm/dsputil_armv6.S	Tue Feb 09 16:13:41 2010 +0000
+++ b/arm/dsputil_armv6.S	Tue Feb 09 16:13:45 2010 +0000
@@ -513,3 +513,54 @@
         add             r0,  r0,  lr
         pop             {r4-r9, pc}
 .endfunc
+
+function ff_sse16_armv6, export=1
+        ldr             r12, [sp]
+        push            {r4-r9, lr}
+        mov             r0,  #0
+1:
+        ldrd            r4,  r5,  [r1]
+        ldr             r8,  [r2]
+        uxtb16          lr,  r4
+        uxtb16          r4,  r4,  ror #8
+        uxtb16          r9,  r8
+        uxtb16          r8,  r8,  ror #8
+        ldr             r7,  [r2, #4]
+        usub16          lr,  lr,  r9
+        usub16          r4,  r4,  r8
+        smlad           r0,  lr,  lr,  r0
+        uxtb16          r6,  r5
+        uxtb16          lr,  r5,  ror #8
+        uxtb16          r8,  r7
+        uxtb16          r9,  r7,  ror #8
+        smlad           r0,  r4,  r4,  r0
+        ldrd            r4,  r5,  [r1, #8]
+        usub16          r6,  r6,  r8
+        usub16          r8,  lr,  r9
+        ldr             r7,  [r2, #8]
+        smlad           r0,  r6,  r6,  r0
+        uxtb16          lr,  r4
+        uxtb16          r4,  r4,  ror #8
+        uxtb16          r9,  r7
+        uxtb16          r7,  r7, ror #8
+        smlad           r0,  r8,  r8,  r0
+        ldr             r8,  [r2, #12]
+        usub16          lr,  lr,  r9
+        usub16          r4,  r4,  r7
+        smlad           r0,  lr,  lr,  r0
+        uxtb16          r6,  r5
+        uxtb16          r5,  r5,  ror #8
+        uxtb16          r9,  r8
+        uxtb16          r8,  r8,  ror #8
+        smlad           r0,  r4,  r4,  r0
+        usub16          r6,  r6,  r9
+        usub16          r5,  r5,  r8
+        smlad           r0,  r6,  r6,  r0
+        add             r1,  r1,  r3
+        add             r2,  r2,  r3
+        subs            r12, r12, #1
+        smlad           r0,  r5,  r5,  r0
+        bgt             1b
+
+        pop             {r4-r9, pc}
+.endfunc
diff -r 852772c36cc6 -r 3fba8a5c6288 arm/dsputil_init_armv6.c
--- a/arm/dsputil_init_armv6.c	Tue Feb 09 16:13:41 2010 +0000
+++ b/arm/dsputil_init_armv6.c	Tue Feb 09 16:13:45 2010 +0000
@@ -64,6 +64,9 @@
 int ff_pix_abs8_armv6(void *s, uint8_t *blk1, uint8_t *blk2,
                        int line_size, int h);
 
+int ff_sse16_armv6(void *s, uint8_t *blk1, uint8_t *blk2,
+                   int line_size, int h);
+
 void av_cold ff_dsputil_init_armv6(DSPContext* c, AVCodecContext *avctx)
 {
     if (!avctx->lowres && (avctx->idct_algo == FF_IDCT_AUTO ||
@@ -107,4 +110,6 @@
 
     c->sad[0] = ff_pix_abs16_armv6;
     c->sad[1] = ff_pix_abs8_armv6;
+
+    c->sse[0] = ff_sse16_armv6;
 }