# HG changeset patch # User rbultje # Date 1279762526 0 # Node ID 657d353cd51578eee8ec776649a7bca31f6cbb45 # Parent c6509c20592214c892061a69ac75744eab041cf7 Fix and enable horizontal >=SSE2 mbedge loopfilter. diff -r c6509c205922 -r 657d353cd515 x86/vp8dsp-init.c --- a/x86/vp8dsp-init.c Thu Jul 22 00:39:49 2010 +0000 +++ b/x86/vp8dsp-init.c Thu Jul 22 01:35:26 2010 +0000 @@ -343,16 +343,16 @@ c->vp8_v_loop_filter16y_inner = ff_vp8_v_loop_filter16y_inner_sse2; c->vp8_v_loop_filter8uv_inner = ff_vp8_v_loop_filter8uv_inner_sse2; - c->vp8_v_loop_filter16y = ff_vp8_v_loop_filter16y_mbedge_mmxext; - c->vp8_v_loop_filter8uv = ff_vp8_v_loop_filter8uv_mbedge_mmxext; + c->vp8_v_loop_filter16y = ff_vp8_v_loop_filter16y_mbedge_sse2; + c->vp8_v_loop_filter8uv = ff_vp8_v_loop_filter8uv_mbedge_sse2; } if (mm_flags & FF_MM_SSE2) { c->vp8_h_loop_filter16y_inner = ff_vp8_h_loop_filter16y_inner_sse2; c->vp8_h_loop_filter8uv_inner = ff_vp8_h_loop_filter8uv_inner_sse2; - //c->vp8_h_loop_filter16y = ff_vp8_h_loop_filter16y_mbedge_sse2; - //c->vp8_h_loop_filter8uv = ff_vp8_h_loop_filter8uv_mbedge_sse2; + c->vp8_h_loop_filter16y = ff_vp8_h_loop_filter16y_mbedge_sse2; + c->vp8_h_loop_filter8uv = ff_vp8_h_loop_filter8uv_mbedge_sse2; } if (mm_flags & FF_MM_SSSE3) { @@ -372,9 +372,9 @@ c->vp8_h_loop_filter8uv_inner = ff_vp8_h_loop_filter8uv_inner_ssse3; c->vp8_v_loop_filter16y = ff_vp8_v_loop_filter16y_mbedge_ssse3; - //c->vp8_h_loop_filter16y = ff_vp8_h_loop_filter16y_mbedge_ssse3; + c->vp8_h_loop_filter16y = ff_vp8_h_loop_filter16y_mbedge_ssse3; c->vp8_v_loop_filter8uv = ff_vp8_v_loop_filter8uv_mbedge_ssse3; - //c->vp8_h_loop_filter8uv = ff_vp8_h_loop_filter8uv_mbedge_ssse3; + c->vp8_h_loop_filter8uv = ff_vp8_h_loop_filter8uv_mbedge_ssse3; } if (mm_flags & FF_MM_SSE4) { diff -r c6509c205922 -r 657d353cd515 x86/vp8dsp.asm --- a/x86/vp8dsp.asm Thu Jul 22 00:39:49 2010 +0000 +++ b/x86/vp8dsp.asm Thu Jul 22 01:35:26 2010 +0000 @@ -2513,8 +2513,8 @@ %else ; sse2 (h) lea dst8_reg, [dst8_reg+mstride_reg+1] WRITE_4x4D 1, 2, 3, 4, dst_reg, dst2_reg, dst8_reg, mstride_reg, stride_reg, %4 - add dst_reg, 4 - add dst8_reg, 4 + lea dst_reg, [dst2_reg+mstride_reg+4] + lea dst8_reg, [dst8_reg+mstride_reg+4] WRITE_8W m5, m5, dst2_reg, dst_reg, mstride_reg, stride_reg WRITE_8W m6, m6, dst2_reg, dst8_reg, mstride_reg, stride_reg %endif