Mercurial > mplayer.hg
annotate cpudetect.c @ 30425:00bb44a07dbf
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author | stefano |
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date | Sat, 30 Jan 2010 21:58:09 +0000 |
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1 #include "config.h" |
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2 #include "cpudetect.h" |
5937 | 3 #include "mp_msg.h" |
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4 |
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5 CpuCaps gCpuCaps; |
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6 |
3837 | 7 #include <stdlib.h> |
8 | |
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9 #if ARCH_X86 |
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10 |
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11 #include <stdio.h> |
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12 #include <string.h> |
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13 |
12143 | 14 #if defined (__NetBSD__) || defined(__OpenBSD__) |
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15 #include <sys/param.h> |
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16 #include <sys/sysctl.h> |
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17 #include <machine/cpu.h> |
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18 #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) || defined(__APPLE__) |
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19 #include <sys/types.h> |
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20 #include <sys/sysctl.h> |
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21 #elif defined(__linux__) |
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22 #include <signal.h> |
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23 #elif defined(__MINGW32__) || defined(__CYGWIN__) |
10440 | 24 #include <windows.h> |
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25 #elif defined(__OS2__) |
26061 | 26 #define INCL_DOS |
27 #include <os2.h> | |
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28 #elif defined(__AMIGAOS4__) |
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29 #include <proto/exec.h> |
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30 #endif |
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31 |
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32 /* Thanks to the FreeBSD project for some of this cpuid code, and |
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33 * help understanding how to use it. Thanks to the Mesa |
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34 * team for SSE support detection and more cpu detect code. |
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35 */ |
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36 |
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37 /* I believe this code works. However, it has only been used on a PII and PIII */ |
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38 |
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39 static void check_os_katmai_support( void ); |
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40 |
2272 | 41 // return TRUE if cpuid supported |
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42 static int has_cpuid(void) |
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43 { |
2272 | 44 // code from libavcodec: |
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45 #if ARCH_X86_64 |
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46 return 1; |
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47 #else |
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48 long a, c; |
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49 __asm__ volatile ( |
2272 | 50 /* See if CPUID instruction is supported ... */ |
51 /* ... Get copies of EFLAGS into eax and ecx */ | |
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52 "pushfl\n\t" |
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53 "pop %0\n\t" |
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54 "mov %0, %1\n\t" |
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55 |
2272 | 56 /* ... Toggle the ID bit in one copy and store */ |
57 /* to the EFLAGS reg */ | |
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58 "xor $0x200000, %0\n\t" |
2272 | 59 "push %0\n\t" |
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60 "popfl\n\t" |
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61 |
2272 | 62 /* ... Get the (hopefully modified) EFLAGS */ |
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63 "pushfl\n\t" |
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64 "pop %0\n\t" |
2272 | 65 : "=a" (a), "=c" (c) |
66 : | |
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67 : "cc" |
2272 | 68 ); |
69 | |
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70 return a != c; |
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71 #endif |
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72 } |
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73 |
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74 static void |
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75 do_cpuid(unsigned int ax, unsigned int *p) |
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76 { |
2272 | 77 #if 0 |
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78 __asm__ volatile( |
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79 "cpuid;" |
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80 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3]) |
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81 : "0" (ax) |
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82 ); |
2272 | 83 #else |
84 // code from libavcodec: | |
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85 __asm__ volatile |
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86 ("mov %%"REG_b", %%"REG_S"\n\t" |
2272 | 87 "cpuid\n\t" |
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88 "xchg %%"REG_b", %%"REG_S |
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89 : "=a" (p[0]), "=S" (p[1]), |
2272 | 90 "=c" (p[2]), "=d" (p[3]) |
91 : "0" (ax)); | |
92 #endif | |
93 | |
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94 } |
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95 |
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96 void GetCpuCaps( CpuCaps *caps) |
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97 { |
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98 unsigned int regs[4]; |
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99 unsigned int regs2[4]; |
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100 |
8860 | 101 memset(caps, 0, sizeof(*caps)); |
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102 caps->isX86=1; |
8860 | 103 caps->cl_size=32; /* default */ |
2288 | 104 if (!has_cpuid()) { |
6134 | 105 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"CPUID not supported!??? (maybe an old 486?)\n"); |
2288 | 106 return; |
107 } | |
108 do_cpuid(0x00000000, regs); // get _max_ cpuid level and vendor name | |
6134 | 109 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU vendor name: %.4s%.4s%.4s max cpuid level: %d\n", |
3837 | 110 (char*) (regs+1),(char*) (regs+3),(char*) (regs+2), regs[0]); |
2288 | 111 if (regs[0]>=0x00000001) |
2280 | 112 { |
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113 char *tmpstr, *ptmpstr; |
8860 | 114 unsigned cl_size; |
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115 |
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116 do_cpuid(0x00000001, regs2); |
2301 | 117 |
2288 | 118 caps->cpuType=(regs2[0] >> 8)&0xf; |
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119 caps->cpuModel=(regs2[0] >> 4)&0xf; |
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120 |
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121 // see AMD64 Architecture Programmer's Manual, Volume 3: General-purpose and |
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122 // System Instructions, Table 3-2: Effective family computation, page 120. |
2288 | 123 if(caps->cpuType==0xf){ |
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124 // use extended family (P4, IA64, K8) |
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125 caps->cpuType=0xf+((regs2[0]>>20)&255); |
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126 } |
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127 if(caps->cpuType==0xf || caps->cpuType==6) |
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128 caps->cpuModel |= ((regs2[0]>>16)&0xf) << 4; |
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129 |
3403 | 130 caps->cpuStepping=regs2[0] & 0xf; |
2288 | 131 |
132 // general feature flags: | |
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133 caps->hasTSC = (regs2[3] & (1 << 8 )) >> 8; // 0x0000010 |
2272 | 134 caps->hasMMX = (regs2[3] & (1 << 23 )) >> 23; // 0x0800000 |
135 caps->hasSSE = (regs2[3] & (1 << 25 )) >> 25; // 0x2000000 | |
136 caps->hasSSE2 = (regs2[3] & (1 << 26 )) >> 26; // 0x4000000 | |
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137 caps->hasSSE3 = (regs2[2] & 1); // 0x0000001 |
28015 | 138 caps->hasSSSE3 = (regs2[2] & (1 << 9 )) >> 9; // 0x0000200 |
2288 | 139 caps->hasMMX2 = caps->hasSSE; // SSE cpus supports mmxext too |
8860 | 140 cl_size = ((regs2[1] >> 8) & 0xFF)*8; |
141 if(cl_size) caps->cl_size = cl_size; | |
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142 |
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143 ptmpstr=tmpstr=GetCpuFriendlyName(regs, regs2); |
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144 while(*ptmpstr == ' ') // strip leading spaces |
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145 ptmpstr++; |
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146 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: %s ", ptmpstr); |
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147 free(tmpstr); |
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148 mp_msg(MSGT_CPUDETECT,MSGL_V,"(Family: %d, Model: %d, Stepping: %d)\n", |
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149 caps->cpuType, caps->cpuModel, caps->cpuStepping); |
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150 |
2288 | 151 } |
152 do_cpuid(0x80000000, regs); | |
153 if (regs[0]>=0x80000001) { | |
6134 | 154 mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cpuid-level: %d\n",regs[0]&0x7FFFFFFF); |
2288 | 155 do_cpuid(0x80000001, regs2); |
3840 | 156 caps->hasMMX |= (regs2[3] & (1 << 23 )) >> 23; // 0x0800000 |
157 caps->hasMMX2 |= (regs2[3] & (1 << 22 )) >> 22; // 0x400000 | |
2288 | 158 caps->has3DNow = (regs2[3] & (1 << 31 )) >> 31; //0x80000000 |
159 caps->has3DNowExt = (regs2[3] & (1 << 30 )) >> 30; | |
28015 | 160 caps->hasSSE4a = (regs2[2] & (1 << 6 )) >> 6; // 0x0000040 |
2288 | 161 } |
8860 | 162 if(regs[0]>=0x80000006) |
163 { | |
164 do_cpuid(0x80000006, regs2); | |
165 mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cache-info: %d\n",regs2[2]&0x7FFFFFFF); | |
166 caps->cl_size = regs2[2] & 0xFF; | |
167 } | |
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168 mp_msg(MSGT_CPUDETECT,MSGL_V,"Detected cache-line size is %u bytes\n",caps->cl_size); |
2288 | 169 #if 0 |
5937 | 170 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"cpudetect: MMX=%d MMX2=%d SSE=%d SSE2=%d 3DNow=%d 3DNowExt=%d\n", |
2288 | 171 gCpuCaps.hasMMX, |
172 gCpuCaps.hasMMX2, | |
173 gCpuCaps.hasSSE, | |
174 gCpuCaps.hasSSE2, | |
175 gCpuCaps.has3DNow, | |
176 gCpuCaps.has3DNowExt ); | |
177 #endif | |
178 | |
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179 /* FIXME: Does SSE2 need more OS support, too? */ |
26060 | 180 #if defined(__linux__) || defined(__FreeBSD__) || defined(__FreeBSD_kernel__) \ |
181 || defined(__NetBSD__) || defined(__OpenBSD__) || defined(__DragonFly__) \ | |
26061 | 182 || defined(__APPLE__) || defined(__CYGWIN__) || defined(__MINGW32__) \ |
183 || defined(__OS2__) | |
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184 if (caps->hasSSE) |
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185 check_os_katmai_support(); |
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186 if (!caps->hasSSE) |
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187 caps->hasSSE2 = 0; |
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188 #else |
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189 caps->hasSSE=0; |
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190 caps->hasSSE2 = 0; |
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191 #endif |
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192 // caps->has3DNow=1; |
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193 // caps->hasMMX2 = 0; |
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194 // caps->hasMMX = 0; |
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195 |
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196 #if !CONFIG_RUNTIME_CPUDETECT |
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197 #if !HAVE_MMX |
6134 | 198 if(caps->hasMMX) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX supported but disabled\n"); |
4829 | 199 caps->hasMMX=0; |
200 #endif | |
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201 #if !HAVE_MMX2 |
6134 | 202 if(caps->hasMMX2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX2 supported but disabled\n"); |
4829 | 203 caps->hasMMX2=0; |
204 #endif | |
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205 #if !HAVE_SSE |
6134 | 206 if(caps->hasSSE) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE supported but disabled\n"); |
4829 | 207 caps->hasSSE=0; |
208 #endif | |
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209 #if !HAVE_SSE2 |
6134 | 210 if(caps->hasSSE2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE2 supported but disabled\n"); |
4829 | 211 caps->hasSSE2=0; |
212 #endif | |
28335 | 213 #if !HAVE_AMD3DNOW |
6134 | 214 if(caps->has3DNow) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNow supported but disabled\n"); |
4829 | 215 caps->has3DNow=0; |
216 #endif | |
28335 | 217 #if !HAVE_AMD3DNOWEXT |
6134 | 218 if(caps->has3DNowExt) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNowExt supported but disabled\n"); |
4829 | 219 caps->has3DNowExt=0; |
220 #endif | |
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221 #endif // CONFIG_RUNTIME_CPUDETECT |
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222 } |
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223 |
2301 | 224 char *GetCpuFriendlyName(unsigned int regs[], unsigned int regs2[]){ |
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225 char vendor[13]; |
2303 | 226 char *retname; |
13628 | 227 int i; |
2301 | 228 |
18869 | 229 if (NULL==(retname=malloc(256))) { |
5937 | 230 mp_msg(MSGT_CPUDETECT,MSGL_FATAL,"Error: GetCpuFriendlyName() not enough memory\n"); |
2303 | 231 exit(1); |
232 } | |
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233 retname[0] = '\0'; |
2303 | 234 |
3837 | 235 sprintf(vendor,"%.4s%.4s%.4s",(char*)(regs+1),(char*)(regs+3),(char*)(regs+2)); |
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236 |
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237 do_cpuid(0x80000000,regs); |
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238 if (regs[0] >= 0x80000004) |
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239 { |
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240 // CPU has built-in namestring |
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241 for (i = 0x80000002; i <= 0x80000004; i++) |
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242 { |
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243 do_cpuid(i, regs); |
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244 strncat(retname, (char*)regs, 16); |
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245 } |
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246 } |
2301 | 247 return retname; |
248 } | |
249 | |
28295 | 250 #if defined(__linux__) && defined(_POSIX_SOURCE) && !ARCH_X86_64 |
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251 static void sigill_handler_sse( int signal, struct sigcontext sc ) |
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252 { |
6134 | 253 mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " ); |
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254 |
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255 /* Both the "xorps %%xmm0,%%xmm0" and "divps %xmm0,%%xmm1" |
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256 * instructions are 3 bytes long. We must increment the instruction |
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257 * pointer manually to avoid repeated execution of the offending |
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258 * instruction. |
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259 * |
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260 * If the SIGILL is caused by a divide-by-zero when unmasked |
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261 * exceptions aren't supported, the SIMD FPU status and control |
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262 * word will be restored at the end of the test, so we don't need |
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263 * to worry about doing it here. Besides, we may not be able to... |
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264 */ |
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265 sc.eip += 3; |
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266 |
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267 gCpuCaps.hasSSE=0; |
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268 } |
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269 #endif /* __linux__ && _POSIX_SOURCE */ |
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270 |
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271 #if (defined(__MINGW32__) || defined(__CYGWIN__)) && !ARCH_X86_64 |
10440 | 272 LONG CALLBACK win32_sig_handler_sse(EXCEPTION_POINTERS* ep) |
273 { | |
274 if(ep->ExceptionRecord->ExceptionCode==EXCEPTION_ILLEGAL_INSTRUCTION){ | |
275 mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " ); | |
276 ep->ContextRecord->Eip +=3; | |
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277 gCpuCaps.hasSSE=0; |
10440 | 278 return EXCEPTION_CONTINUE_EXECUTION; |
279 } | |
280 return EXCEPTION_CONTINUE_SEARCH; | |
281 } | |
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282 #endif /* defined(__MINGW32__) || defined(__CYGWIN__) */ |
10440 | 283 |
26061 | 284 #ifdef __OS2__ |
285 ULONG _System os2_sig_handler_sse( PEXCEPTIONREPORTRECORD p1, | |
286 PEXCEPTIONREGISTRATIONRECORD p2, | |
287 PCONTEXTRECORD p3, | |
288 PVOID p4 ) | |
289 { | |
290 if(p1->ExceptionNum == XCPT_ILLEGAL_INSTRUCTION){ | |
291 mp_msg(MSGT_CPUDETECT, MSGL_V, "SIGILL, "); | |
292 | |
293 p3->ctx_RegEip += 3; | |
294 gCpuCaps.hasSSE = 0; | |
295 | |
296 return XCPT_CONTINUE_EXECUTION; | |
297 } | |
298 return XCPT_CONTINUE_SEARCH; | |
299 } | |
300 #endif | |
301 | |
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302 /* If we're running on a processor that can do SSE, let's see if we |
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303 * are allowed to or not. This will catch 2.4.0 or later kernels that |
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304 * haven't been configured for a Pentium III but are running on one, |
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305 * and RedHat patched 2.2 kernels that have broken exception handling |
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306 * support for user space apps that do SSE. |
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307 */ |
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308 |
21848 | 309 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) |
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310 #define SSE_SYSCTL_NAME "hw.instruction_sse" |
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311 #elif defined(__APPLE__) |
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312 #define SSE_SYSCTL_NAME "hw.optional.sse" |
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313 #endif |
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314 |
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315 static void check_os_katmai_support( void ) |
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316 { |
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317 #if ARCH_X86_64 |
14455 | 318 gCpuCaps.hasSSE=1; |
319 gCpuCaps.hasSSE2=1; | |
21848 | 320 #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) || defined(__APPLE__) |
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321 int has_sse=0, ret; |
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322 size_t len=sizeof(has_sse); |
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323 |
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324 ret = sysctlbyname(SSE_SYSCTL_NAME, &has_sse, &len, NULL, 0); |
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325 if (ret || !has_sse) |
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326 gCpuCaps.hasSSE=0; |
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327 |
12143 | 328 #elif defined(__NetBSD__) || defined (__OpenBSD__) |
329 #if __NetBSD_Version__ >= 105250000 || (defined __OpenBSD__) | |
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330 int has_sse, has_sse2, ret, mib[2]; |
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331 size_t varlen; |
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332 |
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333 mib[0] = CTL_MACHDEP; |
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334 mib[1] = CPU_SSE; |
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335 varlen = sizeof(has_sse); |
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336 |
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337 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " ); |
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338 ret = sysctl(mib, 2, &has_sse, &varlen, NULL, 0); |
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339 gCpuCaps.hasSSE = ret >= 0 && has_sse; |
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340 mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" ); |
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341 |
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Ok, here is a better patch, which even adds a fix to compile it on older
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342 mib[1] = CPU_SSE2; |
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343 varlen = sizeof(has_sse2); |
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344 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE2... " ); |
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345 ret = sysctl(mib, 2, &has_sse2, &varlen, NULL, 0); |
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346 gCpuCaps.hasSSE2 = ret >= 0 && has_sse2; |
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347 mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE2 ? "yes.\n" : "no!\n" ); |
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348 #else |
8533
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349 gCpuCaps.hasSSE = 0; |
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350 mp_msg(MSGT_CPUDETECT,MSGL_WARN, "No OS support for SSE, disabling to be safe.\n" ); |
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351 #endif |
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352 #elif defined(__MINGW32__) || defined(__CYGWIN__) |
10440 | 353 LPTOP_LEVEL_EXCEPTION_FILTER exc_fil; |
354 if ( gCpuCaps.hasSSE ) { | |
355 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " ); | |
356 exc_fil = SetUnhandledExceptionFilter(win32_sig_handler_sse); | |
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357 __asm__ volatile ("xorps %xmm0, %xmm0"); |
10440 | 358 SetUnhandledExceptionFilter(exc_fil); |
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359 mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" ); |
10440 | 360 } |
26061 | 361 #elif defined(__OS2__) |
362 EXCEPTIONREGISTRATIONRECORD RegRec = { 0, &os2_sig_handler_sse }; | |
363 if ( gCpuCaps.hasSSE ) { | |
364 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " ); | |
365 DosSetExceptionHandler( &RegRec ); | |
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366 __asm__ volatile ("xorps %xmm0, %xmm0"); |
26061 | 367 DosUnsetExceptionHandler( &RegRec ); |
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368 mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" ); |
26061 | 369 } |
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370 #elif defined(__linux__) |
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371 #if defined(_POSIX_SOURCE) |
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372 struct sigaction saved_sigill; |
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373 |
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374 /* Save the original signal handlers. |
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375 */ |
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376 sigaction( SIGILL, NULL, &saved_sigill ); |
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377 |
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378 signal( SIGILL, (void (*)(int))sigill_handler_sse ); |
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379 |
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380 /* Emulate test for OSFXSR in CR4. The OS will set this bit if it |
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381 * supports the extended FPU save and restore required for SSE. If |
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382 * we execute an SSE instruction on a PIII and get a SIGILL, the OS |
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383 * doesn't support Streaming SIMD Exceptions, even if the processor |
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384 * does. |
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385 */ |
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386 if ( gCpuCaps.hasSSE ) { |
6134 | 387 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " ); |
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388 |
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389 // __asm__ volatile ("xorps %%xmm0, %%xmm0"); |
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390 __asm__ volatile ("xorps %xmm0, %xmm0"); |
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391 |
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392 mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" ); |
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393 } |
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394 |
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395 /* Restore the original signal handlers. |
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396 */ |
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397 sigaction( SIGILL, &saved_sigill, NULL ); |
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398 |
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399 /* If we've gotten to here and the XMM CPUID bit is still set, we're |
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400 * safe to go ahead and hook out the SSE code throughout Mesa. |
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401 */ |
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402 mp_msg(MSGT_CPUDETECT,MSGL_V, "Tests of OS support for SSE %s\n", gCpuCaps.hasSSE ? "passed." : "failed!" ); |
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403 #else |
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404 /* We can't use POSIX signal handling to test the availability of |
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405 * SSE, so we disable it by default. |
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406 */ |
5937 | 407 mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, disabling to be safe.\n" ); |
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408 gCpuCaps.hasSSE=0; |
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409 #endif /* _POSIX_SOURCE */ |
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410 #else |
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411 /* Do nothing on other platforms for now. |
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412 */ |
6134 | 413 mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, leaving disabled.\n" ); |
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414 gCpuCaps.hasSSE=0; |
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415 #endif /* __linux__ */ |
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416 } |
20577 | 417 #else /* ARCH_X86 */ |
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418 |
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419 #ifdef __APPLE__ |
9003 | 420 #include <sys/sysctl.h> |
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421 #elif defined(__AMIGAOS4__) |
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422 /* nothing */ |
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423 #else |
9003 | 424 #include <signal.h> |
425 #include <setjmp.h> | |
426 | |
427 static sigjmp_buf jmpbuf; | |
428 static volatile sig_atomic_t canjump = 0; | |
429 | |
430 static void sigill_handler (int sig) | |
431 { | |
432 if (!canjump) { | |
433 signal (sig, SIG_DFL); | |
434 raise (sig); | |
435 } | |
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436 |
9003 | 437 canjump = 0; |
438 siglongjmp (jmpbuf, 1); | |
439 } | |
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440 #endif /* __APPLE__ */ |
9003 | 441 |
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442 void GetCpuCaps( CpuCaps *caps) |
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443 { |
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444 caps->cpuType=0; |
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739849dfb699
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445 caps->cpuModel=0; |
3403 | 446 caps->cpuStepping=0; |
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447 caps->hasMMX=0; |
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448 caps->hasMMX2=0; |
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449 caps->has3DNow=0; |
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450 caps->has3DNowExt=0; |
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451 caps->hasSSE=0; |
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452 caps->hasSSE2=0; |
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453 caps->hasSSE3=0; |
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454 caps->hasSSSE3=0; |
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455 caps->hasSSE4a=0; |
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456 caps->isX86=0; |
9003 | 457 caps->hasAltiVec = 0; |
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458 #if HAVE_ALTIVEC |
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459 #ifdef __APPLE__ |
9003 | 460 /* |
461 rip-off from ffmpeg altivec detection code. | |
462 this code also appears on Apple's AltiVec pages. | |
463 */ | |
464 { | |
465 int sels[2] = {CTL_HW, HW_VECTORUNIT}; | |
466 int has_vu = 0; | |
467 size_t len = sizeof(has_vu); | |
468 int err; | |
469 | |
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470 err = sysctl(sels, 2, &has_vu, &len, NULL, 0); |
9003 | 471 |
472 if (err == 0) | |
473 if (has_vu != 0) | |
474 caps->hasAltiVec = 1; | |
475 } | |
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476 #elif defined(__AMIGAOS4__) |
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477 ULONG result = 0; |
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478 |
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479 GetCPUInfoTags(GCIT_VectorUnit, &result, TAG_DONE); |
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480 if (result == VECTORTYPE_ALTIVEC) |
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481 caps->hasAltiVec = 1; |
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482 #else |
9003 | 483 /* no Darwin, do it the brute-force way */ |
484 /* this is borrowed from the libmpeg2 library */ | |
485 { | |
486 signal (SIGILL, sigill_handler); | |
487 if (sigsetjmp (jmpbuf, 1)) { | |
488 signal (SIGILL, SIG_DFL); | |
489 } else { | |
490 canjump = 1; | |
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491 |
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492 __asm__ volatile ("mtspr 256, %0\n\t" |
9122 | 493 "vand %%v0, %%v0, %%v0" |
9003 | 494 : |
495 : "r" (-1)); | |
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496 |
9003 | 497 signal (SIGILL, SIG_DFL); |
498 caps->hasAltiVec = 1; | |
499 } | |
500 } | |
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501 #endif /* __APPLE__ */ |
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502 mp_msg(MSGT_CPUDETECT,MSGL_V,"AltiVec %sfound\n", (caps->hasAltiVec ? "" : "not ")); |
9003 | 503 #endif /* HAVE_ALTIVEC */ |
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504 |
28342
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505 if (ARCH_IA64) |
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506 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Intel Itanium\n"); |
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507 |
28342
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508 if (ARCH_SPARC) |
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509 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Sun Sparc\n"); |
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510 |
28342
457eb94aaf59
Replace another bunch of '#if HAVE_FOO' preprocessor checks by 'if (HAVE_FOO)'.
diego
parents:
28335
diff
changeset
|
511 if (ARCH_ARM) |
28458
6629e391d52d
Print information about detected CPU in verbose mode only.
diego
parents:
28364
diff
changeset
|
512 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: ARM\n"); |
11962
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
513 |
28342
457eb94aaf59
Replace another bunch of '#if HAVE_FOO' preprocessor checks by 'if (HAVE_FOO)'.
diego
parents:
28335
diff
changeset
|
514 if (ARCH_PPC) |
28458
6629e391d52d
Print information about detected CPU in verbose mode only.
diego
parents:
28364
diff
changeset
|
515 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: PowerPC\n"); |
11962
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
516 |
28342
457eb94aaf59
Replace another bunch of '#if HAVE_FOO' preprocessor checks by 'if (HAVE_FOO)'.
diego
parents:
28335
diff
changeset
|
517 if (ARCH_ALPHA) |
28458
6629e391d52d
Print information about detected CPU in verbose mode only.
diego
parents:
28364
diff
changeset
|
518 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Digital Alpha\n"); |
11962
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
519 |
28342
457eb94aaf59
Replace another bunch of '#if HAVE_FOO' preprocessor checks by 'if (HAVE_FOO)'.
diego
parents:
28335
diff
changeset
|
520 if (ARCH_SGI_MIPS) |
28458
6629e391d52d
Print information about detected CPU in verbose mode only.
diego
parents:
28364
diff
changeset
|
521 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: SGI MIPS\n"); |
11962
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
522 |
28342
457eb94aaf59
Replace another bunch of '#if HAVE_FOO' preprocessor checks by 'if (HAVE_FOO)'.
diego
parents:
28335
diff
changeset
|
523 if (ARCH_PA_RISC) |
28458
6629e391d52d
Print information about detected CPU in verbose mode only.
diego
parents:
28364
diff
changeset
|
524 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Hewlett-Packard PA-RISC\n"); |
11962
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
525 |
28342
457eb94aaf59
Replace another bunch of '#if HAVE_FOO' preprocessor checks by 'if (HAVE_FOO)'.
diego
parents:
28335
diff
changeset
|
526 if (ARCH_S390) |
28458
6629e391d52d
Print information about detected CPU in verbose mode only.
diego
parents:
28364
diff
changeset
|
527 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: IBM S/390\n"); |
11962
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
528 |
28342
457eb94aaf59
Replace another bunch of '#if HAVE_FOO' preprocessor checks by 'if (HAVE_FOO)'.
diego
parents:
28335
diff
changeset
|
529 if (ARCH_S390X) |
28458
6629e391d52d
Print information about detected CPU in verbose mode only.
diego
parents:
28364
diff
changeset
|
530 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: IBM S/390X\n"); |
11962
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
531 |
28342
457eb94aaf59
Replace another bunch of '#if HAVE_FOO' preprocessor checks by 'if (HAVE_FOO)'.
diego
parents:
28335
diff
changeset
|
532 if (ARCH_VAX) |
28458
6629e391d52d
Print information about detected CPU in verbose mode only.
diego
parents:
28364
diff
changeset
|
533 mp_msg(MSGT_CPUDETECT,MSGL_V, "CPU: Digital VAX\n" ); |
25340 | 534 |
28342
457eb94aaf59
Replace another bunch of '#if HAVE_FOO' preprocessor checks by 'if (HAVE_FOO)'.
diego
parents:
28335
diff
changeset
|
535 if (ARCH_XTENSA) |
28458
6629e391d52d
Print information about detected CPU in verbose mode only.
diego
parents:
28364
diff
changeset
|
536 mp_msg(MSGT_CPUDETECT,MSGL_V, "CPU: Tensilica Xtensa\n" ); |
3146
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents:
2417
diff
changeset
|
537 } |
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents:
2417
diff
changeset
|
538 #endif /* !ARCH_X86 */ |