Mercurial > mplayer.hg
annotate vidix/drivers/radeon.h @ 6173:020bfd8ac9ef
- put back SystemTooSlow message
- more tips for tooslow (ni vs cache) and buffer overflow (-ni)
author | arpi |
---|---|
date | Thu, 23 May 2002 21:58:29 +0000 |
parents | 43dc579db3d1 |
children | 034b12194350 |
rev | line source |
---|---|
3996 | 1 /* |
2 * radeon.h | |
3 * This software has been released under the terms of the GNU Public | |
4 * license. See http://www.gnu.org/copyleft/gpl.html for details. | |
5 * | |
6 * This collection of definition was written by Nick Kurshev | |
7 * It's based on radeonfb, X11, GATOS sources | |
8 * and partly compatible with Rage128 set (in OV0, CAP0, CAP1 parts) | |
9 */ | |
10 | |
11 #ifndef _RADEON_H | |
12 #define _RADEON_H | |
13 | |
14 #define RADEON_REGSIZE 0x4000 | |
15 #define MM_INDEX 0x0000 | |
16 /* MM_INDEX bit constants */ | |
17 # define MM_APER 0x80000000 | |
18 #define MM_DATA 0x0004 | |
19 #define BUS_CNTL 0x0030 | |
20 /* BUS_CNTL bit constants */ | |
21 # define BUS_DBL_RESYNC 0x00000001 | |
22 # define BUS_MSTR_RESET 0x00000002 | |
23 # define BUS_FLUSH_BUF 0x00000004 | |
24 # define BUS_STOP_REQ_DIS 0x00000008 | |
25 # define BUS_ROTATION_DIS 0x00000010 | |
26 # define BUS_MASTER_DIS 0x00000040 | |
27 # define BUS_ROM_WRT_EN 0x00000080 | |
28 # define BUS_DIS_ROM 0x00001000 | |
29 # define BUS_PCI_READ_RETRY_EN 0x00002000 | |
30 # define BUS_AGP_AD_STEPPING_EN 0x00004000 | |
31 # define BUS_PCI_WRT_RETRY_EN 0x00008000 | |
32 # define BUS_MSTR_RD_MULT 0x00100000 | |
33 # define BUS_MSTR_RD_LINE 0x00200000 | |
34 # define BUS_SUSPEND 0x00400000 | |
35 # define LAT_16X 0x00800000 | |
36 # define BUS_RD_DISCARD_EN 0x01000000 | |
37 # define BUS_RD_ABORT_EN 0x02000000 | |
38 # define BUS_MSTR_WS 0x04000000 | |
39 # define BUS_PARKING_DIS 0x08000000 | |
40 # define BUS_MSTR_DISCONNECT_EN 0x10000000 | |
41 # define BUS_WRT_BURST 0x20000000 | |
42 # define BUS_READ_BURST 0x40000000 | |
43 # define BUS_RDY_READ_DLY 0x80000000 | |
44 #define HI_STAT 0x004C | |
45 #define BUS_CNTL1 0x0034 | |
46 # define BUS_WAIT_ON_LOCK_EN (1 << 4) | |
47 #define I2C_CNTL_0 0x0090 | |
48 # define I2C_DONE (1<<0) | |
49 # define I2C_NACK (1<<1) | |
50 # define I2C_HALT (1<<2) | |
51 # define I2C_SOFT_RST (1<<5) | |
52 # define I2C_DRIVE_EN (1<<6) | |
53 # define I2C_DRIVE_SEL (1<<7) | |
54 # define I2C_START (1<<8) | |
55 # define I2C_STOP (1<<9) | |
56 # define I2C_RECEIVE (1<<10) | |
57 # define I2C_ABORT (1<<11) | |
58 # define I2C_GO (1<<12) | |
59 # define I2C_SEL (1<<16) | |
60 # define I2C_EN (1<<17) | |
61 #define I2C_CNTL_1 0x0094 | |
62 #define I2C_DATA 0x0098 | |
63 #define CONFIG_CNTL 0x00E0 | |
64 /* CONFIG_CNTL bit constants */ | |
65 # define CFG_VGA_RAM_EN 0x00000100 | |
66 #define CONFIG_MEMSIZE 0x00F8 | |
67 #define CONFIG_APER_0_BASE 0x0100 | |
68 #define CONFIG_APER_1_BASE 0x0104 | |
69 #define CONFIG_APER_SIZE 0x0108 | |
70 #define CONFIG_REG_1_BASE 0x010C | |
71 #define CONFIG_REG_APER_SIZE 0x0110 | |
72 #define PAD_AGPINPUT_DELAY 0x0164 | |
73 #define PAD_CTLR_STRENGTH 0x0168 | |
74 #define PAD_CTLR_UPDATE 0x016C | |
75 #define AGP_CNTL 0x0174 | |
76 # define AGP_APER_SIZE_256MB (0x00 << 0) | |
77 # define AGP_APER_SIZE_128MB (0x20 << 0) | |
78 # define AGP_APER_SIZE_64MB (0x30 << 0) | |
79 # define AGP_APER_SIZE_32MB (0x38 << 0) | |
80 # define AGP_APER_SIZE_16MB (0x3c << 0) | |
81 # define AGP_APER_SIZE_8MB (0x3e << 0) | |
82 # define AGP_APER_SIZE_4MB (0x3f << 0) | |
83 # define AGP_APER_SIZE_MASK (0x3f << 0) | |
84 #define AMCGPIO_A_REG 0x01a0 | |
85 #define AMCGPIO_EN_REG 0x01a8 | |
86 #define AMCGPIO_MASK 0x0194 | |
87 #define AMCGPIO_Y_REG 0x01a4 | |
88 #define BM_STATUS 0x0160 | |
89 #define MPP_TB_CONFIG 0x01c0 /* ? */ | |
90 #define MPP_GP_CONFIG 0x01c8 /* ? */ | |
91 #define VENDOR_ID 0x0F00 | |
92 #define DEVICE_ID 0x0F02 | |
93 #define COMMAND 0x0F04 | |
94 #define STATUS 0x0F06 | |
95 #define REVISION_ID 0x0F08 | |
96 #define REGPROG_INF 0x0F09 | |
97 #define SUB_CLASS 0x0F0A | |
98 #define CACHE_LINE 0x0F0C | |
99 #define LATENCY 0x0F0D | |
100 #define HEADER 0x0F0E | |
101 #define BIST 0x0F0F | |
102 #define REG_MEM_BASE 0x0F10 | |
103 #define REG_IO_BASE 0x0F14 | |
104 #define REG_REG_BASE 0x0F18 | |
105 #define ADAPTER_ID 0x0F2C | |
106 #define BIOS_ROM 0x0F30 | |
107 #define CAPABILITIES_PTR 0x0F34 | |
108 #define INTERRUPT_LINE 0x0F3C | |
109 #define INTERRUPT_PIN 0x0F3D | |
110 #define MIN_GRANT 0x0F3E | |
111 #define MAX_LATENCY 0x0F3F | |
112 #define ADAPTER_ID_W 0x0F4C | |
113 #define PMI_CAP_ID 0x0F50 | |
114 #define PMI_NXT_CAP_PTR 0x0F51 | |
115 #define PMI_PMC_REG 0x0F52 | |
116 #define PM_STATUS 0x0F54 | |
117 #define PMI_DATA 0x0F57 | |
118 #define AGP_CAP_ID 0x0F58 | |
119 #define AGP_STATUS 0x0F5C | |
120 # define AGP_1X_MODE 0x01 | |
121 # define AGP_2X_MODE 0x02 | |
122 # define AGP_4X_MODE 0x04 | |
123 # define AGP_MODE_MASK 0x07 | |
124 #define AGP_COMMAND 0x0F60 | |
125 | |
126 /* Video muxer unit */ | |
127 #define VIDEOMUX_CNTL 0x0190 | |
128 #define VIPPAD_MASK 0x0198 | |
129 #define VIPPAD1_A 0x01AC | |
130 #define VIPPAD1_EN 0x01B0 | |
131 #define VIPPAD1_Y 0x01B4 | |
132 | |
133 #define AIC_CTRL 0x01D0 | |
134 #define AIC_STAT 0x01D4 | |
135 #define AIC_PT_BASE 0x01D8 | |
136 #define AIC_LO_ADDR 0x01DC | |
137 #define AIC_HI_ADDR 0x01E0 | |
138 #define AIC_TLB_ADDR 0x01E4 | |
139 #define AIC_TLB_DATA 0x01E8 | |
140 #define DAC_CNTL 0x0058 | |
141 /* DAC_CNTL bit constants */ | |
142 # define DAC_8BIT_EN 0x00000100 | |
143 # define DAC_4BPP_PIX_ORDER 0x00000200 | |
144 # define DAC_CRC_EN 0x00080000 | |
145 # define DAC_MASK_ALL (0xff << 24) | |
146 # define DAC_VGA_ADR_EN (1 << 13) | |
147 # define DAC_RANGE_CNTL (3 << 0) | |
148 # define DAC_BLANKING (1 << 2) | |
149 #define DAC_CNTL2 0x007c | |
150 /* DAC_CNTL2 bit constants */ | |
151 # define DAC2_DAC_CLK_SEL (1 << 0) | |
152 # define DAC2_DAC2_CLK_SEL (1 << 1) | |
153 # define DAC2_PALETTE_ACC_CTL (1 << 5) | |
154 #define TV_DAC_CNTL 0x088c | |
155 /* TV_DAC_CNTL bit constants */ | |
156 # define TV_DAC_STD_MASK 0x0300 | |
157 # define TV_DAC_RDACPD (1 << 24) | |
158 # define TV_DAC_GDACPD (1 << 25) | |
159 # define TV_DAC_BDACPD (1 << 26) | |
160 #define CRTC_GEN_CNTL 0x0050 | |
161 /* CRTC_GEN_CNTL bit constants */ | |
162 # define CRTC_DBL_SCAN_EN 0x00000001 | |
163 # define CRTC_INTERLACE_EN (1 << 1) | |
164 # define CRTC_CSYNC_EN (1 << 4) | |
165 # define CRTC_CUR_EN 0x00010000 | |
166 # define CRTC_CUR_MODE_MASK (7 << 17) | |
167 # define CRTC_ICON_EN (1 << 20) | |
168 # define CRTC_EXT_DISP_EN (1 << 24) | |
169 # define CRTC_EN (1 << 25) | |
170 # define CRTC_DISP_REQ_EN_B (1 << 26) | |
171 #define CRTC2_GEN_CNTL 0x03f8 | |
172 /* CRTC2_GEN_CNTL bit constants */ | |
173 # define CRTC2_DBL_SCAN_EN (1 << 0) | |
174 # define CRTC2_INTERLACE_EN (1 << 1) | |
175 # define CRTC2_SYNC_TRISTAT (1 << 4) | |
176 # define CRTC2_HSYNC_TRISTAT (1 << 5) | |
177 # define CRTC2_VSYNC_TRISTAT (1 << 6) | |
178 # define CRTC2_CRT2_ON (1 << 7) | |
179 # define CRTC2_ICON_EN (1 << 15) | |
180 # define CRTC2_CUR_EN (1 << 16) | |
181 # define CRTC2_CUR_MODE_MASK (7 << 20) | |
182 # define CRTC2_DISP_DIS (1 << 23) | |
183 # define CRTC2_EN (1 << 25) | |
184 # define CRTC2_DISP_REQ_EN_B (1 << 26) | |
185 # define CRTC2_HSYNC_DIS (1 << 28) | |
186 # define CRTC2_VSYNC_DIS (1 << 29) | |
187 #define MEM_CNTL 0x0140 | |
188 /* MEM_CNTL bit constants */ | |
189 # define MEM_CTLR_STATUS_IDLE 0x00000000 | |
190 # define MEM_CTLR_STATUS_BUSY 0x00100000 | |
191 # define MEM_SEQNCR_STATUS_IDLE 0x00000000 | |
192 # define MEM_SEQNCR_STATUS_BUSY 0x00200000 | |
193 # define MEM_ARBITER_STATUS_IDLE 0x00000000 | |
194 # define MEM_ARBITER_STATUS_BUSY 0x00400000 | |
195 # define MEM_REQ_UNLOCK 0x00000000 | |
196 # define MEM_REQ_LOCK 0x00800000 | |
197 #define EXT_MEM_CNTL 0x0144 | |
198 #define MC_AGP_LOCATION 0x014C | |
199 #define MEM_IO_CNTL_A0 0x0178 | |
200 #define MEM_INIT_LATENCY_TIMER 0x0154 | |
201 #define MEM_SDRAM_MODE_REG 0x0158 | |
202 #define AGP_BASE 0x0170 | |
203 #define MEM_IO_CNTL_A1 0x017C | |
204 #define MEM_IO_CNTL_B0 0x0180 | |
205 #define MEM_IO_CNTL_B1 0x0184 | |
206 #define MC_DEBUG 0x0188 | |
207 #define MC_STATUS 0x0150 | |
208 #define MEM_IO_OE_CNTL 0x018C | |
209 #define MC_FB_LOCATION 0x0148 | |
210 #define HOST_PATH_CNTL 0x0130 | |
211 #define MEM_VGA_WP_SEL 0x0038 | |
212 #define MEM_VGA_RP_SEL 0x003C | |
213 #define HDP_DEBUG 0x0138 | |
214 #define SW_SEMAPHORE 0x013C | |
215 #define SURFACE_CNTL 0x0B00 | |
216 /* SURFACE_CNTL bit constants */ | |
217 # define SURF_TRANSLATION_DIS (1 << 8) | |
218 # define NONSURF_AP0_SWP_16BPP (1 << 20) | |
219 # define NONSURF_AP0_SWP_32BPP (2 << 20) | |
220 #define SURFACE0_LOWER_BOUND 0x0B04 | |
221 #define SURFACE1_LOWER_BOUND 0x0B14 | |
222 #define SURFACE2_LOWER_BOUND 0x0B24 | |
223 #define SURFACE3_LOWER_BOUND 0x0B34 | |
224 #define SURFACE4_LOWER_BOUND 0x0B44 | |
225 #define SURFACE5_LOWER_BOUND 0x0B54 | |
226 #define SURFACE6_LOWER_BOUND 0x0B64 | |
227 #define SURFACE7_LOWER_BOUND 0x0B74 | |
228 #define SURFACE0_UPPER_BOUND 0x0B08 | |
229 #define SURFACE1_UPPER_BOUND 0x0B18 | |
230 #define SURFACE2_UPPER_BOUND 0x0B28 | |
231 #define SURFACE3_UPPER_BOUND 0x0B38 | |
232 #define SURFACE4_UPPER_BOUND 0x0B48 | |
233 #define SURFACE5_UPPER_BOUND 0x0B58 | |
234 #define SURFACE6_UPPER_BOUND 0x0B68 | |
235 #define SURFACE7_UPPER_BOUND 0x0B78 | |
236 #define SURFACE0_INFO 0x0B0C | |
237 #define SURFACE1_INFO 0x0B1C | |
238 #define SURFACE2_INFO 0x0B2C | |
239 #define SURFACE3_INFO 0x0B3C | |
240 #define SURFACE4_INFO 0x0B4C | |
241 #define SURFACE5_INFO 0x0B5C | |
242 #define SURFACE6_INFO 0x0B6C | |
243 #define SURFACE7_INFO 0x0B7C | |
244 #define SURFACE_ACCESS_FLAGS 0x0BF8 | |
245 #define SURFACE_ACCESS_CLR 0x0BFC | |
246 #define GEN_INT_CNTL 0x0040 | |
247 #define GEN_INT_STATUS 0x0044 | |
248 # define VSYNC_INT_AK (1 << 2) | |
249 # define VSYNC_INT (1 << 2) | |
250 #define CRTC_EXT_CNTL 0x0054 | |
251 /* CRTC_EXT_CNTL bit constants */ | |
252 # define CRTC_VGA_XOVERSCAN (1 << 0) | |
253 # define VGA_ATI_LINEAR 0x00000008 | |
254 # define VGA_128KAP_PAGING 0x00000010 | |
255 # define XCRT_CNT_EN (1 << 6) | |
256 # define CRTC_HSYNC_DIS (1 << 8) | |
257 # define CRTC_VSYNC_DIS (1 << 9) | |
258 # define CRTC_DISPLAY_DIS (1 << 10) | |
259 # define CRTC_SYNC_TRISTAT (1 << 11) | |
260 # define CRTC_CRT_ON (1 << 15) | |
261 #define CRTC_EXT_CNTL_DPMS_BYTE 0x0055 | |
262 # define CRTC_HSYNC_DIS_BYTE (1 << 0) | |
263 # define CRTC_VSYNC_DIS_BYTE (1 << 1) | |
264 # define CRTC_DISPLAY_DIS_BYTE (1 << 2) | |
265 #define RB3D_CNTL 0x1C3C | |
266 #define WAIT_UNTIL 0x1720 | |
267 #define ISYNC_CNTL 0x1724 | |
268 #define RBBM_GUICNTL 0x172C | |
269 #define RBBM_STATUS 0x0E40 | |
270 # define RBBM_FIFOCNT_MASK 0x007f | |
271 # define RBBM_ACTIVE (1 << 31) | |
272 #define RBBM_STATUS_alt_1 0x1740 | |
273 #define RBBM_CNTL 0x00EC | |
274 #define RBBM_CNTL_alt_1 0x0E44 | |
275 #define RBBM_SOFT_RESET 0x00F0 | |
276 /* RBBM_SOFT_RESET bit constants */ | |
277 # define SOFT_RESET_CP (1 << 0) | |
278 # define SOFT_RESET_HI (1 << 1) | |
279 # define SOFT_RESET_SE (1 << 2) | |
280 # define SOFT_RESET_RE (1 << 3) | |
281 # define SOFT_RESET_PP (1 << 4) | |
282 # define SOFT_RESET_E2 (1 << 5) | |
283 # define SOFT_RESET_RB (1 << 6) | |
284 # define SOFT_RESET_HDP (1 << 7) | |
285 #define RBBM_SOFT_RESET_alt_1 0x0E48 | |
286 #define NQWAIT_UNTIL 0x0E50 | |
287 #define RBBM_DEBUG 0x0E6C | |
288 #define RBBM_CMDFIFO_ADDR 0x0E70 | |
289 #define RBBM_CMDFIFO_DATAL 0x0E74 | |
290 #define RBBM_CMDFIFO_DATAH 0x0E78 | |
291 #define RBBM_CMDFIFO_STAT 0x0E7C | |
292 #define CRTC_STATUS 0x005C | |
293 /* CRTC_STATUS bit constants */ | |
294 # define CRTC_VBLANK 0x00000001 | |
295 # define CRTC_VBLANK_SAVE ( 1 << 1) | |
296 #define GPIO_VGA_DDC 0x0060 | |
297 #define GPIO_DVI_DDC 0x0064 | |
298 #define GPIO_MONID 0x0068 | |
299 #define PALETTE_INDEX 0x00B0 | |
300 #define PALETTE_DATA 0x00B4 | |
301 #define PALETTE_30_DATA 0x00B8 | |
302 #define CRTC_H_TOTAL_DISP 0x0200 | |
303 # define CRTC_H_TOTAL (0x03ff << 0) | |
304 # define CRTC_H_TOTAL_SHIFT 0 | |
305 # define CRTC_H_DISP (0x01ff << 16) | |
306 # define CRTC_H_DISP_SHIFT 16 | |
307 #define CRTC2_H_TOTAL_DISP 0x0300 | |
308 # define CRTC2_H_TOTAL (0x03ff << 0) | |
309 # define CRTC2_H_TOTAL_SHIFT 0 | |
310 # define CRTC2_H_DISP (0x01ff << 16) | |
311 # define CRTC2_H_DISP_SHIFT 16 | |
312 #define CRTC_H_SYNC_STRT_WID 0x0204 | |
313 # define CRTC_H_SYNC_STRT_PIX (0x07 << 0) | |
314 # define CRTC_H_SYNC_STRT_CHAR (0x3ff << 3) | |
315 # define CRTC_H_SYNC_STRT_CHAR_SHIFT 3 | |
316 # define CRTC_H_SYNC_WID (0x3f << 16) | |
317 # define CRTC_H_SYNC_WID_SHIFT 16 | |
318 # define CRTC_H_SYNC_POL (1 << 23) | |
319 #define CRTC2_H_SYNC_STRT_WID 0x0304 | |
320 # define CRTC2_H_SYNC_STRT_PIX (0x07 << 0) | |
321 # define CRTC2_H_SYNC_STRT_CHAR (0x3ff << 3) | |
322 # define CRTC2_H_SYNC_STRT_CHAR_SHIFT 3 | |
323 # define CRTC2_H_SYNC_WID (0x3f << 16) | |
324 # define CRTC2_H_SYNC_WID_SHIFT 16 | |
325 # define CRTC2_H_SYNC_POL (1 << 23) | |
326 #define CRTC_V_TOTAL_DISP 0x0208 | |
327 # define CRTC_V_TOTAL (0x07ff << 0) | |
328 # define CRTC_V_TOTAL_SHIFT 0 | |
329 # define CRTC_V_DISP (0x07ff << 16) | |
330 # define CRTC_V_DISP_SHIFT 16 | |
331 #define CRTC2_V_TOTAL_DISP 0x0308 | |
332 # define CRTC2_V_TOTAL (0x07ff << 0) | |
333 # define CRTC2_V_TOTAL_SHIFT 0 | |
334 # define CRTC2_V_DISP (0x07ff << 16) | |
335 # define CRTC2_V_DISP_SHIFT 16 | |
336 #define CRTC_V_SYNC_STRT_WID 0x020C | |
337 # define CRTC_V_SYNC_STRT (0x7ff << 0) | |
338 # define CRTC_V_SYNC_STRT_SHIFT 0 | |
339 # define CRTC_V_SYNC_WID (0x1f << 16) | |
340 # define CRTC_V_SYNC_WID_SHIFT 16 | |
341 # define CRTC_V_SYNC_POL (1 << 23) | |
342 #define CRTC2_V_SYNC_STRT_WID 0x030C | |
343 # define CRTC2_V_SYNC_STRT (0x7ff << 0) | |
344 # define CRTC2_V_SYNC_STRT_SHIFT 0 | |
345 # define CRTC2_V_SYNC_WID (0x1f << 16) | |
346 # define CRTC2_V_SYNC_WID_SHIFT 16 | |
347 # define CRTC2_V_SYNC_POL (1 << 23) | |
348 #define CRTC_VLINE_CRNT_VLINE 0x0210 | |
349 # define CRTC_CRNT_VLINE_MASK (0x7ff << 16) | |
350 #define CRTC2_VLINE_CRNT_VLINE 0x0310 | |
351 #define CRTC_CRNT_FRAME 0x0214 | |
352 #define CRTC2_CRNT_FRAME 0x0314 | |
353 #define CRTC_GUI_TRIG_VLINE 0x0218 | |
354 #define CRTC2_GUI_TRIG_VLINE 0x0318 | |
355 #define CRTC_DEBUG 0x021C | |
356 #define CRTC2_DEBUG 0x031C | |
357 #define CRTC_OFFSET_RIGHT 0x0220 | |
358 #define CRTC_OFFSET 0x0224 | |
359 #define CRTC2_OFFSET 0x0324 | |
360 #define CRTC_OFFSET_CNTL 0x0228 | |
361 # define CRTC_TILE_EN (1 << 15) | |
362 #define CRTC2_OFFSET_CNTL 0x0328 | |
363 # define CRTC2_TILE_EN (1 << 15) | |
364 #define CRTC_PITCH 0x022C | |
365 #define CRTC2_PITCH 0x032C | |
366 #define TMDS_CRC 0x02a0 | |
367 #define OVR_CLR 0x0230 | |
368 #define OVR_WID_LEFT_RIGHT 0x0234 | |
369 #define OVR_WID_TOP_BOTTOM 0x0238 | |
370 #define DISPLAY_BASE_ADDR 0x023C | |
371 #define SNAPSHOT_VH_COUNTS 0x0240 | |
372 #define SNAPSHOT_F_COUNT 0x0244 | |
373 #define N_VIF_COUNT 0x0248 | |
374 #define SNAPSHOT_VIF_COUNT 0x024C | |
375 #define FP_CRTC_H_TOTAL_DISP 0x0250 | |
376 #define FP_CRTC2_H_TOTAL_DISP 0x0350 | |
377 #define FP_CRTC_V_TOTAL_DISP 0x0254 | |
378 #define FP_CRTC2_V_TOTAL_DISP 0x0354 | |
379 # define FP_CRTC_H_TOTAL_MASK 0x000003ff | |
380 # define FP_CRTC_H_DISP_MASK 0x01ff0000 | |
381 # define FP_CRTC_V_TOTAL_MASK 0x00000fff | |
382 # define FP_CRTC_V_DISP_MASK 0x0fff0000 | |
383 # define FP_H_SYNC_STRT_CHAR_MASK 0x00001ff8 | |
384 # define FP_H_SYNC_WID_MASK 0x003f0000 | |
385 # define FP_V_SYNC_STRT_MASK 0x00000fff | |
386 # define FP_V_SYNC_WID_MASK 0x001f0000 | |
387 # define FP_CRTC_H_TOTAL_SHIFT 0x00000000 | |
388 # define FP_CRTC_H_DISP_SHIFT 0x00000010 | |
389 # define FP_CRTC_V_TOTAL_SHIFT 0x00000000 | |
390 # define FP_CRTC_V_DISP_SHIFT 0x00000010 | |
391 # define FP_H_SYNC_STRT_CHAR_SHIFT 0x00000003 | |
392 # define FP_H_SYNC_WID_SHIFT 0x00000010 | |
393 # define FP_V_SYNC_STRT_SHIFT 0x00000000 | |
394 # define FP_V_SYNC_WID_SHIFT 0x00000010 | |
395 #define CRT_CRTC_H_SYNC_STRT_WID 0x0258 | |
396 #define CRT_CRTC_V_SYNC_STRT_WID 0x025C | |
397 #define CUR_OFFSET 0x0260 | |
398 #define CUR_HORZ_VERT_POSN 0x0264 | |
399 #define CUR_HORZ_VERT_OFF 0x0268 | |
400 /* CUR_OFFSET, CUR_HORZ_VERT_POSN, CUR_HORZ_VERT_OFF bit constants */ | |
401 # define CUR_LOCK 0x80000000 | |
402 #define CUR_CLR0 0x026C | |
403 #define CUR_CLR1 0x0270 | |
404 #define CUR2_OFFSET 0x0360 | |
405 #define CUR2_HORZ_VERT_POSN 0x0364 | |
406 #define CUR2_HORZ_VERT_OFF 0x0368 | |
407 # define CUR2_LOCK (1 << 31) | |
408 #define CUR2_CLR0 0x036c | |
409 #define CUR2_CLR1 0x0370 | |
410 #define FP_HORZ_VERT_ACTIVE 0x0278 | |
411 #define CRTC_MORE_CNTL 0x027C | |
412 #define DAC_EXT_CNTL 0x0280 | |
413 #define FP_GEN_CNTL 0x0284 | |
414 /* FP_GEN_CNTL bit constants */ | |
415 # define FP_FPON (1 << 0) | |
416 # define FP_TMDS_EN (1 << 2) | |
417 # define FP_EN_TMDS (1 << 7) | |
418 # define FP_DETECT_SENSE (1 << 8) | |
419 # define FP_SEL_CRTC2 (1 << 13) | |
420 # define FP_CRTC_DONT_SHADOW_HPAR (1 << 15) | |
421 # define FP_CRTC_DONT_SHADOW_VPAR (1 << 16) | |
422 # define FP_CRTC_DONT_SHADOW_HEND (1 << 17) | |
423 # define FP_CRTC_USE_SHADOW_VEND (1 << 18) | |
424 # define FP_RMX_HVSYNC_CONTROL_EN (1 << 20) | |
425 # define FP_DFP_SYNC_SEL (1 << 21) | |
426 # define FP_CRTC_LOCK_8DOT (1 << 22) | |
427 # define FP_CRT_SYNC_SEL (1 << 23) | |
428 # define FP_USE_SHADOW_EN (1 << 24) | |
429 # define FP_CRT_SYNC_ALT (1 << 26) | |
430 #define FP2_GEN_CNTL 0x0288 | |
431 /* FP2_GEN_CNTL bit constants */ | |
432 # define FP2_FPON (1 << 0) | |
433 # define FP2_TMDS_EN (1 << 2) | |
434 # define FP2_EN_TMDS (1 << 7) | |
435 # define FP2_DETECT_SENSE (1 << 8) | |
436 # define FP2_SEL_CRTC2 (1 << 13) | |
437 # define FP2_FP_POL (1 << 16) | |
438 # define FP2_LP_POL (1 << 17) | |
439 # define FP2_SCK_POL (1 << 18) | |
440 # define FP2_LCD_CNTL_MASK (7 << 19) | |
441 # define FP2_PAD_FLOP_EN (1 << 22) | |
442 # define FP2_CRC_EN (1 << 23) | |
443 # define FP2_CRC_READ_EN (1 << 24) | |
444 #define FP_HORZ_STRETCH 0x028C | |
445 #define FP_HORZ2_STRETCH 0x038C | |
446 # define HORZ_STRETCH_RATIO_MASK 0xffff | |
447 # define HORZ_STRETCH_RATIO_MAX 4096 | |
448 # define HORZ_PANEL_SIZE (0x1ff << 16) | |
449 # define HORZ_PANEL_SHIFT 16 | |
450 # define HORZ_STRETCH_PIXREP (0 << 25) | |
451 # define HORZ_STRETCH_BLEND (1 << 26) | |
452 # define HORZ_STRETCH_ENABLE (1 << 25) | |
453 # define HORZ_AUTO_RATIO (1 << 27) | |
454 # define HORZ_FP_LOOP_STRETCH (0x7 << 28) | |
455 # define HORZ_AUTO_RATIO_INC (1 << 31) | |
456 #define FP_VERT_STRETCH 0x0290 | |
457 #define FP_VERT2_STRETCH 0x0390 | |
458 # define VERT_PANEL_SIZE (0xfff << 12) | |
459 # define VERT_PANEL_SHIFT 12 | |
460 # define VERT_STRETCH_RATIO_MASK 0xfff | |
461 # define VERT_STRETCH_RATIO_SHIFT 0 | |
462 # define VERT_STRETCH_RATIO_MAX 4096 | |
463 # define VERT_STRETCH_ENABLE (1 << 25) | |
464 # define VERT_STRETCH_LINEREP (0 << 26) | |
465 # define VERT_STRETCH_BLEND (1 << 26) | |
466 # define VERT_AUTO_RATIO_EN (1 << 27) | |
467 # define VERT_STRETCH_RESERVED 0xf1000000 | |
468 #define FP_H_SYNC_STRT_WID 0x02C4 | |
469 #define FP_H2_SYNC_STRT_WID 0x03C4 | |
470 #define FP_V_SYNC_STRT_WID 0x02C8 | |
471 #define FP_V2_SYNC_STRT_WID 0x03C8 | |
472 #define LVDS_GEN_CNTL 0x02d0 | |
473 # define LVDS_ON (1 << 0) | |
474 # define LVDS_DISPLAY_DIS (1 << 1) | |
475 # define LVDS_PANEL_TYPE (1 << 2) | |
476 # define LVDS_PANEL_FORMAT (1 << 3) | |
477 # define LVDS_EN (1 << 7) | |
478 # define LVDS_DIGON (1 << 18) | |
479 # define LVDS_BLON (1 << 19) | |
480 # define LVDS_SEL_CRTC2 (1 << 23) | |
481 #define LVDS_PLL_CNTL 0x02d4 | |
482 # define HSYNC_DELAY_SHIFT 28 | |
483 # define HSYNC_DELAY_MASK (0xf << 28) | |
484 #define AUX_WINDOW_HORZ_CNTL 0x02D8 | |
485 #define AUX_WINDOW_VERT_CNTL 0x02DC | |
486 #define DDA_CONFIG 0x02e0 | |
487 #define DDA_ON_OFF 0x02e4 | |
488 | |
489 #define GRPH_BUFFER_CNTL 0x02F0 | |
490 #define VGA_BUFFER_CNTL 0x02F4 | |
491 | |
492 /* first overlay unit (there is only one) */ | |
493 | |
494 #define OV0_Y_X_START 0x0400 | |
495 #define OV0_Y_X_END 0x0404 | |
496 #define OV0_PIPELINE_CNTL 0x0408 | |
497 #define OV0_EXCLUSIVE_HORZ 0x0408 | |
498 # define EXCL_HORZ_START_MASK 0x000000ff | |
499 # define EXCL_HORZ_END_MASK 0x0000ff00 | |
500 # define EXCL_HORZ_BACK_PORCH_MASK 0x00ff0000 | |
501 # define EXCL_HORZ_EXCLUSIVE_EN 0x80000000 | |
502 #define OV0_EXCLUSIVE_VERT 0x040C | |
503 # define EXCL_VERT_START_MASK 0x000003ff | |
504 # define EXCL_VERT_END_MASK 0x03ff0000 | |
505 #define OV0_REG_LOAD_CNTL 0x0410 | |
506 # define REG_LD_CTL_LOCK 0x00000001L | |
507 # define REG_LD_CTL_VBLANK_DURING_LOCK 0x00000002L | |
508 # define REG_LD_CTL_STALL_GUI_UNTIL_FLIP 0x00000004L | |
509 # define REG_LD_CTL_LOCK_READBACK 0x00000008L | |
510 #define OV0_SCALE_CNTL 0x0420 | |
511 # define SCALER_PIX_EXPAND 0x00000001L | |
512 # define SCALER_Y2R_TEMP 0x00000002L | |
513 #ifdef RAGE128 | |
514 # define SCALER_HORZ_PICK_NEAREST 0x00000003L | |
515 # define SCALER_VERT_PICK_NEAREST 0x00000004L | |
516 #else | |
517 # define SCALER_HORZ_PICK_NEAREST 0x00000004L | |
518 # define SCALER_VERT_PICK_NEAREST 0x00000008L | |
519 #endif | |
520 # define SCALER_SIGNED_UV 0x00000010L | |
521 # define SCALER_GAMMA_SEL_MASK 0x00000060L | |
522 # define SCALER_GAMMA_SEL_BRIGHT 0x00000000L | |
523 # define SCALER_GAMMA_SEL_G22 0x00000020L | |
524 # define SCALER_GAMMA_SEL_G18 0x00000040L | |
525 # define SCALER_GAMMA_SEL_G14 0x00000060L | |
526 # define SCALER_COMCORE_SHIFT_UP_ONE 0x00000080L | |
527 # define SCALER_SURFAC_FORMAT 0x00000f00L | |
528 # define SCALER_SOURCE_UNK0 0x00000000L /* 2 bpp ??? */ | |
529 # define SCALER_SOURCE_UNK1 0x00000100L /* 4 bpp ??? */ | |
530 # define SCALER_SOURCE_UNK2 0x00000200L /* 8 bpp ??? */ | |
531 # define SCALER_SOURCE_15BPP 0x00000300L | |
532 # define SCALER_SOURCE_16BPP 0x00000400L | |
4417 | 533 /*# define SCALER_SOURCE_24BPP 0x00000500L*/ |
3996 | 534 # define SCALER_SOURCE_32BPP 0x00000600L |
535 # define SCALER_SOURCE_UNK3 0x00000700L /* 8BPP_RGB332 ??? */ | |
536 # define SCALER_SOURCE_UNK4 0x00000800L /* 8BPP_Y8 ??? */ | |
537 # define SCALER_SOURCE_YUV9 0x00000900L /* 8BPP_RGB8 */ | |
538 # define SCALER_SOURCE_YUV12 0x00000A00L | |
539 # define SCALER_SOURCE_VYUY422 0x00000B00L | |
540 # define SCALER_SOURCE_YVYU422 0x00000C00L | |
541 # define SCALER_SOURCE_UNK5 0x00000D00L /* ??? */ | |
542 # define SCALER_SOURCE_UNK6 0x00000E00L /* 32BPP_AYUV444 */ | |
543 # define SCALER_SOURCE_UNK7 0x00000F00L /* 16BPP_ARGB4444 */ | |
544 # define SCALER_ADAPTIVE_DEINT 0x00001000L | |
545 # define R200_SCALER_TEMPORAL_DEINT 0x00002000L | |
546 # define SCALER_UNKNOWN_FLAG1 0x00004000L /* ??? */ | |
547 # define SCALER_SMART_SWITCH 0x00008000L | |
548 #ifdef RAGE128 | |
549 # define SCALER_BURST_PER_PLANE 0x00ff0000L | |
550 #else | |
551 # define SCALER_BURST_PER_PLANE 0x007f0000L | |
552 #endif | |
553 # define SCALER_DOUBLE_BUFFER 0x01000000L | |
554 # define SCALER_UNKNOWN_FLAG3 0x02000000L /* ??? */ | |
555 # define SCALER_UNKNOWN_FLAG4 0x04000000L /* ??? */ | |
556 # define SCALER_DIS_LIMIT 0x08000000L | |
557 # define SCALER_PRG_LOAD_START 0x10000000L | |
558 # define SCALER_INT_EMU 0x20000000L | |
559 # define SCALER_ENABLE 0x40000000L | |
560 # define SCALER_SOFT_RESET 0x80000000L | |
561 #define OV0_V_INC 0x0424 | |
562 #define OV0_P1_V_ACCUM_INIT 0x0428 | |
563 # define OV0_P1_MAX_LN_IN_PER_LN_OUT 0x00000003L | |
564 # define OV0_P1_V_ACCUM_INIT_MASK 0x01ff8000L | |
565 #define OV0_P23_V_ACCUM_INIT 0x042C | |
566 # define OV0_P23_MAX_LN_IN_PER_LN_OUT 0x00000003L | |
567 # define OV0_P23_V_ACCUM_INIT_MASK 0x01ff8000L | |
568 #define OV0_P1_BLANK_LINES_AT_TOP 0x0430 | |
569 # define P1_BLNK_LN_AT_TOP_M1_MASK 0x00000fffL | |
570 # define P1_ACTIVE_LINES_M1 0x0fff0000L | |
571 #define OV0_P23_BLANK_LINES_AT_TOP 0x0434 | |
572 # define P23_BLNK_LN_AT_TOP_M1_MASK 0x000007ffL | |
573 # define P23_ACTIVE_LINES_M1 0x07ff0000L | |
574 #ifndef RAGE128 | |
575 #define OV0_BASE_ADDR 0x043C | |
576 #endif | |
577 #define OV0_VID_BUF0_BASE_ADRS 0x0440 | |
578 # define VIF_BUF0_PITCH_SEL 0x00000001L | |
579 # define VIF_BUF0_TILE_ADRS 0x00000002L | |
580 # define VIF_BUF0_BASE_ADRS_MASK 0x03fffff0L | |
581 # define VIF_BUF0_1ST_LINE_LSBS_MASK 0x48000000L | |
582 #define OV0_VID_BUF1_BASE_ADRS 0x0444 | |
583 # define VIF_BUF1_PITCH_SEL 0x00000001L | |
584 # define VIF_BUF1_TILE_ADRS 0x00000002L | |
585 # define VIF_BUF1_BASE_ADRS_MASK 0x03fffff0L | |
586 # define VIF_BUF1_1ST_LINE_LSBS_MASK 0x48000000L | |
587 #define OV0_VID_BUF2_BASE_ADRS 0x0448 | |
588 # define VIF_BUF2_PITCH_SEL 0x00000001L | |
589 # define VIF_BUF2_TILE_ADRS 0x00000002L | |
590 # define VIF_BUF2_BASE_ADRS_MASK 0x03fffff0L | |
591 # define VIF_BUF2_1ST_LINE_LSBS_MASK 0x48000000L | |
592 #define OV0_VID_BUF3_BASE_ADRS 0x044C | |
593 # define VIF_BUF3_PITCH_SEL 0x00000001L | |
594 # define VIF_BUF3_TILE_ADRS 0x00000002L | |
595 # define VIF_BUF3_BASE_ADRS_MASK 0x03fffff0L | |
596 # define VIF_BUF3_1ST_LINE_LSBS_MASK 0x48000000L | |
597 #define OV0_VID_BUF4_BASE_ADRS 0x0450 | |
598 # define VIF_BUF4_PITCH_SEL 0x00000001L | |
599 # define VIF_BUF4_TILE_ADRS 0x00000002L | |
600 # define VIF_BUF4_BASE_ADRS_MASK 0x03fffff0L | |
601 # define VIF_BUF4_1ST_LINE_LSBS_MASK 0x48000000L | |
602 #define OV0_VID_BUF5_BASE_ADRS 0x0454 | |
603 # define VIF_BUF5_PITCH_SEL 0x00000001L | |
604 # define VIF_BUF5_TILE_ADRS 0x00000002L | |
605 # define VIF_BUF5_BASE_ADRS_MASK 0x03fffff0L | |
606 # define VIF_BUF5_1ST_LINE_LSBS_MASK 0x48000000L | |
607 #define OV0_VID_BUF_PITCH0_VALUE 0x0460 | |
608 #define OV0_VID_BUF_PITCH1_VALUE 0x0464 | |
609 #define OV0_AUTO_FLIP_CNTL 0x0470 | |
610 # define OV0_AUTO_FLIP_CNTL_SOFT_BUF_NUM 0x00000007 | |
611 # define OV0_AUTO_FLIP_CNTL_SOFT_REPEAT_FIELD 0x00000008 | |
612 # define OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD 0x00000010 | |
613 # define OV0_AUTO_FLIP_CNTL_IGNORE_REPEAT_FIELD 0x00000020 | |
614 # define OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE 0x00000040 | |
615 # define OV0_AUTO_FLIP_CNTL_VID_PORT_SELECT 0x00000300 | |
616 # define OV0_AUTO_FLIP_CNTL_P1_FIRST_LINE_EVEN 0x00010000 | |
617 # define OV0_AUTO_FLIP_CNTL_SHIFT_EVEN_DOWN 0x00040000 | |
618 # define OV0_AUTO_FLIP_CNTL_SHIFT_ODD_DOWN 0x00080000 | |
619 # define OV0_AUTO_FLIP_CNTL_FIELD_POL_SOURCE 0x00800000 | |
620 #define OV0_DEINTERLACE_PATTERN 0x0474 | |
621 #define OV0_SUBMIT_HISTORY 0x0478 | |
622 #define OV0_H_INC 0x0480 | |
623 #define OV0_STEP_BY 0x0484 | |
624 #define OV0_P1_H_ACCUM_INIT 0x0488 | |
625 #define OV0_P23_H_ACCUM_INIT 0x048C | |
626 #define OV0_P1_X_START_END 0x0494 | |
627 #define OV0_P2_X_START_END 0x0498 | |
628 #define OV0_P3_X_START_END 0x049C | |
629 #define OV0_FILTER_CNTL 0x04A0 | |
630 # define FILTER_PROGRAMMABLE_COEF 0x00000000 | |
4404 | 631 # define FILTER_HARD_SCALE_HORZ_Y 0x00000001 |
632 # define FILTER_HARD_SCALE_HORZ_UV 0x00000002 | |
633 # define FILTER_HARD_SCALE_VERT_Y 0x00000004 | |
634 # define FILTER_HARD_SCALE_VERT_UV 0x00000008 | |
3996 | 635 # define FILTER_HARDCODED_COEF 0x0000000F |
636 # define FILTER_COEF_MASK 0x0000000F | |
4404 | 637 /* When bit is set hard coded coefficients are used. */ |
638 | |
3996 | 639 /* |
640 Top quality 4x4-tap filtered vertical and horizontal scaler. | |
641 It allows up to 64:1 upscaling and downscaling without | |
642 performance or quality degradation. | |
643 */ | |
644 #define OV0_FOUR_TAP_COEF_0 0x04B0 | |
4404 | 645 # define OV0_FOUR_TAP_PHASE_0_TAP_0 0x0000000F |
646 # define OV0_FOUR_TAP_PHASE_0_TAP_1 0x00007F00 | |
647 # define OV0_FOUR_TAP_PHASE_0_TAP_2 0x007F0000 | |
648 # define OV0_FOUR_TAP_PHASE_0_TAP_3 0x0F000000 | |
3996 | 649 #define OV0_FOUR_TAP_COEF_1 0x04B4 |
4404 | 650 # define OV0_FOUR_TAP_PHASE_1_5_TAP_0 0x0000000F |
651 # define OV0_FOUR_TAP_PHASE_1_5_TAP_1 0x00007F00 | |
652 # define OV0_FOUR_TAP_PHASE_1_5_TAP_2 0x007F0000 | |
653 # define OV0_FOUR_TAP_PHASE_1_5_TAP_3 0x0F000000 | |
3996 | 654 #define OV0_FOUR_TAP_COEF_2 0x04B8 |
4404 | 655 # define OV0_FOUR_TAP_PHASE_2_6_TAP_0 0x0000000F |
656 # define OV0_FOUR_TAP_PHASE_2_6_TAP_1 0x00007F00 | |
657 # define OV0_FOUR_TAP_PHASE_2_6_TAP_2 0x007F0000 | |
658 # define OV0_FOUR_TAP_PHASE_2_6_TAP_3 0x0F000000 | |
3996 | 659 #define OV0_FOUR_TAP_COEF_3 0x04BC |
4404 | 660 # define OV0_FOUR_TAP_PHASE_3_7_TAP_0 0x0000000F |
661 # define OV0_FOUR_TAP_PHASE_3_7_TAP_1 0x00007F00 | |
662 # define OV0_FOUR_TAP_PHASE_3_7_TAP_2 0x007F0000 | |
663 # define OV0_FOUR_TAP_PHASE_3_7_TAP_3 0x0F000000 | |
3996 | 664 #define OV0_FOUR_TAP_COEF_4 0x04C0 |
4404 | 665 # define OV0_FOUR_TAP_PHASE_4_TAP_0 0x0000000F |
666 # define OV0_FOUR_TAP_PHASE_4_TAP_1 0x00007F00 | |
667 # define OV0_FOUR_TAP_PHASE_4_TAP_2 0x007F0000 | |
668 # define OV0_FOUR_TAP_PHASE_4_TAP_3 0x0F000000 | |
669 /* 0th_tap means that the left most of top most pixel in a set of four will | |
670 be multiplied by this coefficient. */ | |
3996 | 671 |
672 #define OV0_FLAG_CNTL 0x04DC | |
673 #ifdef RAGE128 | |
674 #define OV0_COLOUR_CNTL 0x04E0 | |
675 # define COLOUR_CNTL_BRIGHTNESS 0x0000007F | |
676 # define COLOUR_CNTL_SATURATION 0x001F1F00 | |
677 #else | |
678 /* NB: radeons have no COLOUR_CNTL register */ | |
679 #define OV0_SLICE_CNTL 0x04E0 | |
680 # define SLICE_CNTL_DISABLE 0x40000000 | |
681 #endif | |
682 /* Video and graphics keys allow alpha blending, color correction | |
683 and many other video effects */ | |
684 #define OV0_VID_KEY_CLR 0x04E4 | |
685 #define OV0_VID_KEY_MSK 0x04E8 | |
686 #define OV0_GRAPHICS_KEY_CLR 0x04EC | |
687 #define OV0_GRAPHICS_KEY_MSK 0x04F0 | |
688 #define OV0_KEY_CNTL 0x04F4 | |
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689 # define VIDEO_KEY_FN_MASK 0x00000003L |
3996 | 690 # define VIDEO_KEY_FN_FALSE 0x00000000L |
691 # define VIDEO_KEY_FN_TRUE 0x00000001L | |
5044
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692 # define VIDEO_KEY_FN_EQ 0x00000002L |
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Fixed color key definitions. Waiting for new bugreports ;)
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693 # define VIDEO_KEY_FN_NE 0x00000003L |
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Fixed color key definitions. Waiting for new bugreports ;)
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694 # define GRAPHIC_KEY_FN_MASK 0x00000030L |
3996 | 695 # define GRAPHIC_KEY_FN_FALSE 0x00000000L |
696 # define GRAPHIC_KEY_FN_TRUE 0x00000010L | |
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697 # define GRAPHIC_KEY_FN_EQ 0x00000020L |
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698 # define GRAPHIC_KEY_FN_NE 0x00000030L |
3996 | 699 # define CMP_MIX_MASK 0x00000100L |
700 # define CMP_MIX_OR 0x00000000L | |
701 # define CMP_MIX_AND 0x00000100L | |
702 #define OV0_TEST 0x04F8 | |
703 #define OV0_LIN_TRANS_A 0x0D20 | |
704 #define OV0_LIN_TRANS_B 0x0D24 | |
705 #define OV0_LIN_TRANS_C 0x0D28 | |
706 #define OV0_LIN_TRANS_D 0x0D2C | |
707 #define OV0_LIN_TRANS_E 0x0D30 | |
708 #define OV0_LIN_TRANS_F 0x0D34 | |
709 #define OV0_GAMMA_0_F 0x0D40 | |
710 #define OV0_GAMMA_10_1F 0x0D44 | |
711 #define OV0_GAMMA_20_3F 0x0D48 | |
712 #define OV0_GAMMA_40_7F 0x0D4C | |
713 /* These registers exist on R200 only */ | |
714 #define OV0_GAMMA_80_BF 0x0E00 | |
715 #define OV0_GAMMA_C0_FF 0x0E04 | |
716 #define OV0_GAMMA_100_13F 0x0E08 | |
717 #define OV0_GAMMA_140_17F 0x0E0C | |
718 #define OV0_GAMMA_180_1BF 0x0E10 | |
719 #define OV0_GAMMA_1C0_1FF 0x0E14 | |
720 #define OV0_GAMMA_200_23F 0x0E18 | |
721 #define OV0_GAMMA_240_27F 0x0E1C | |
722 #define OV0_GAMMA_280_2BF 0x0E20 | |
723 #define OV0_GAMMA_2C0_2FF 0x0E24 | |
724 #define OV0_GAMMA_300_33F 0x0E28 | |
725 #define OV0_GAMMA_340_37F 0x0E2C | |
726 /* End of R200 specific definitions */ | |
727 #define OV0_GAMMA_380_3BF 0x0D50 | |
728 #define OV0_GAMMA_3C0_3FF 0x0D54 | |
729 | |
730 /* | |
731 IDCT ENGINE: | |
732 It's MPEG-2 hardware decoder which incorporates run-level decode, de-zigzag | |
733 and IDCT into an IDCT engine to complement the motion compensation engine. | |
734 */ | |
735 #define IDCT_RUNS 0x1F80 | |
736 #define IDCT_LEVELS 0x1F84 | |
737 #define IDCT_AUTH_CONTROL 0x1F88 | |
738 #define IDCT_AUTH 0x1F8C | |
739 #define IDCT_CONTROL 0x1FBC | |
740 | |
741 #define SE_MC_SRC2_CNTL 0x19D4 | |
742 #define SE_MC_SRC1_CNTL 0x19D8 | |
743 #define SE_MC_DST_CNTL 0x19DC | |
744 #define SE_MC_CNTL_START 0x19E0 | |
745 #ifndef RAGE128 | |
746 #define SE_MC_BUF_BASE 0x19E4 | |
747 #define PP_MC_CONTEXT 0x19E8 | |
748 #define PP_MISC 0x1C14 | |
749 #endif | |
750 /* | |
751 SUBPICTURE UNIT: | |
752 Decompressing, scaling and alpha blending the compressed bitmap on the fly. | |
753 Provide optimal DVD subpicture qualtity. | |
754 */ | |
755 #define SUBPIC_CNTL 0x0540 | |
756 #define SUBPIC_DEFCOLCON 0x0544 | |
757 #define SUBPIC_Y_X_START 0x054C | |
758 #define SUBPIC_Y_X_END 0x0550 | |
759 #define SUBPIC_V_INC 0x0554 | |
760 #define SUBPIC_H_INC 0x0558 | |
761 #define SUBPIC_BUF0_OFFSET 0x055C | |
762 #define SUBPIC_BUF1_OFFSET 0x0560 | |
763 #define SUBPIC_LC0_OFFSET 0x0564 | |
764 #define SUBPIC_LC1_OFFSET 0x0568 | |
765 #define SUBPIC_PITCH 0x056C | |
766 #define SUBPIC_BTN_HLI_COLCON 0x0570 | |
767 #define SUBPIC_BTN_HLI_Y_X_START 0x0574 | |
768 #define SUBPIC_BTN_HLI_Y_X_END 0x0578 | |
769 #define SUBPIC_PALETTE_INDEX 0x057C | |
770 #define SUBPIC_PALETTE_DATA 0x0580 | |
771 #define SUBPIC_H_ACCUM_INIT 0x0584 | |
772 #define SUBPIC_V_ACCUM_INIT 0x0588 | |
773 | |
774 #define CP_RB_BASE 0x0700 | |
775 #define CP_RB_CNTL 0x0704 | |
776 #define CP_RB_RPTR_ADDR 0x070C | |
777 #define CP_RB_RPTR 0x0710 | |
778 #define CP_RB_WPTR 0x0714 | |
779 #define CP_RB_WPTR_DELAY 0x0718 | |
780 #define CP_IB_BASE 0x0738 | |
781 #define CP_IB_BUFSZ 0x073C | |
782 #define CP_CSQ_CNTL 0x0740 | |
783 #define SCRATCH_UMSK 0x0770 | |
784 #define SCRATCH_ADDR 0x0774 | |
785 #define DMA_GUI_TABLE_ADDR 0x0780 | |
786 #define DMA_GUI_SRC_ADDR 0x0784 | |
787 #define DMA_GUI_DST_ADDR 0x0788 | |
788 #define DMA_GUI_COMMAND 0x078C | |
789 #define DMA_GUI_STATUS 0x0790 | |
790 #define DMA_GUI_ACT_DSCRPTR 0x0794 | |
791 #define DMA_VID_TABLE_ADDR 0x07A0 | |
792 #define DMA_VID_SRC_ADDR 0x07A4 | |
793 #define DMA_VID_DST_ADDR 0x07A8 | |
794 #define DMA_VID_COMMAND 0x07AC | |
795 #define DMA_VID_STATUS 0x07B0 | |
796 #define DMA_VID_ACT_DSCRPTR 0x07B4 | |
797 #define CP_ME_CNTL 0x07D0 | |
798 #define CP_ME_RAM_ADDR 0x07D4 | |
799 #define CP_ME_RAM_RADDR 0x07D8 | |
800 #define CP_ME_RAM_DATAH 0x07DC | |
801 #define CP_ME_RAM_DATAL 0x07E0 | |
802 #define CP_CSQ_ADDR 0x07F0 | |
803 #define CP_CSQ_DATA 0x07F4 | |
804 #define CP_CSQ_STAT 0x07F8 | |
805 | |
806 #define DISP_MISC_CNTL 0x0D00 | |
807 # define SOFT_RESET_GRPH_PP (1 << 0) | |
808 #define DAC_MACRO_CNTL 0x0D04 | |
809 #define DISP_PWR_MAN 0x0D08 | |
810 #define DISP_TEST_DEBUG_CNTL 0x0D10 | |
811 #define DISP_HW_DEBUG 0x0D14 | |
812 #define DAC_CRC_SIG1 0x0D18 | |
813 #define DAC_CRC_SIG2 0x0D1C | |
814 | |
815 /* first capture unit */ | |
816 | |
817 #define VID_BUFFER_CONTROL 0x0900 | |
818 #define CAP_INT_CNTL 0x0908 | |
819 #define CAP_INT_STATUS 0x090C | |
820 #define FCP_CNTL 0x0910 | |
4666 | 821 # define FCP_CNTL__PCICLK 0 |
822 # define FCP_CNTL__PCLK 1 | |
4690 | 823 # define FCP_CNTL__PCLKb 2 |
4666 | 824 # define FCP_CNTL__HREF 3 |
825 # define FCP_CNTL__GND 4 | |
4690 | 826 # define FCP_CNTL__HREFb 5 |
4666 | 827 |
3996 | 828 #define CAP0_BUF0_OFFSET 0x0920 |
829 #define CAP0_BUF1_OFFSET 0x0924 | |
830 #define CAP0_BUF0_EVEN_OFFSET 0x0928 | |
831 #define CAP0_BUF1_EVEN_OFFSET 0x092C | |
832 #define CAP0_BUF_PITCH 0x0930 | |
833 #define CAP0_V_WINDOW 0x0934 | |
834 #define CAP0_H_WINDOW 0x0938 | |
835 #define CAP0_VBI0_OFFSET 0x093C | |
836 #define CAP0_VBI1_OFFSET 0x0940 | |
837 #define CAP0_VBI_V_WINDOW 0x0944 | |
838 #define CAP0_VBI_H_WINDOW 0x0948 | |
839 #define CAP0_PORT_MODE_CNTL 0x094C | |
840 #define CAP0_TRIG_CNTL 0x0950 | |
841 #define CAP0_DEBUG 0x0954 | |
842 #define CAP0_CONFIG 0x0958 | |
843 # define CAP0_CONFIG_CONTINUOS 0x00000001 | |
844 # define CAP0_CONFIG_START_FIELD_EVEN 0x00000002 | |
845 # define CAP0_CONFIG_START_BUF_GET 0x00000004 | |
846 # define CAP0_CONFIG_START_BUF_SET 0x00000008 | |
847 # define CAP0_CONFIG_BUF_TYPE_ALT 0x00000010 | |
848 # define CAP0_CONFIG_BUF_TYPE_FRAME 0x00000020 | |
849 # define CAP0_CONFIG_ONESHOT_MODE_FRAME 0x00000040 | |
850 # define CAP0_CONFIG_BUF_MODE_DOUBLE 0x00000080 | |
851 # define CAP0_CONFIG_BUF_MODE_TRIPLE 0x00000100 | |
852 # define CAP0_CONFIG_MIRROR_EN 0x00000200 | |
853 # define CAP0_CONFIG_ONESHOT_MIRROR_EN 0x00000400 | |
854 # define CAP0_CONFIG_VIDEO_SIGNED_UV 0x00000800 | |
855 # define CAP0_CONFIG_ANC_DECODE_EN 0x00001000 | |
856 # define CAP0_CONFIG_VBI_EN 0x00002000 | |
857 # define CAP0_CONFIG_SOFT_PULL_DOWN_EN 0x00004000 | |
858 # define CAP0_CONFIG_VIP_EXTEND_FLAG_EN 0x00008000 | |
859 # define CAP0_CONFIG_FAKE_FIELD_EN 0x00010000 | |
860 # define CAP0_CONFIG_ODD_ONE_MORE_LINE 0x00020000 | |
861 # define CAP0_CONFIG_EVEN_ONE_MORE_LINE 0x00040000 | |
862 # define CAP0_CONFIG_HORZ_DIVIDE_2 0x00080000 | |
863 # define CAP0_CONFIG_HORZ_DIVIDE_4 0x00100000 | |
864 # define CAP0_CONFIG_VERT_DIVIDE_2 0x00200000 | |
865 # define CAP0_CONFIG_VERT_DIVIDE_4 0x00400000 | |
866 # define CAP0_CONFIG_FORMAT_BROOKTREE 0x00000000 | |
867 # define CAP0_CONFIG_FORMAT_CCIR656 0x00800000 | |
868 # define CAP0_CONFIG_FORMAT_ZV 0x01000000 | |
869 # define CAP0_CONFIG_FORMAT_VIP 0x01800000 | |
870 # define CAP0_CONFIG_FORMAT_TRANSPORT 0x02000000 | |
871 # define CAP0_CONFIG_HORZ_DECIMATOR 0x04000000 | |
872 # define CAP0_CONFIG_VIDEO_IN_YVYU422 0x00000000 | |
873 # define CAP0_CONFIG_VIDEO_IN_VYUY422 0x20000000 | |
874 # define CAP0_CONFIG_VBI_DIVIDE_2 0x40000000 | |
875 # define CAP0_CONFIG_VBI_DIVIDE_4 0x80000000 | |
876 #define CAP0_ANC_ODD_OFFSET 0x095C | |
877 #define CAP0_ANC_EVEN_OFFSET 0x0960 | |
878 #define CAP0_ANC_H_WINDOW 0x0964 | |
879 #define CAP0_VIDEO_SYNC_TEST 0x0968 | |
880 #define CAP0_ONESHOT_BUF_OFFSET 0x096C | |
881 #define CAP0_BUF_STATUS 0x0970 | |
882 #ifdef RAGE128 | |
883 #define CAP0_DWNSC_XRATIO 0x0978 | |
884 #define CAP0_XSHARPNESS 0x097C | |
885 #else | |
886 /* #define CAP0_DWNSC_XRATIO 0x0978 */ | |
887 /* #define CAP0_XSHARPNESS 0x097C */ | |
888 #endif | |
889 #define CAP0_VBI2_OFFSET 0x0980 | |
890 #define CAP0_VBI3_OFFSET 0x0984 | |
891 #define CAP0_ANC2_OFFSET 0x0988 | |
892 #define CAP0_ANC3_OFFSET 0x098C | |
893 | |
894 /* second capture unit */ | |
895 | |
896 #define CAP1_BUF0_OFFSET 0x0990 | |
897 #define CAP1_BUF1_OFFSET 0x0994 | |
898 #define CAP1_BUF0_EVEN_OFFSET 0x0998 | |
899 #define CAP1_BUF1_EVEN_OFFSET 0x099C | |
900 | |
901 #define CAP1_BUF_PITCH 0x09A0 | |
902 #define CAP1_V_WINDOW 0x09A4 | |
903 #define CAP1_H_WINDOW 0x09A8 | |
904 #define CAP1_VBI_ODD_OFFSET 0x09AC | |
905 #define CAP1_VBI_EVEN_OFFSET 0x09B0 | |
906 #define CAP1_VBI_V_WINDOW 0x09B4 | |
907 #define CAP1_VBI_H_WINDOW 0x09B8 | |
908 #define CAP1_PORT_MODE_CNTL 0x09BC | |
909 #define CAP1_TRIG_CNTL 0x09C0 | |
910 #define CAP1_DEBUG 0x09C4 | |
911 #define CAP1_CONFIG 0x09C8 | |
912 #define CAP1_ANC_ODD_OFFSET 0x09CC | |
913 #define CAP1_ANC_EVEN_OFFSET 0x09D0 | |
914 #define CAP1_ANC_H_WINDOW 0x09D4 | |
915 #define CAP1_VIDEO_SYNC_TEST 0x09D8 | |
916 #define CAP1_ONESHOT_BUF_OFFSET 0x09DC | |
917 #define CAP1_BUF_STATUS 0x09E0 | |
918 #define CAP1_DWNSC_XRATIO 0x09E8 | |
919 #define CAP1_XSHARPNESS 0x09EC | |
920 | |
921 #define DISP_MERGE_CNTL 0x0D60 | |
922 #define DISP_OUTPUT_CNTL 0x0D64 | |
923 # define DISP_DAC_SOURCE_MASK 0x03 | |
924 # define DISP_DAC_SOURCE_CRTC2 0x01 | |
925 #define DISP_LIN_TRANS_GRPH_A 0x0D80 | |
926 #define DISP_LIN_TRANS_GRPH_B 0x0D84 | |
927 #define DISP_LIN_TRANS_GRPH_C 0x0D88 | |
928 #define DISP_LIN_TRANS_GRPH_D 0x0D8C | |
929 #define DISP_LIN_TRANS_GRPH_E 0x0D90 | |
930 #define DISP_LIN_TRANS_GRPH_F 0x0D94 | |
931 #define DISP_LIN_TRANS_VID_A 0x0D98 | |
932 #define DISP_LIN_TRANS_VID_B 0x0D9C | |
933 #define DISP_LIN_TRANS_VID_C 0x0DA0 | |
934 #define DISP_LIN_TRANS_VID_D 0x0DA4 | |
935 #define DISP_LIN_TRANS_VID_E 0x0DA8 | |
936 #define DISP_LIN_TRANS_VID_F 0x0DAC | |
937 #define RMX_HORZ_FILTER_0TAP_COEF 0x0DB0 | |
938 #define RMX_HORZ_FILTER_1TAP_COEF 0x0DB4 | |
939 #define RMX_HORZ_FILTER_2TAP_COEF 0x0DB8 | |
940 #define RMX_HORZ_PHASE 0x0DBC | |
941 #define DAC_EMBEDDED_SYNC_CNTL 0x0DC0 | |
942 #define DAC_BROAD_PULSE 0x0DC4 | |
943 #define DAC_SKEW_CLKS 0x0DC8 | |
944 #define DAC_INCR 0x0DCC | |
945 #define DAC_NEG_SYNC_LEVEL 0x0DD0 | |
946 #define DAC_POS_SYNC_LEVEL 0x0DD4 | |
947 #define DAC_BLANK_LEVEL 0x0DD8 | |
948 #define CLOCK_CNTL_INDEX 0x0008 | |
949 /* CLOCK_CNTL_INDEX bit constants */ | |
950 # define PLL_WR_EN 0x00000080 | |
951 # define PLL_DIV_SEL (3 << 8) | |
952 # define PLL2_DIV_SEL_MASK ~(3 << 8) | |
953 #define CLOCK_CNTL_DATA 0x000C | |
954 #define CP_RB_CNTL 0x0704 | |
955 #define CP_RB_BASE 0x0700 | |
956 #define CP_RB_RPTR_ADDR 0x070C | |
957 #define CP_RB_RPTR 0x0710 | |
958 #define CP_RB_WPTR 0x0714 | |
959 #define CP_RB_WPTR_DELAY 0x0718 | |
960 #define CP_IB_BASE 0x0738 | |
961 #define CP_IB_BUFSZ 0x073C | |
962 #define SCRATCH_REG0 0x15E0 | |
963 #define GUI_SCRATCH_REG0 0x15E0 | |
964 #define SCRATCH_REG1 0x15E4 | |
965 #define GUI_SCRATCH_REG1 0x15E4 | |
966 #define SCRATCH_REG2 0x15E8 | |
967 #define GUI_SCRATCH_REG2 0x15E8 | |
968 #define SCRATCH_REG3 0x15EC | |
969 #define GUI_SCRATCH_REG3 0x15EC | |
970 #define SCRATCH_REG4 0x15F0 | |
971 #define GUI_SCRATCH_REG4 0x15F0 | |
972 #define SCRATCH_REG5 0x15F4 | |
973 #define GUI_SCRATCH_REG5 0x15F4 | |
974 #define SCRATCH_UMSK 0x0770 | |
975 #define SCRATCH_ADDR 0x0774 | |
976 #define DP_BRUSH_FRGD_CLR 0x147C | |
977 #define DP_BRUSH_BKGD_CLR 0x1478 | |
978 #define DST_LINE_START 0x1600 | |
979 #define DST_LINE_END 0x1604 | |
980 #define SRC_OFFSET 0x15AC | |
981 #define SRC_PITCH 0x15B0 | |
982 #define SRC_TILE 0x1704 | |
983 #define SRC_PITCH_OFFSET 0x1428 | |
984 #define SRC_X 0x1414 | |
985 #define SRC_Y 0x1418 | |
986 #define DST_WIDTH_X 0x1588 | |
987 #define DST_HEIGHT_WIDTH_8 0x158C | |
988 #define SRC_X_Y 0x1590 | |
989 #define SRC_Y_X 0x1434 | |
990 #define DST_Y_X 0x1438 | |
991 #define DST_WIDTH_HEIGHT 0x1598 | |
992 #define DST_HEIGHT_WIDTH 0x143c | |
993 #define SRC_CLUT_ADDRESS 0x1780 | |
994 #define SRC_CLUT_DATA 0x1784 | |
995 #define SRC_CLUT_DATA_RD 0x1788 | |
996 #define HOST_DATA0 0x17C0 | |
997 #define HOST_DATA1 0x17C4 | |
998 #define HOST_DATA2 0x17C8 | |
999 #define HOST_DATA3 0x17CC | |
1000 #define HOST_DATA4 0x17D0 | |
1001 #define HOST_DATA5 0x17D4 | |
1002 #define HOST_DATA6 0x17D8 | |
1003 #define HOST_DATA7 0x17DC | |
1004 #define HOST_DATA_LAST 0x17E0 | |
1005 #define DP_SRC_ENDIAN 0x15D4 | |
1006 #define DP_SRC_FRGD_CLR 0x15D8 | |
1007 #define DP_SRC_BKGD_CLR 0x15DC | |
1008 #define DP_WRITE_MASK 0x16cc | |
1009 #define SC_LEFT 0x1640 | |
1010 #define SC_RIGHT 0x1644 | |
1011 #define SC_TOP 0x1648 | |
1012 #define SC_BOTTOM 0x164C | |
1013 #define SRC_SC_RIGHT 0x1654 | |
1014 #define SRC_SC_BOTTOM 0x165C | |
1015 #define DP_CNTL 0x16C0 | |
1016 /* DP_CNTL bit constants */ | |
1017 # define DST_X_RIGHT_TO_LEFT 0x00000000 | |
1018 # define DST_X_LEFT_TO_RIGHT 0x00000001 | |
1019 # define DST_Y_BOTTOM_TO_TOP 0x00000000 | |
1020 # define DST_Y_TOP_TO_BOTTOM 0x00000002 | |
1021 # define DST_X_MAJOR 0x00000000 | |
1022 # define DST_Y_MAJOR 0x00000004 | |
1023 # define DST_X_TILE 0x00000008 | |
1024 # define DST_Y_TILE 0x00000010 | |
1025 # define DST_LAST_PEL 0x00000020 | |
1026 # define DST_TRAIL_X_RIGHT_TO_LEFT 0x00000000 | |
1027 # define DST_TRAIL_X_LEFT_TO_RIGHT 0x00000040 | |
1028 # define DST_TRAP_FILL_RIGHT_TO_LEFT 0x00000000 | |
1029 # define DST_TRAP_FILL_LEFT_TO_RIGHT 0x00000080 | |
1030 # define DST_BRES_SIGN 0x00000100 | |
1031 # define DST_HOST_BIG_ENDIAN_EN 0x00000200 | |
1032 # define DST_POLYLINE_NONLAST 0x00008000 | |
1033 # define DST_RASTER_STALL 0x00010000 | |
1034 # define DST_POLY_EDGE 0x00040000 | |
1035 #define DP_CNTL_XDIR_YDIR_YMAJOR 0x16D0 | |
1036 /* DP_CNTL_XDIR_YDIR_YMAJOR bit constants (short version of DP_CNTL) */ | |
1037 # define DST_X_MAJOR_S 0x00000000 | |
1038 # define DST_Y_MAJOR_S 0x00000001 | |
1039 # define DST_Y_BOTTOM_TO_TOP_S 0x00000000 | |
1040 # define DST_Y_TOP_TO_BOTTOM_S 0x00008000 | |
1041 # define DST_X_RIGHT_TO_LEFT_S 0x00000000 | |
1042 # define DST_X_LEFT_TO_RIGHT_S 0x80000000 | |
1043 #define DP_DATATYPE 0x16C4 | |
1044 /* DP_DATATYPE bit constants */ | |
1045 # define DST_8BPP 0x00000002 | |
1046 # define DST_15BPP 0x00000003 | |
1047 # define DST_16BPP 0x00000004 | |
1048 # define DST_24BPP 0x00000005 | |
1049 # define DST_32BPP 0x00000006 | |
1050 # define DST_8BPP_RGB332 0x00000007 | |
1051 # define DST_8BPP_Y8 0x00000008 | |
1052 # define DST_8BPP_RGB8 0x00000009 | |
1053 # define DST_16BPP_VYUY422 0x0000000b | |
1054 # define DST_16BPP_YVYU422 0x0000000c | |
1055 # define DST_32BPP_AYUV444 0x0000000e | |
1056 # define DST_16BPP_ARGB4444 0x0000000f | |
1057 # define BRUSH_SOLIDCOLOR 0x00000d00 | |
1058 # define SRC_MONO 0x00000000 | |
1059 # define SRC_MONO_LBKGD 0x00010000 | |
1060 # define SRC_DSTCOLOR 0x00030000 | |
1061 # define BYTE_ORDER_MSB_TO_LSB 0x00000000 | |
1062 # define BYTE_ORDER_LSB_TO_MSB 0x40000000 | |
1063 # define DP_CONVERSION_TEMP 0x80000000 | |
1064 # define HOST_BIG_ENDIAN_EN (1 << 29) | |
1065 #define DP_MIX 0x16C8 | |
1066 /* DP_MIX bit constants */ | |
1067 # define DP_SRC_RECT 0x00000200 | |
1068 # define DP_SRC_HOST 0x00000300 | |
1069 # define DP_SRC_HOST_BYTEALIGN 0x00000400 | |
1070 #define DP_WRITE_MSK 0x16CC | |
1071 #define DP_XOP 0x17F8 | |
1072 #define CLR_CMP_CLR_SRC 0x15C4 | |
1073 #define CLR_CMP_CLR_DST 0x15C8 | |
1074 #define CLR_CMP_CNTL 0x15C0 | |
1075 /* CLR_CMP_CNTL bit constants */ | |
1076 # define COMPARE_SRC_FALSE 0x00000000 | |
1077 # define COMPARE_SRC_TRUE 0x00000001 | |
1078 # define COMPARE_SRC_NOT_EQUAL 0x00000004 | |
1079 # define COMPARE_SRC_EQUAL 0x00000005 | |
1080 # define COMPARE_SRC_EQUAL_FLIP 0x00000007 | |
1081 # define COMPARE_DST_FALSE 0x00000000 | |
1082 # define COMPARE_DST_TRUE 0x00000100 | |
1083 # define COMPARE_DST_NOT_EQUAL 0x00000400 | |
1084 # define COMPARE_DST_EQUAL 0x00000500 | |
1085 # define COMPARE_DESTINATION 0x00000000 | |
1086 # define COMPARE_SOURCE 0x01000000 | |
1087 # define COMPARE_SRC_AND_DST 0x02000000 | |
1088 #define CLR_CMP_MSK 0x15CC | |
1089 #define DSTCACHE_MODE 0x1710 | |
1090 #define DSTCACHE_CTLSTAT 0x1714 | |
1091 /* DSTCACHE_CTLSTAT bit constants */ | |
1092 # define RB2D_DC_FLUSH (3 << 0) | |
1093 # define RB2D_DC_FLUSH_ALL 0xf | |
1094 # define RB2D_DC_BUSY (1 << 31) | |
1095 #define DEFAULT_OFFSET 0x16e0 | |
1096 #define DEFAULT_PITCH_OFFSET 0x16E0 | |
1097 #define DEFAULT_SC_BOTTOM_RIGHT 0x16E8 | |
1098 /* DEFAULT_SC_BOTTOM_RIGHT bit constants */ | |
1099 # define DEFAULT_SC_RIGHT_MAX (0x1fff << 0) | |
1100 # define DEFAULT_SC_BOTTOM_MAX (0x1fff << 16) | |
1101 #define DP_GUI_MASTER_CNTL 0x146C | |
1102 /* DP_GUI_MASTER_CNTL bit constants */ | |
1103 # define GMC_SRC_PITCH_OFFSET_DEFAULT 0x00000000 | |
1104 # define GMC_SRC_PITCH_OFFSET_LEAVE 0x00000001 | |
1105 # define GMC_DST_PITCH_OFFSET_DEFAULT 0x00000000 | |
1106 # define GMC_DST_PITCH_OFFSET_LEAVE 0x00000002 | |
1107 # define GMC_SRC_CLIP_DEFAULT 0x00000000 | |
1108 # define GMC_SRC_CLIP_LEAVE 0x00000004 | |
1109 # define GMC_DST_CLIP_DEFAULT 0x00000000 | |
1110 # define GMC_DST_CLIP_LEAVE 0x00000008 | |
1111 # define GMC_BRUSH_8x8MONO 0x00000000 | |
1112 # define GMC_BRUSH_8x8MONO_LBKGD 0x00000010 | |
1113 # define GMC_BRUSH_8x1MONO 0x00000020 | |
1114 # define GMC_BRUSH_8x1MONO_LBKGD 0x00000030 | |
1115 # define GMC_BRUSH_1x8MONO 0x00000040 | |
1116 # define GMC_BRUSH_1x8MONO_LBKGD 0x00000050 | |
1117 # define GMC_BRUSH_32x1MONO 0x00000060 | |
1118 # define GMC_BRUSH_32x1MONO_LBKGD 0x00000070 | |
1119 # define GMC_BRUSH_32x32MONO 0x00000080 | |
1120 # define GMC_BRUSH_32x32MONO_LBKGD 0x00000090 | |
1121 # define GMC_BRUSH_8x8COLOR 0x000000a0 | |
1122 # define GMC_BRUSH_8x1COLOR 0x000000b0 | |
1123 # define GMC_BRUSH_1x8COLOR 0x000000c0 | |
1124 # define GMC_BRUSH_SOLID_COLOR 0x000000d0 | |
1125 # define GMC_DST_8BPP 0x00000200 | |
1126 # define GMC_DST_15BPP 0x00000300 | |
1127 # define GMC_DST_16BPP 0x00000400 | |
1128 # define GMC_DST_24BPP 0x00000500 | |
1129 # define GMC_DST_32BPP 0x00000600 | |
1130 # define GMC_DST_8BPP_RGB332 0x00000700 | |
1131 # define GMC_DST_8BPP_Y8 0x00000800 | |
1132 # define GMC_DST_8BPP_RGB8 0x00000900 | |
1133 # define GMC_DST_16BPP_VYUY422 0x00000b00 | |
1134 # define GMC_DST_16BPP_YVYU422 0x00000c00 | |
1135 # define GMC_DST_32BPP_AYUV444 0x00000e00 | |
1136 # define GMC_DST_16BPP_ARGB4444 0x00000f00 | |
1137 # define GMC_SRC_MONO 0x00000000 | |
1138 # define GMC_SRC_MONO_LBKGD 0x00001000 | |
1139 # define GMC_SRC_DSTCOLOR 0x00003000 | |
1140 # define GMC_BYTE_ORDER_MSB_TO_LSB 0x00000000 | |
1141 # define GMC_BYTE_ORDER_LSB_TO_MSB 0x00004000 | |
1142 # define GMC_DP_CONVERSION_TEMP_9300 0x00008000 | |
1143 # define GMC_DP_CONVERSION_TEMP_6500 0x00000000 | |
1144 # define GMC_DP_SRC_RECT 0x02000000 | |
1145 # define GMC_DP_SRC_HOST 0x03000000 | |
1146 # define GMC_DP_SRC_HOST_BYTEALIGN 0x04000000 | |
1147 # define GMC_3D_FCN_EN_CLR 0x00000000 | |
1148 # define GMC_3D_FCN_EN_SET 0x08000000 | |
1149 # define GMC_DST_CLR_CMP_FCN_LEAVE 0x00000000 | |
1150 # define GMC_DST_CLR_CMP_FCN_CLEAR 0x10000000 | |
1151 # define GMC_AUX_CLIP_LEAVE 0x00000000 | |
1152 # define GMC_AUX_CLIP_CLEAR 0x20000000 | |
1153 # define GMC_WRITE_MASK_LEAVE 0x00000000 | |
1154 # define GMC_WRITE_MASK_SET 0x40000000 | |
1155 # define GMC_CLR_CMP_CNTL_DIS (1 << 28) | |
1156 # define GMC_SRC_DATATYPE_COLOR (3 << 12) | |
1157 # define ROP3_S 0x00cc0000 | |
1158 # define ROP3_SRCCOPY 0x00cc0000 | |
1159 # define ROP3_P 0x00f00000 | |
1160 # define ROP3_PATCOPY 0x00f00000 | |
1161 # define DP_SRC_SOURCE_MASK (7 << 24) | |
1162 # define GMC_BRUSH_NONE (15 << 4) | |
1163 # define DP_SRC_SOURCE_MEMORY (2 << 24) | |
1164 # define GMC_BRUSH_SOLIDCOLOR 0x000000d0 | |
1165 #define SC_TOP_LEFT 0x16EC | |
1166 #define SC_BOTTOM_RIGHT 0x16F0 | |
1167 #define SRC_SC_BOTTOM_RIGHT 0x16F4 | |
1168 #define RB2D_DSTCACHE_CTLSTAT 0x342C | |
1169 #define RB2D_DSTCACHE_MODE 0x3428 | |
1170 | |
1171 #define BASE_CODE 0x0f0b | |
1172 #define RADEON_BIOS_0_SCRATCH 0x0010 | |
1173 #define RADEON_BIOS_1_SCRATCH 0x0014 | |
1174 #define RADEON_BIOS_2_SCRATCH 0x0018 | |
1175 #define RADEON_BIOS_3_SCRATCH 0x001c | |
1176 #define RADEON_BIOS_4_SCRATCH 0x0020 | |
1177 #define RADEON_BIOS_5_SCRATCH 0x0024 | |
1178 #define RADEON_BIOS_6_SCRATCH 0x0028 | |
1179 #define RADEON_BIOS_7_SCRATCH 0x002c | |
1180 | |
1181 | |
1182 #define CLK_PIN_CNTL 0x0001 | |
1183 #define PPLL_CNTL 0x0002 | |
1184 # define PPLL_RESET (1 << 0) | |
1185 # define PPLL_SLEEP (1 << 1) | |
1186 # define PPLL_ATOMIC_UPDATE_EN (1 << 16) | |
1187 # define PPLL_VGA_ATOMIC_UPDATE_EN (1 << 17) | |
1188 # define PPLL_ATOMIC_UPDATE_VSYNC (1 << 18) | |
1189 #define PPLL_REF_DIV 0x0003 | |
1190 # define PPLL_REF_DIV_MASK 0x03ff | |
1191 # define PPLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */ | |
1192 # define PPLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */ | |
1193 #define PPLL_DIV_0 0x0004 | |
1194 #define PPLL_DIV_1 0x0005 | |
1195 #define PPLL_DIV_2 0x0006 | |
1196 #define PPLL_DIV_3 0x0007 | |
1197 #define VCLK_ECP_CNTL 0x0008 | |
1198 #define HTOTAL_CNTL 0x0009 | |
1199 #define HTOTAL2_CNTL 0x002e /* PLL */ | |
1200 #define M_SPLL_REF_FB_DIV 0x000a | |
1201 #define AGP_PLL_CNTL 0x000b | |
1202 #define SPLL_CNTL 0x000c | |
1203 #define SCLK_CNTL 0x000d | |
1204 #define MPLL_CNTL 0x000e | |
1205 #define MCLK_CNTL 0x0012 | |
1206 /* MCLK_CNTL bit constants */ | |
1207 # define FORCEON_MCLKA (1 << 16) | |
1208 # define FORCEON_MCLKB (1 << 17) | |
1209 # define FORCEON_YCLKA (1 << 18) | |
1210 # define FORCEON_YCLKB (1 << 19) | |
1211 # define FORCEON_MC (1 << 20) | |
1212 # define FORCEON_AIC (1 << 21) | |
1213 #define PLL_TEST_CNTL 0x0013 | |
1214 #define P2PLL_CNTL 0x002a /* P2PLL */ | |
1215 # define P2PLL_RESET (1 << 0) | |
1216 # define P2PLL_SLEEP (1 << 1) | |
1217 # define P2PLL_ATOMIC_UPDATE_EN (1 << 16) | |
1218 # define P2PLL_VGA_ATOMIC_UPDATE_EN (1 << 17) | |
1219 # define P2PLL_ATOMIC_UPDATE_VSYNC (1 << 18) | |
1220 #define P2PLL_DIV_0 0x002c | |
1221 # define P2PLL_FB0_DIV_MASK 0x07ff | |
1222 # define P2PLL_POST0_DIV_MASK 0x00070000 | |
1223 #define P2PLL_REF_DIV 0x002B /* PLL */ | |
1224 # define P2PLL_REF_DIV_MASK 0x03ff | |
1225 # define P2PLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */ | |
1226 # define P2PLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */ | |
1227 | |
1228 /* masks */ | |
1229 | |
1230 #define CONFIG_MEMSIZE_MASK 0x1f000000 | |
1231 #define MEM_CFG_TYPE 0x40000000 | |
1232 #define DST_OFFSET_MASK 0x003fffff | |
1233 #define DST_PITCH_MASK 0x3fc00000 | |
1234 #define DEFAULT_TILE_MASK 0xc0000000 | |
1235 #define PPLL_DIV_SEL_MASK 0x00000300 | |
1236 #define PPLL_FB3_DIV_MASK 0x000007ff | |
1237 #define PPLL_POST3_DIV_MASK 0x00070000 | |
1238 | |
1239 #define GUI_ACTIVE 0x80000000 | |
1240 | |
1241 /* GEN_RESET_CNTL bit constants */ | |
1242 #define SOFT_RESET_GUI 0x00000001 | |
1243 #define SOFT_RESET_VCLK 0x00000100 | |
1244 #define SOFT_RESET_PCLK 0x00000200 | |
1245 #define SOFT_RESET_ECP 0x00000400 | |
1246 #define SOFT_RESET_DISPENG_XCLK 0x00000800 | |
1247 | |
1248 /* RAGE THEATER REGISTERS */ | |
1249 | |
1250 #define DMA_VIPH0_COMMAND 0x0A00 | |
1251 #define DMA_VIPH1_COMMAND 0x0A04 | |
1252 #define DMA_VIPH2_COMMAND 0x0A08 | |
1253 #define DMA_VIPH3_COMMAND 0x0A0C | |
1254 #define DMA_VIPH_STATUS 0x0A10 | |
1255 #define DMA_VIPH_CHUNK_0 0x0A18 | |
1256 #define DMA_VIPH_CHUNK_1_VAL 0x0A1C | |
1257 #define DMA_VIP0_TABLE_ADDR 0x0A20 | |
1258 #define DMA_VIPH0_ACTIVE 0x0A24 | |
1259 #define DMA_VIP1_TABLE_ADDR 0x0A30 | |
1260 #define DMA_VIPH1_ACTIVE 0x0A34 | |
1261 #define DMA_VIP2_TABLE_ADDR 0x0A40 | |
1262 #define DMA_VIPH2_ACTIVE 0x0A44 | |
1263 #define DMA_VIP3_TABLE_ADDR 0x0A50 | |
1264 #define DMA_VIPH3_ACTIVE 0x0A54 | |
1265 #define DMA_VIPH_ABORT 0x0A88 | |
1266 | |
1267 #define VIPH_CH0_DATA 0x0c00 | |
1268 #define VIPH_CH1_DATA 0x0c04 | |
1269 #define VIPH_CH2_DATA 0x0c08 | |
1270 #define VIPH_CH3_DATA 0x0c0c | |
1271 #define VIPH_CH0_ADDR 0x0c10 | |
1272 #define VIPH_CH1_ADDR 0x0c14 | |
1273 #define VIPH_CH2_ADDR 0x0c18 | |
1274 #define VIPH_CH3_ADDR 0x0c1c | |
1275 #define VIPH_CH0_SBCNT 0x0c20 | |
1276 #define VIPH_CH1_SBCNT 0x0c24 | |
1277 #define VIPH_CH2_SBCNT 0x0c28 | |
1278 #define VIPH_CH3_SBCNT 0x0c2c | |
1279 #define VIPH_CH0_ABCNT 0x0c30 | |
1280 #define VIPH_CH1_ABCNT 0x0c34 | |
1281 #define VIPH_CH2_ABCNT 0x0c38 | |
1282 #define VIPH_CH3_ABCNT 0x0c3c | |
1283 #define VIPH_CONTROL 0x0c40 | |
1284 #define VIPH_DV_LAT 0x0c44 | |
1285 #define VIPH_BM_CHUNK 0x0c48 | |
1286 #define VIPH_DV_INT 0x0c4c | |
1287 #define VIPH_TIMEOUT_STAT 0x0c50 | |
1288 | |
1289 #define VIPH_REG_DATA 0x0084 | |
1290 #define VIPH_REG_ADDR 0x0080 | |
1291 | |
1292 /* Address Space Rage Theatre Registers (VIP Access) */ | |
1293 #define VIP_VIP_VENDOR_DEVICE_ID 0x0000 | |
1294 #define VIP_VIP_SUB_VENDOR_DEVICE_ID 0x0004 | |
1295 #define VIP_VIP_COMMAND_STATUS 0x0008 | |
1296 #define VIP_VIP_REVISION_ID 0x000c | |
1297 #define VIP_HW_DEBUG 0x0010 | |
1298 #define VIP_SW_SCRATCH 0x0014 | |
1299 #define VIP_I2C_CNTL_0 0x0020 | |
1300 #define VIP_I2C_CNTL_1 0x0024 | |
1301 #define VIP_I2C_DATA 0x0028 | |
1302 #define VIP_INT_CNTL 0x002c | |
1303 #define VIP_GPIO_INOUT 0x0030 | |
1304 #define VIP_GPIO_CNTL 0x0034 | |
1305 #define VIP_CLKOUT_GPIO_CNTL 0x0038 | |
1306 #define VIP_RIPINTF_PORT_CNTL 0x003c | |
1307 #define VIP_ADC_CNTL 0x0400 | |
1308 #define VIP_ADC_DEBUG 0x0404 | |
1309 #define VIP_STANDARD_SELECT 0x0408 | |
1310 #define VIP_THERMO2BIN_STATUS 0x040c | |
1311 #define VIP_COMB_CNTL0 0x0440 | |
1312 #define VIP_COMB_CNTL1 0x0444 | |
1313 #define VIP_COMB_CNTL2 0x0448 | |
1314 #define VIP_COMB_LINE_LENGTH 0x044c | |
1315 #define VIP_NOISE_CNTL0 0x0450 | |
1316 #define VIP_HS_PLINE 0x0480 | |
1317 #define VIP_HS_DTOINC 0x0484 | |
1318 #define VIP_HS_PLLGAIN 0x0488 | |
1319 #define VIP_HS_MINMAXWIDTH 0x048c | |
1320 #define VIP_HS_GENLOCKDELAY 0x0490 | |
1321 #define VIP_HS_WINDOW_LIMIT 0x0494 | |
1322 #define VIP_HS_WINDOW_OC_SPEED 0x0498 | |
1323 #define VIP_HS_PULSE_WIDTH 0x049c | |
1324 #define VIP_HS_PLL_ERROR 0x04a0 | |
1325 #define VIP_HS_PLL_FS_PATH 0x04a4 | |
1326 #define VIP_SG_BLACK_GATE 0x04c0 | |
1327 #define VIP_SG_SYNCTIP_GATE 0x04c4 | |
1328 #define VIP_SG_UVGATE_GATE 0x04c8 | |
1329 #define VIP_LP_AGC_CLAMP_CNTL0 0x0500 | |
1330 #define VIP_LP_AGC_CLAMP_CNTL1 0x0504 | |
1331 #define VIP_LP_BRIGHTNESS 0x0508 | |
1332 #define VIP_LP_CONTRAST 0x050c | |
1333 #define VIP_LP_SLICE_LIMIT 0x0510 | |
1334 #define VIP_LP_WPA_CNTL0 0x0514 | |
1335 #define VIP_LP_WPA_CNTL1 0x0518 | |
1336 #define VIP_LP_BLACK_LEVEL 0x051c | |
1337 #define VIP_LP_SLICE_LEVEL 0x0520 | |
1338 #define VIP_LP_SYNCTIP_LEVEL 0x0524 | |
1339 #define VIP_LP_VERT_LOCKOUT 0x0528 | |
1340 #define VIP_VS_DETECTOR_CNTL 0x0540 | |
1341 #define VIP_VS_BLANKING_CNTL 0x0544 | |
1342 #define VIP_VS_FIELD_ID_CNTL 0x0548 | |
1343 #define VIP_VS_COUNTER_CNTL 0x054c | |
1344 #define VIP_VS_FRAME_TOTAL 0x0550 | |
1345 #define VIP_VS_LINE_COUNT 0x0554 | |
1346 #define VIP_CP_PLL_CNTL0 0x0580 | |
1347 #define VIP_CP_PLL_CNTL1 0x0584 | |
1348 #define VIP_CP_HUE_CNTL 0x0588 | |
1349 #define VIP_CP_BURST_GAIN 0x058c | |
1350 #define VIP_CP_AGC_CNTL 0x0590 | |
1351 #define VIP_CP_ACTIVE_GAIN 0x0594 | |
1352 #define VIP_CP_PLL_STATUS0 0x0598 | |
1353 #define VIP_CP_PLL_STATUS1 0x059c | |
1354 #define VIP_CP_PLL_STATUS2 0x05a0 | |
1355 #define VIP_CP_PLL_STATUS3 0x05a4 | |
1356 #define VIP_CP_PLL_STATUS4 0x05a8 | |
1357 #define VIP_CP_PLL_STATUS5 0x05ac | |
1358 #define VIP_CP_PLL_STATUS6 0x05b0 | |
1359 #define VIP_CP_PLL_STATUS7 0x05b4 | |
1360 #define VIP_CP_DEBUG_FORCE 0x05b8 | |
1361 #define VIP_CP_VERT_LOCKOUT 0x05bc | |
1362 #define VIP_H_ACTIVE_WINDOW 0x05c0 | |
1363 #define VIP_V_ACTIVE_WINDOW 0x05c4 | |
1364 #define VIP_H_VBI_WINDOW 0x05c8 | |
1365 #define VIP_V_VBI_WINDOW 0x05cc | |
1366 #define VIP_VBI_CONTROL 0x05d0 | |
1367 #define VIP_DECODER_DEBUG_CNTL 0x05d4 | |
1368 #define VIP_SINGLE_STEP_DATA 0x05d8 | |
1369 #define VIP_MASTER_CNTL 0x0040 | |
1370 #define VIP_RGB_CNTL 0x0048 | |
1371 #define VIP_CLKOUT_CNTL 0x004c | |
1372 #define VIP_SYNC_CNTL 0x0050 | |
1373 #define VIP_I2C_CNTL 0x0054 | |
1374 #define VIP_HTOTAL 0x0080 | |
1375 #define VIP_HDISP 0x0084 | |
1376 #define VIP_HSIZE 0x0088 | |
1377 #define VIP_HSTART 0x008c | |
1378 #define VIP_HCOUNT 0x0090 | |
1379 #define VIP_VTOTAL 0x0094 | |
1380 #define VIP_VDISP 0x0098 | |
1381 #define VIP_VCOUNT 0x009c | |
1382 #define VIP_VFTOTAL 0x00a0 | |
1383 #define VIP_DFCOUNT 0x00a4 | |
1384 #define VIP_DFRESTART 0x00a8 | |
1385 #define VIP_DHRESTART 0x00ac | |
1386 #define VIP_DVRESTART 0x00b0 | |
1387 #define VIP_SYNC_SIZE 0x00b4 | |
1388 #define VIP_TV_PLL_FINE_CNTL 0x00b8 | |
1389 #define VIP_CRT_PLL_FINE_CNTL 0x00bc | |
1390 #define VIP_TV_PLL_CNTL 0x00c0 | |
1391 #define VIP_CRT_PLL_CNTL 0x00c4 | |
1392 #define VIP_PLL_CNTL0 0x00c8 | |
1393 #define VIP_PLL_TEST_CNTL 0x00cc | |
1394 #define VIP_CLOCK_SEL_CNTL 0x00d0 | |
1395 #define VIP_VIN_PLL_CNTL 0x00d4 | |
1396 #define VIP_VIN_PLL_FINE_CNTL 0x00d8 | |
1397 #define VIP_AUD_PLL_CNTL 0x00e0 | |
1398 #define VIP_AUD_PLL_FINE_CNTL 0x00e4 | |
1399 #define VIP_AUD_CLK_DIVIDERS 0x00e8 | |
1400 #define VIP_AUD_DTO_INCREMENTS 0x00ec | |
1401 #define VIP_L54_PLL_CNTL 0x00f0 | |
1402 #define VIP_L54_PLL_FINE_CNTL 0x00f4 | |
1403 #define VIP_L54_DTO_INCREMENTS 0x00f8 | |
1404 #define VIP_PLL_CNTL1 0x00fc | |
1405 #define VIP_FRAME_LOCK_CNTL 0x0100 | |
1406 #define VIP_SYNC_LOCK_CNTL 0x0104 | |
1407 #define VIP_TVO_SYNC_PAT_ACCUM 0x0108 | |
1408 #define VIP_TVO_SYNC_THRESHOLD 0x010c | |
1409 #define VIP_TVO_SYNC_PAT_EXPECT 0x0110 | |
1410 #define VIP_DELAY_ONE_MAP_A 0x0114 | |
1411 #define VIP_DELAY_ONE_MAP_B 0x0118 | |
1412 #define VIP_DELAY_ZERO_MAP_A 0x011c | |
1413 #define VIP_DELAY_ZERO_MAP_B 0x0120 | |
1414 #define VIP_TVO_DATA_DELAY_A 0x0140 | |
1415 #define VIP_TVO_DATA_DELAY_B 0x0144 | |
1416 #define VIP_HOST_READ_DATA 0x0180 | |
1417 #define VIP_HOST_WRITE_DATA 0x0184 | |
1418 #define VIP_HOST_RD_WT_CNTL 0x0188 | |
1419 #define VIP_VSCALER_CNTL1 0x01c0 | |
1420 #define VIP_TIMING_CNTL 0x01c4 | |
1421 #define VIP_VSCALER_CNTL2 0x01c8 | |
1422 #define VIP_Y_FALL_CNTL 0x01cc | |
1423 #define VIP_Y_RISE_CNTL 0x01d0 | |
1424 #define VIP_Y_SAW_TOOTH_CNTL 0x01d4 | |
1425 #define VIP_UPSAMP_AND_GAIN_CNTL 0x01e0 | |
1426 #define VIP_GAIN_LIMIT_SETTINGS 0x01e4 | |
1427 #define VIP_LINEAR_GAIN_SETTINGS 0x01e8 | |
1428 #define VIP_MODULATOR_CNTL1 0x0200 | |
1429 #define VIP_MODULATOR_CNTL2 0x0204 | |
1430 #define VIP_MV_MODE_CNTL 0x0208 | |
1431 #define VIP_MV_STRIPE_CNTL 0x020c | |
1432 #define VIP_MV_LEVEL_CNTL1 0x0210 | |
1433 #define VIP_MV_LEVEL_CNTL2 0x0214 | |
1434 #define VIP_PRE_DAC_MUX_CNTL 0x0240 | |
1435 #define VIP_TV_DAC_CNTL 0x0280 | |
1436 #define VIP_CRC_CNTL 0x02c0 | |
1437 #define VIP_VIDEO_PORT_SIG 0x02c4 | |
1438 #define VIP_VBI_CC_CNTL 0x02c8 | |
1439 #define VIP_VBI_EDS_CNTL 0x02cc | |
1440 #define VIP_VBI_20BIT_CNTL 0x02d0 | |
1441 #define VIP_VBI_DTO_CNTL 0x02d4 | |
1442 #define VIP_VBI_LEVEL_CNTL 0x02d8 | |
1443 #define VIP_UV_ADR 0x0300 | |
1444 #define VIP_MV_STATUS 0x0330 | |
1445 #define VIP_UPSAMP_COEFF0_0 0x0340 | |
1446 #define VIP_UPSAMP_COEFF0_1 0x0344 | |
1447 #define VIP_UPSAMP_COEFF0_2 0x0348 | |
1448 #define VIP_UPSAMP_COEFF1_0 0x034c | |
1449 #define VIP_UPSAMP_COEFF1_1 0x0350 | |
1450 #define VIP_UPSAMP_COEFF1_2 0x0354 | |
1451 #define VIP_UPSAMP_COEFF2_0 0x0358 | |
1452 #define VIP_UPSAMP_COEFF2_1 0x035c | |
1453 #define VIP_UPSAMP_COEFF2_2 0x0360 | |
1454 #define VIP_UPSAMP_COEFF3_0 0x0364 | |
1455 #define VIP_UPSAMP_COEFF3_1 0x0368 | |
1456 #define VIP_UPSAMP_COEFF3_2 0x036c | |
1457 #define VIP_UPSAMP_COEFF4_0 0x0370 | |
1458 #define VIP_UPSAMP_COEFF4_1 0x0374 | |
1459 #define VIP_UPSAMP_COEFF4_2 0x0378 | |
1460 #define VIP_TV_DTO_INCREMENTS 0x0390 | |
1461 #define VIP_CRT_DTO_INCREMENTS 0x0394 | |
1462 #define VIP_VSYNC_DIFF_CNTL 0x03a0 | |
1463 #define VIP_VSYNC_DIFF_LIMITS 0x03a4 | |
1464 #define VIP_VSYNC_DIFF_RD_DATA 0x03a8 | |
1465 #define VIP_SCALER_IN_WINDOW 0x0618 | |
1466 #define VIP_SCALER_OUT_WINDOW 0x061c | |
1467 #define VIP_H_SCALER_CONTROL 0x0600 | |
1468 #define VIP_V_SCALER_CONTROL 0x0604 | |
1469 #define VIP_V_DEINTERLACE_CONTROL 0x0608 | |
1470 #define VIP_VBI_SCALER_CONTROL 0x060c | |
1471 #define VIP_DVS_PORT_CTRL 0x0610 | |
1472 #define VIP_DVS_PORT_READBACK 0x0614 | |
1473 #define VIP_FIFOA_CONFIG 0x0800 | |
1474 #define VIP_FIFOB_CONFIG 0x0804 | |
1475 #define VIP_FIFOC_CONFIG 0x0808 | |
1476 #define VIP_SPDIF_PORT_CNTL 0x080c | |
1477 #define VIP_SPDIF_CHANNEL_STAT 0x0810 | |
1478 #define VIP_SPDIF_AC3_PREAMBLE 0x0814 | |
1479 #define VIP_I2S_TRANSMIT_CNTL 0x0818 | |
1480 #define VIP_I2S_RECEIVE_CNTL 0x081c | |
1481 #define VIP_SPDIF_TX_CNT_REG 0x0820 | |
1482 #define VIP_IIS_TX_CNT_REG 0x0824 | |
1483 | |
1484 /* Status defines */ | |
1485 #define VIP_BUSY 0 | |
1486 #define VIP_IDLE 1 | |
1487 #define VIP_RESET 2 | |
1488 | |
1489 #define VIPH_TIMEOUT_STAT__VIPH_REG_STAT 0x00000010 | |
1490 #define VIPH_TIMEOUT_STAT__VIPH_REG_AK 0x00000010 | |
1491 #define VIPH_TIMEOUT_STAT__VIPH_REGR_DIS 0x01000000 | |
1492 #define TEST_DEBUG_CNTL__TEST_DEBUG_OUT_EN 0x00000001 | |
1493 | |
1494 #define RT_ATI_ID 0x4D541002 | |
1495 | |
1496 /* Register/Field values: */ | |
1497 #define RT_COMP0 0x0 | |
1498 #define RT_COMP1 0x1 | |
1499 #define RT_COMP2 0x2 | |
1500 #define RT_YF_COMP3 0x3 | |
1501 #define RT_YR_COMP3 0x4 | |
1502 #define RT_YCF_COMP4 0x5 | |
1503 #define RT_YCR_COMP4 0x6 | |
1504 | |
1505 /* Video standard defines */ | |
1506 #define RT_NTSC 0x0 | |
1507 #define RT_PAL 0x1 | |
1508 #define RT_SECAM 0x2 | |
1509 #define extNONE 0x0000 | |
1510 #define extNTSC 0x0100 | |
1511 #define extRsvd 0x0200 | |
1512 #define extPAL 0x0300 | |
1513 #define extPAL_M 0x0400 | |
1514 #define extPAL_N 0x0500 | |
1515 #define extSECAM 0x0600 | |
1516 #define extPAL_NCOMB 0x0700 | |
1517 #define extNTSC_J 0x0800 | |
1518 #define extNTSC_443 0x0900 | |
1519 #define extPAL_BGHI 0x0A00 | |
1520 #define extPAL_60 0x0B00 | |
1521 /* these are used in MSP3430 */ | |
1522 #define extPAL_DK1 0x0C00 | |
1523 #define extPAL_AUTO 0x0D00 | |
1524 | |
1525 #define RT_FREF_2700 6 | |
1526 #define RT_FREF_2950 5 | |
1527 | |
1528 #define RT_COMPOSITE 0x0 | |
1529 #define RT_SVIDEO 0x1 | |
1530 | |
1531 #define RT_NORM_SHARPNESS 0x03 | |
1532 #define RT_HIGH_SHARPNESS 0x0F | |
1533 | |
1534 #define RT_HUE_PAL_DEF 0x00 | |
1535 | |
1536 #define RT_DECINTERLACED 0x1 | |
1537 #define RT_DECNONINTERLACED 0x0 | |
1538 | |
1539 #define NTSC_LINES 525 | |
1540 #define PAL_SECAM_LINES 625 | |
1541 | |
1542 #define RT_ASYNC_ENABLE 0x0 | |
1543 #define RT_ASYNC_DISABLE 0x1 | |
1544 #define RT_ASYNC_RESET 0x1 | |
1545 | |
1546 #define RT_VINRST_ACTIVE 0x0 | |
1547 #define RT_VINRST_RESET 0x1 | |
1548 #define RT_L54RST_RESET 0x1 | |
1549 | |
1550 #define RT_REF_CLK 0x0 | |
1551 #define RT_PLL_VIN_CLK 0x1 | |
1552 | |
1553 #define RT_VIN_ASYNC_RST 0x20 | |
1554 #define RT_DVS_ASYNC_RST 0x80 | |
1555 | |
1556 #define RT_ADC_ENABLE 0x0 | |
1557 #define RT_ADC_DISABLE 0x1 | |
1558 | |
1559 #define RT_DVSDIR_IN 0x0 | |
1560 #define RT_DVSDIR_OUT 0x1 | |
1561 | |
1562 #define RT_DVSCLK_HIGH 0x0 | |
1563 #define RT_DVSCLK_LOW 0x1 | |
1564 | |
1565 #define RT_DVSCLK_SEL_8FS 0x0 | |
1566 #define RT_DVSCLK_SEL_27MHZ 0x1 | |
1567 | |
1568 #define RT_DVS_CONTSTREAM 0x1 | |
1569 #define RT_DVS_NONCONTSTREAM 0x0 | |
1570 | |
1571 #define RT_DVSDAT_HIGH 0x0 | |
1572 #define RT_DVSDAT_LOW 0x1 | |
1573 | |
1574 #define RT_ADC_CNTL_DEFAULT 0x03252338 | |
1575 | |
1576 /* COMB_CNTL0 FILTER SETTINGS FOR DIFFERENT STANDARDS: */ | |
1577 #define RT_NTSCM_COMB_CNTL0_COMPOSITE 0x09438090 | |
1578 #define RT_NTSCM_COMB_CNTL0_SVIDEO 0x48540000 | |
1579 | |
1580 #define RT_PAL_COMB_CNTL0_COMPOSITE 0x09438090 | |
1581 #define RT_PAL_COMB_CNTL0_SVIDEO 0x40348090 | |
1582 | |
1583 #define RT_SECAM_COMB_CNTL0_COMPOSITE 0xD0108090 /* instead of orig 0xD0088090 - eric*/ | |
1584 #define RT_SECAM_COMB_CNTL0_SVIDEO 0x50148090 | |
1585 | |
1586 #define RT_PALN_COMB_CNTL0_COMPOSITE 0x09438090 | |
1587 #define RT_PALN_COMB_CNTL0_SVIDEO 0x40348090 | |
1588 | |
1589 #define RT_PALM_COMB_CNTL0_COMPOSITE 0x09438090 | |
1590 #define RT_PALM_COMB_CNTL0_SVIDEO 0x40348090 | |
1591 /* End of filter settings. */ | |
1592 | |
1593 /* COMB_CNTL1 FILTER SETTINGS FOR DIFFERENT STANDARDS: */ | |
1594 #define RT_NTSCM_COMB_CNTL1_COMPOSITE 0x00000010 | |
1595 #define RT_NTSCM_COMB_CNTL1_SVIDEO 0x00000081 | |
1596 | |
1597 #define RT_PAL_COMB_CNTL1_COMPOSITE 0x00000010 | |
1598 #define RT_PAL_COMB_CNTL1_SVIDEO 0x000000A1 | |
1599 | |
1600 #define RT_SECAM_COMB_CNTL1_COMPOSITE 0x00000091 | |
1601 #define RT_SECAM_COMB_CNTL1_SVIDEO 0x00000081 | |
1602 | |
1603 #define RT_PALN_COMB_CNTL1_COMPOSITE 0x00000010 | |
1604 #define RT_PALN_COMB_CNTL1_SVIDEO 0x000000A1 | |
1605 | |
1606 #define RT_PALM_COMB_CNTL1_COMPOSITE 0x00000010 | |
1607 #define RT_PALM_COMB_CNTL1_SVIDEO 0x000000A1 | |
1608 /* End of filter settings. */ | |
1609 | |
1610 /* COMB_CNTL2 FILTER SETTINGS FOR DIFFERENT STANDARDS: */ | |
1611 #define RT_NTSCM_COMB_CNTL2_COMPOSITE 0x16161010 | |
1612 #define RT_NTSCM_COMB_CNTL2_SVIDEO 0xFFFFFFFF | |
1613 | |
1614 #define RT_PAL_COMB_CNTL2_COMPOSITE 0x06080102 /* instead of 0x16161010 - Ivo */ | |
1615 #define RT_PAL_COMB_CNTL2_SVIDEO 0x06080102 | |
1616 | |
1617 #define RT_SECAM_COMB_CNTL2_COMPOSITE 0xffffffff /* instead of 0x06080102 - eric */ | |
1618 #define RT_SECAM_COMB_CNTL2_SVIDEO 0x06080102 | |
1619 | |
1620 #define RT_PALN_COMB_CNTL2_COMPOSITE 0x06080102 | |
1621 #define RT_PALN_COMB_CNTL2_SVIDEO 0x06080102 | |
1622 | |
1623 #define RT_PALM_COMB_CNTL2_COMPOSITE 0x06080102 | |
1624 #define RT_PALM_COMB_CNTL2_SVIDEO 0x06080102 | |
1625 /* End of filter settings. */ | |
1626 | |
1627 /* COMB_LINE_LENGTH FILTER SETTINGS FOR DIFFERENT STANDARDS: */ | |
1628 #define RT_NTSCM_COMB_LENGTH_COMPOSITE 0x0718038A | |
1629 #define RT_NTSCM_COMB_LENGTH_SVIDEO 0x0718038A | |
1630 | |
1631 #define RT_PAL_COMB_LENGTH_COMPOSITE 0x08DA046B | |
1632 #define RT_PAL_COMB_LENGTH_SVIDEO 0x08DA046B | |
1633 | |
1634 #define RT_SECAM_COMB_LENGTH_COMPOSITE 0x08DA046A | |
1635 #define RT_SECAM_COMB_LENGTH_SVIDEO 0x08DA046A | |
1636 | |
1637 #define RT_PALN_COMB_LENGTH_COMPOSITE 0x07260391 | |
1638 #define RT_PALN_COMB_LENGTH_SVIDEO 0x07260391 | |
1639 | |
1640 #define RT_PALM_COMB_LENGTH_COMPOSITE 0x07160389 | |
1641 #define RT_PALM_COMB_LENGTH_SVIDEO 0x07160389 | |
1642 /* End of filter settings. */ | |
1643 | |
1644 /* LP_AGC_CLAMP_CNTL0 */ | |
1645 #define RT_NTSCM_SYNCTIP_REF0 0x00000037 | |
1646 #define RT_NTSCM_SYNCTIP_REF1 0x00000029 | |
1647 #define RT_NTSCM_CLAMP_REF 0x0000003B | |
1648 #define RT_NTSCM_PEAKWHITE 0x000000FF | |
1649 #define RT_NTSCM_VBI_PEAKWHITE 0x000000C2 | |
1650 | |
1651 #define RT_NTSCM_WPA_THRESHOLD 0x00000406 | |
1652 #define RT_NTSCM_WPA_TRIGGER_LO 0x000000B3 | |
1653 | |
1654 #define RT_NTSCM_WPA_TRIGGER_HIGH 0x0000021B | |
1655 | |
1656 #define RT_NTSCM_LP_LOCKOUT_START 0x00000206 | |
1657 #define RT_NTSCM_LP_LOCKOUT_END 0x00000021 | |
1658 #define RT_NTSCM_CH_DTO_INC 0x00400000 | |
1659 #define RT_NTSCM_CH_PLL_SGAIN 0x00000001 | |
1660 #define RT_NTSCM_CH_PLL_FGAIN 0x00000002 | |
1661 | |
1662 #define RT_NTSCM_CR_BURST_GAIN 0x0000007A | |
1663 #define RT_NTSCM_CB_BURST_GAIN 0x000000AC | |
1664 | |
1665 #define RT_NTSCM_CH_HEIGHT 0x000000CD | |
1666 #define RT_NTSCM_CH_KILL_LEVEL 0x000000C0 | |
1667 #define RT_NTSCM_CH_AGC_ERROR_LIM 0x00000002 | |
1668 #define RT_NTSCM_CH_AGC_FILTER_EN 0x00000000 | |
1669 #define RT_NTSCM_CH_AGC_LOOP_SPEED 0x00000000 | |
1670 | |
1671 #define RT_NTSCM_CRDR_ACTIVE_GAIN 0x0000007A | |
1672 #define RT_NTSCM_CBDB_ACTIVE_GAIN 0x000000AC | |
1673 | |
1674 #define RT_NTSCM_VERT_LOCKOUT_START 0x00000207 | |
1675 #define RT_NTSCM_VERT_LOCKOUT_END 0x0000000E | |
1676 | |
1677 #define RT_NTSCJ_SYNCTIP_REF0 0x00000004 | |
1678 #define RT_NTSCJ_SYNCTIP_REF1 0x00000012 | |
1679 #define RT_NTSCJ_CLAMP_REF 0x0000003B | |
1680 #define RT_NTSCJ_PEAKWHITE 0x000000CB | |
1681 #define RT_NTSCJ_VBI_PEAKWHITE 0x000000C2 | |
1682 #define RT_NTSCJ_WPA_THRESHOLD 0x000004B0 | |
1683 #define RT_NTSCJ_WPA_TRIGGER_LO 0x000000B4 | |
1684 #define RT_NTSCJ_WPA_TRIGGER_HIGH 0x0000021C | |
1685 #define RT_NTSCJ_LP_LOCKOUT_START 0x00000206 | |
1686 #define RT_NTSCJ_LP_LOCKOUT_END 0x00000021 | |
1687 | |
1688 #define RT_NTSCJ_CR_BURST_GAIN 0x00000071 | |
1689 #define RT_NTSCJ_CB_BURST_GAIN 0x0000009F | |
1690 #define RT_NTSCJ_CH_HEIGHT 0x000000CD | |
1691 #define RT_NTSCJ_CH_KILL_LEVEL 0x000000C0 | |
1692 #define RT_NTSCJ_CH_AGC_ERROR_LIM 0x00000002 | |
1693 #define RT_NTSCJ_CH_AGC_FILTER_EN 0x00000000 | |
1694 #define RT_NTSCJ_CH_AGC_LOOP_SPEED 0x00000000 | |
1695 | |
1696 #define RT_NTSCJ_CRDR_ACTIVE_GAIN 0x00000071 | |
1697 #define RT_NTSCJ_CBDB_ACTIVE_GAIN 0x0000009F | |
1698 #define RT_NTSCJ_VERT_LOCKOUT_START 0x00000207 | |
1699 #define RT_NTSCJ_VERT_LOCKOUT_END 0x0000000E | |
1700 | |
1701 #define RT_PAL_SYNCTIP_REF0 0x37 /* instead of 0x00000004 - Ivo */ | |
1702 #define RT_PAL_SYNCTIP_REF1 0x26 /* instead of 0x0000000F - Ivo */ | |
1703 #define RT_PAL_CLAMP_REF 0x0000003B | |
1704 #define RT_PAL_PEAKWHITE 0xFF /* instead of 0x000000C1 - Ivo */ | |
1705 #define RT_PAL_VBI_PEAKWHITE 0xC6 /* instead of 0x000000C7 - Ivo */ | |
1706 #define RT_PAL_WPA_THRESHOLD 0x59C /* instead of 0x000006A4 - Ivo */ | |
1707 | |
1708 #define RT_PAL_WPA_TRIGGER_LO 0x00000096 | |
1709 #define RT_PAL_WPA_TRIGGER_HIGH 0x000001C2 | |
1710 #define RT_PAL_LP_LOCKOUT_START 0x00000263 | |
1711 #define RT_PAL_LP_LOCKOUT_END 0x0000002C | |
1712 | |
1713 #define RT_PAL_CH_DTO_INC 0x00400000 | |
1714 #define RT_PAL_CH_PLL_SGAIN 1 /* instead of 0x00000002 - Ivo */ | |
1715 #define RT_PAL_CH_PLL_FGAIN 2 /* instead of 0x00000001 - Ivo */ | |
1716 #define RT_PAL_CR_BURST_GAIN 0x0000007A | |
1717 #define RT_PAL_CB_BURST_GAIN 0x000000AB | |
1718 #define RT_PAL_CH_HEIGHT 0x0000009C | |
1719 #define RT_PAL_CH_KILL_LEVEL 4 /* instead of 0x00000090 - Ivo */ | |
1720 #define RT_PAL_CH_AGC_ERROR_LIM 1 /* instead of 0x00000002 - Ivo */ | |
1721 #define RT_PAL_CH_AGC_FILTER_EN 1 /* instead of 0x00000000 - Ivo */ | |
1722 #define RT_PAL_CH_AGC_LOOP_SPEED 0x00000000 | |
1723 | |
1724 #define RT_PAL_CRDR_ACTIVE_GAIN 0x9E /* instead of 0x0000007A - Ivo */ | |
1725 #define RT_PAL_CBDB_ACTIVE_GAIN 0xDF /* instead of 0x000000AB - Ivo */ | |
1726 #define RT_PAL_VERT_LOCKOUT_START 0x00000269 | |
1727 #define RT_PAL_VERT_LOCKOUT_END 0x00000012 | |
1728 | |
1729 #define RT_SECAM_SYNCTIP_REF0 0x37 /* instead of 0x00000004 - Ivo */ | |
1730 #define RT_SECAM_SYNCTIP_REF1 0x26 /* instead of 0x0000000F - Ivo */ | |
1731 #define RT_SECAM_CLAMP_REF 0x0000003B | |
1732 #define RT_SECAM_PEAKWHITE 0xFF /* instead of 0x000000C1 - Ivo */ | |
1733 #define RT_SECAM_VBI_PEAKWHITE 0xC6 /* instead of 0x000000C7 - Ivo */ | |
1734 #define RT_SECAM_WPA_THRESHOLD 0x57A /* instead of 0x6A4, instead of 0x0000059C is Ivo's value , -eric*/ | |
1735 | |
1736 #define RT_SECAM_WPA_TRIGGER_LO 0x96 /* instead of 0x0000026B - eric */ | |
1737 #define RT_SECAM_WPA_TRIGGER_HIGH 0x000001C2 | |
1738 #define RT_SECAM_LP_LOCKOUT_START 0x263 /* instead of 0x0000026B - eric */ | |
1739 #define RT_SECAM_LP_LOCKOUT_END 0x2b /* instead of 0x0000002C -eric */ | |
1740 | |
1741 #define RT_SECAM_CH_DTO_INC 0x003E7A28 | |
1742 #define RT_SECAM_CH_PLL_SGAIN 0x4 /* instead of 0x00000006 -Volodya */ | |
1743 #define RT_SECAM_CH_PLL_FGAIN 0x7 /* instead of 0x00000006 -Volodya */ | |
1744 | |
1745 #define RT_SECAM_CR_BURST_GAIN 0x1FF /* instead of 0x00000200 -Volodya */ | |
1746 #define RT_SECAM_CB_BURST_GAIN 0x1FF /* instead of 0x00000200 -Volodya */ | |
1747 #define RT_SECAM_CH_HEIGHT 0x00000066 | |
1748 #define RT_SECAM_CH_KILL_LEVEL 0x00000060 | |
1749 #define RT_SECAM_CH_AGC_ERROR_LIM 0x00000003 | |
1750 #define RT_SECAM_CH_AGC_FILTER_EN 0x00000000 | |
1751 #define RT_SECAM_CH_AGC_LOOP_SPEED 0x00000000 | |
1752 | |
1753 #define RT_SECAM_CRDR_ACTIVE_GAIN 0x11B /* instead of 0x00000200 - eric */ | |
1754 #define RT_SECAM_CBDB_ACTIVE_GAIN 0x15A /* instead of 0x00000200 - eric */ | |
1755 #define RT_SECAM_VERT_LOCKOUT_START 0x00000269 | |
1756 #define RT_SECAM_VERT_LOCKOUT_END 0x00000012 | |
1757 | |
1758 #define RT_PAL_VS_FIELD_BLANK_END 0x2A /* instead of 0x0000002C - Ivo*/ | |
1759 #define RT_NTSCM_VS_FIELD_BLANK_END 0x0000000A | |
1760 | |
1761 #define RT_NTSCM_FIELD_IDLOCATION 0x00000105 | |
1762 #define RT_PAL_FIELD_IDLOCATION 0x00000137 | |
1763 | |
1764 #define RT_NTSCM_H_ACTIVE_START 0x00000070 | |
1765 #define RT_NTSCM_H_ACTIVE_END 0x00000363 | |
1766 | |
1767 #define RT_PAL_H_ACTIVE_START 0x0000009A | |
1768 #define RT_PAL_H_ACTIVE_END 0x00000439 | |
1769 | |
1770 #define RT_NTSCM_V_ACTIVE_START ((22-4)*2+1) | |
1771 #define RT_NTSCM_V_ACTIVE_END ((22+240-4)*2+1) | |
1772 | |
1773 #define RT_PAL_V_ACTIVE_START 0x2E /* instead of 0x00000023 (Same as SECAM) - Ivo */ | |
1774 #define RT_PAL_V_ACTIVE_END 0x269 /* instead of 0x00000262 - Ivo */ | |
1775 | |
1776 /* VBI */ | |
1777 #define RT_NTSCM_H_VBI_WIND_START 0x00000049 | |
1778 #define RT_NTSCM_H_VBI_WIND_END 0x00000366 | |
1779 | |
1780 #define RT_PAL_H_VBI_WIND_START 0x00000084 | |
1781 #define RT_PAL_H_VBI_WIND_END 0x0000041F | |
1782 | |
1783 #define RT_NTSCM_V_VBI_WIND_START fld_V_VBI_WIND_START_def | |
1784 #define RT_NTSCM_V_VBI_WIND_END fld_V_VBI_WIND_END_def | |
1785 | |
1786 #define RT_PAL_V_VBI_WIND_START 0x8 /* instead of 0x0000000B - Ivo */ | |
1787 #define RT_PAL_V_VBI_WIND_END 0x2D /* instead of 0x00000022 - Ivo */ | |
1788 | |
1789 #define RT_VBI_CAPTURE_EN 0x00000001 /* Enable */ | |
1790 #define RT_VBI_CAPTURE_DIS 0x00000000 /* Disable */ | |
1791 #define RT_RAW_CAPTURE 0x00000002 /* Use raw Video Capture. */ | |
1792 | |
1793 #define RT_NTSCM_VSYNC_INT_TRIGGER 0x2AA | |
1794 #define RT_PALSEM_VSYNC_INT_TRIGGER 0x353 | |
1795 | |
1796 #define RT_NTSCM_VSYNC_INT_HOLD 0x17 | |
1797 #define RT_PALSEM_VSYNC_INT_HOLD 0x1C | |
1798 | |
1799 #define RT_NTSCM_VS_FIELD_BLANK_START 0x206 | |
1800 #define RT_PALSEM_VS_FIELD_BLANK_START 0x26D /* instead of 0x26C - Ivo */ | |
1801 | |
1802 #define RT_FIELD_FLIP_EN 0x4 | |
1803 #define RT_V_FIELD_FLIP_INVERTED 0x2000 | |
1804 | |
1805 #define RT_NTSCM_H_IN_START 0x70 | |
1806 #define RT_PAL_H_IN_START 154 /* instead of 144 - Ivo */ | |
1807 #define RT_SECAM_H_IN_START 0x91 /* instead of 0x9A, Ivo value is 154, instead of 144 - Volodya, - eric */ | |
1808 #define RT_NTSC_H_ACTIVE_SIZE 744 | |
1809 #define RT_PAL_H_ACTIVE_SIZE 928 /* instead of 927 - Ivo */ | |
1810 #define RT_SECAM_H_ACTIVE_SIZE 932 /* instead of 928, instead of 927 - Ivo, - eric */ | |
1811 #define RT_NTSCM_V_IN_START (0x23) | |
1812 #define RT_PAL_V_IN_START 44 /* instead of (45-6) - Ivo */ | |
1813 #define RT_SECAM_V_IN_START 0x2C /* instead of (45-6) - Volodya */ | |
1814 #define RT_NTSCM_V_ACTIVE_SIZE 480 | |
1815 #define RT_PAL_V_ACTIVE_SIZE 572 /* instead of 575 - Ivo */ | |
1816 #define RT_SECAM_V_ACTIVE_SIZE 570 /* instead of 572, instead of 575 - Ivo, - eric */ | |
1817 | |
1818 #define RT_NTSCM_WIN_CLOSE_LIMIT 0x4D | |
1819 #define RT_NTSCJ_WIN_CLOSE_LIMIT 0x4D | |
1820 #define RT_NTSC443_WIN_CLOSE_LIMIT 0x5F | |
1821 #define RT_PALM_WIN_CLOSE_LIMIT 0x4D | |
1822 #define RT_PALN_WIN_CLOSE_LIMIT 0x5F | |
1823 #define RT_SECAM_WIN_CLOSE_LIMIT 0xC7 /* instead of 0x5F - eric */ | |
1824 | |
1825 #define RT_NTSCM_VS_FIELD_BLANK_START 0x206 | |
1826 | |
1827 #define RT_NTSCM_HS_PLL_SGAIN 0x5 | |
1828 #define RT_NTSCM_HS_PLL_FGAIN 0x7 | |
1829 | |
1830 #define RT_NTSCM_H_OUT_WIND_WIDTH 0x2F4 | |
1831 #define RT_NTSCM_V_OUT_WIND_HEIGHT 0xF0 | |
1832 | |
1833 #define TV 0x1 | |
1834 #define LINEIN 0x2 | |
1835 #define MUTE 0x3 | |
1836 | |
1837 #define DEC_COMPOSITE 0 | |
1838 #define DEC_SVIDEO 1 | |
1839 #define DEC_TUNER 2 | |
1840 | |
1841 #define DEC_NTSC 0 | |
1842 #define DEC_PAL 1 | |
1843 #define DEC_SECAM 2 | |
1844 #define DEC_NTSC_J 8 | |
1845 | |
1846 #define DEC_SMOOTH 0 | |
1847 #define DEC_SHARP 1 | |
1848 | |
1849 /* RT Register Field Defaults: */ | |
1850 #define fld_tmpReg1_def 0x00000000 | |
1851 #define fld_tmpReg2_def 0x00000001 | |
1852 #define fld_tmpReg3_def 0x00000002 | |
1853 | |
1854 #define fld_LP_CONTRAST_def 0x0000006e | |
1855 #define fld_LP_BRIGHTNESS_def 0x00003ff0 | |
1856 #define fld_CP_HUE_CNTL_def 0x00000000 | |
1857 #define fld_LUMA_FILTER_def 0x00000001 | |
1858 #define fld_H_SCALE_RATIO_def 0x00010000 | |
1859 #define fld_H_SHARPNESS_def 0x00000000 | |
1860 | |
1861 #define fld_V_SCALE_RATIO_def 0x00000800 | |
1862 #define fld_V_DEINTERLACE_ON_def 0x00000001 | |
1863 #define fld_V_BYPSS_def 0x00000000 | |
1864 #define fld_V_DITHER_ON_def 0x00000001 | |
1865 #define fld_EVENF_OFFSET_def 0x00000000 | |
1866 #define fld_ODDF_OFFSET_def 0x00000000 | |
1867 | |
1868 #define fld_INTERLACE_DETECTED_def 0x00000000 | |
1869 | |
1870 #define fld_VS_LINE_COUNT_def 0x00000000 | |
1871 #define fld_VS_DETECTED_LINES_def 0x00000000 | |
1872 #define fld_VS_ITU656_VB_def 0x00000000 | |
1873 | |
1874 #define fld_VBI_CC_DATA_def 0x00000000 | |
1875 #define fld_VBI_CC_WT_def 0x00000000 | |
1876 #define fld_VBI_CC_WT_ACK_def 0x00000000 | |
1877 #define fld_VBI_CC_HOLD_def 0x00000000 | |
1878 #define fld_VBI_DECODE_EN_def 0x00000000 | |
1879 | |
1880 #define fld_VBI_CC_DTO_P_def 0x00001802 | |
1881 #define fld_VBI_20BIT_DTO_P_def 0x0000155c | |
1882 | |
1883 #define fld_VBI_CC_LEVEL_def 0x0000003f | |
1884 #define fld_VBI_20BIT_LEVEL_def 0x00000059 | |
1885 #define fld_VBI_CLK_RUNIN_GAIN_def 0x0000010f | |
1886 | |
1887 #define fld_H_VBI_WIND_START_def 0x00000041 | |
1888 #define fld_H_VBI_WIND_END_def 0x00000366 | |
1889 | |
1890 #define fld_V_VBI_WIND_START_def 0x0D | |
1891 #define fld_V_VBI_WIND_END_def 0x24 | |
1892 | |
1893 #define fld_VBI_20BIT_DATA0_def 0x00000000 | |
1894 #define fld_VBI_20BIT_DATA1_def 0x00000000 | |
1895 #define fld_VBI_20BIT_WT_def 0x00000000 | |
1896 #define fld_VBI_20BIT_WT_ACK_def 0x00000000 | |
1897 #define fld_VBI_20BIT_HOLD_def 0x00000000 | |
1898 | |
1899 #define fld_VBI_CAPTURE_ENABLE_def 0x00000000 | |
1900 | |
1901 #define fld_VBI_EDS_DATA_def 0x00000000 | |
1902 #define fld_VBI_EDS_WT_def 0x00000000 | |
1903 #define fld_VBI_EDS_WT_ACK_def 0x00000000 | |
1904 #define fld_VBI_EDS_HOLD_def 0x00000000 | |
1905 | |
1906 #define fld_VBI_SCALING_RATIO_def 0x00010000 | |
1907 #define fld_VBI_ALIGNER_ENABLE_def 0x00000000 | |
1908 | |
1909 #define fld_H_ACTIVE_START_def 0x00000070 | |
1910 #define fld_H_ACTIVE_END_def 0x000002f0 | |
1911 | |
1912 #define fld_V_ACTIVE_START_def ((22-4)*2+1) | |
1913 #define fld_V_ACTIVE_END_def ((22+240-4)*2+2) | |
1914 | |
1915 #define fld_CH_HEIGHT_def 0x000000CD | |
1916 #define fld_CH_KILL_LEVEL_def 0x000000C0 | |
1917 #define fld_CH_AGC_ERROR_LIM_def 0x00000002 | |
1918 #define fld_CH_AGC_FILTER_EN_def 0x00000000 | |
1919 #define fld_CH_AGC_LOOP_SPEED_def 0x00000000 | |
1920 | |
1921 #define fld_HUE_ADJ_def 0x00000000 | |
1922 | |
1923 #define fld_STANDARD_SEL_def 0x00000000 | |
1924 #define fld_STANDARD_YC_def 0x00000000 | |
1925 | |
1926 #define fld_ADC_PDWN_def 0x00000001 | |
1927 #define fld_INPUT_SELECT_def 0x00000000 | |
1928 | |
1929 #define fld_ADC_PREFLO_def 0x00000003 | |
1930 #define fld_H_SYNC_PULSE_WIDTH_def 0x00000000 | |
1931 #define fld_HS_GENLOCKED_def 0x00000000 | |
1932 #define fld_HS_SYNC_IN_WIN_def 0x00000000 | |
1933 | |
1934 #define fld_VIN_ASYNC_RST_def 0x00000001 | |
1935 #define fld_DVS_ASYNC_RST_def 0x00000001 | |
1936 | |
1937 /* Vendor IDs: */ | |
1938 #define fld_VIP_VENDOR_ID_def 0x00001002 | |
1939 #define fld_VIP_DEVICE_ID_def 0x00004d54 | |
1940 #define fld_VIP_REVISION_ID_def 0x00000001 | |
1941 | |
1942 /* AGC Delay Register */ | |
1943 #define fld_BLACK_INT_START_def 0x00000031 | |
1944 #define fld_BLACK_INT_LENGTH_def 0x0000000f | |
1945 | |
1946 #define fld_UV_INT_START_def 0x0000003b | |
1947 #define fld_U_INT_LENGTH_def 0x0000000f | |
1948 #define fld_V_INT_LENGTH_def 0x0000000f | |
1949 #define fld_CRDR_ACTIVE_GAIN_def 0x0000007a | |
1950 #define fld_CBDB_ACTIVE_GAIN_def 0x000000ac | |
1951 | |
1952 #define fld_DVS_DIRECTION_def 0x00000000 | |
1953 #define fld_DVS_VBI_CARD8_SWAP_def 0x00000000 | |
1954 #define fld_DVS_CLK_SELECT_def 0x00000000 | |
1955 #define fld_CONTINUOUS_STREAM_def 0x00000000 | |
1956 #define fld_DVSOUT_CLK_DRV_def 0x00000001 | |
1957 #define fld_DVSOUT_DATA_DRV_def 0x00000001 | |
1958 | |
1959 #define fld_COMB_CNTL0_def 0x09438090 | |
1960 #define fld_COMB_CNTL1_def 0x00000010 | |
1961 | |
1962 #define fld_COMB_CNTL2_def 0x16161010 | |
1963 #define fld_COMB_LENGTH_def 0x0718038A | |
1964 | |
1965 #define fld_SYNCTIP_REF0_def 0x00000037 | |
1966 #define fld_SYNCTIP_REF1_def 0x00000029 | |
1967 #define fld_CLAMP_REF_def 0x0000003B | |
1968 #define fld_AGC_PEAKWHITE_def 0x000000FF | |
1969 #define fld_VBI_PEAKWHITE_def 0x000000D2 | |
1970 | |
1971 #define fld_WPA_THRESHOLD_def 0x000003B0 | |
1972 | |
1973 #define fld_WPA_TRIGGER_LO_def 0x000000B4 | |
1974 #define fld_WPA_TRIGGER_HIGH_def 0x0000021C | |
1975 | |
1976 #define fld_LOCKOUT_START_def 0x00000206 | |
1977 #define fld_LOCKOUT_END_def 0x00000021 | |
1978 | |
1979 #define fld_CH_DTO_INC_def 0x00400000 | |
1980 #define fld_PLL_SGAIN_def 0x00000001 | |
1981 #define fld_PLL_FGAIN_def 0x00000002 | |
1982 | |
1983 #define fld_CR_BURST_GAIN_def 0x0000007a | |
1984 #define fld_CB_BURST_GAIN_def 0x000000ac | |
1985 | |
1986 #define fld_VERT_LOCKOUT_START_def 0x00000207 | |
1987 #define fld_VERT_LOCKOUT_END_def 0x0000000E | |
1988 | |
1989 #define fld_H_IN_WIND_START_def 0x00000070 | |
1990 #define fld_V_IN_WIND_START_def 0x00000027 | |
1991 | |
1992 #define fld_H_OUT_WIND_WIDTH_def 0x000002f4 | |
1993 | |
1994 #define fld_V_OUT_WIND_WIDTH_def 0x000000f0 | |
1995 | |
1996 #define fld_HS_LINE_TOTAL_def 0x0000038E | |
1997 | |
1998 #define fld_MIN_PULSE_WIDTH_def 0x0000002F | |
1999 #define fld_MAX_PULSE_WIDTH_def 0x00000046 | |
2000 | |
2001 #define fld_WIN_CLOSE_LIMIT_def 0x0000004D | |
2002 #define fld_WIN_OPEN_LIMIT_def 0x000001B7 | |
2003 | |
2004 #define fld_VSYNC_INT_TRIGGER_def 0x000002AA | |
2005 | |
2006 #define fld_VSYNC_INT_HOLD_def 0x0000001D | |
2007 | |
2008 #define fld_VIN_M0_def 0x00000039 | |
2009 #define fld_VIN_N0_def 0x0000014c | |
2010 #define fld_MNFLIP_EN_def 0x00000000 | |
2011 #define fld_VIN_P_def 0x00000006 | |
2012 #define fld_REG_CLK_SEL_def 0x00000000 | |
2013 | |
2014 #define fld_VIN_M1_def 0x00000000 | |
2015 #define fld_VIN_N1_def 0x00000000 | |
2016 #define fld_VIN_DRIVER_SEL_def 0x00000000 | |
2017 #define fld_VIN_MNFLIP_REQ_def 0x00000000 | |
2018 #define fld_VIN_MNFLIP_DONE_def 0x00000000 | |
2019 #define fld_TV_LOCK_TO_VIN_def 0x00000000 | |
2020 #define fld_TV_P_FOR_WINCLK_def 0x00000004 | |
2021 | |
2022 #define fld_VINRST_def 0x00000001 | |
2023 #define fld_VIN_CLK_SEL_def 0x00000000 | |
2024 | |
2025 #define fld_VS_FIELD_BLANK_START_def 0x00000206 | |
2026 | |
2027 #define fld_VS_FIELD_BLANK_END_def 0x0000000A | |
2028 | |
2029 /*#define fld_VS_FIELD_IDLOCATION_def 0x00000105 */ | |
2030 #define fld_VS_FIELD_IDLOCATION_def 0x00000001 | |
2031 #define fld_VS_FRAME_TOTAL_def 0x00000217 | |
2032 | |
2033 #define fld_SYNC_TIP_START_def 0x00000372 | |
2034 #define fld_SYNC_TIP_LENGTH_def 0x0000000F | |
2035 | |
2036 #define fld_GAIN_FORCE_DATA_def 0x00000000 | |
2037 #define fld_GAIN_FORCE_EN_def 0x00000000 | |
2038 #define fld_I_CLAMP_SEL_def 0x00000003 | |
2039 #define fld_I_AGC_SEL_def 0x00000001 | |
2040 #define fld_EXT_CLAMP_CAP_def 0x00000001 | |
2041 #define fld_EXT_AGC_CAP_def 0x00000001 | |
2042 #define fld_DECI_DITHER_EN_def 0x00000001 | |
2043 #define fld_ADC_PREFHI_def 0x00000000 | |
2044 #define fld_ADC_CH_GAIN_SEL_def 0x00000001 | |
2045 | |
2046 #define fld_HS_PLL_SGAIN_def 0x00000003 | |
2047 | |
2048 #define fld_NREn_def 0x00000000 | |
2049 #define fld_NRGainCntl_def 0x00000000 | |
2050 #define fld_NRBWTresh_def 0x00000000 | |
2051 #define fld_NRGCTresh_def 0x00000000 | |
2052 #define fld_NRCoefDespeclMode_def 0x00000000 | |
2053 | |
2054 #define fld_GPIO_5_OE_def 0x00000000 | |
2055 #define fld_GPIO_6_OE_def 0x00000000 | |
2056 | |
2057 #define fld_GPIO_5_OUT_def 0x00000000 | |
2058 #define fld_GPIO_6_OUT_def 0x00000000 | |
2059 | |
2060 /* End of field default values. */ | |
2061 | |
2062 #endif /* RADEON_H */ |