Mercurial > mplayer.hg
annotate libvo/aclib_template.c @ 34802:0743fc227f05
Add a preliminary release.sh file.
author | reimar |
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date | Sun, 06 May 2012 12:34:00 +0000 |
parents | 4e2f4bd081ce |
children | b4ce15212bfc |
rev | line source |
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10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
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1 /* |
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2 * aclib - advanced C library ;) |
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3 * functions which improve and expand the standard C library |
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4 * |
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5 * This file is part of MPlayer. |
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6 * |
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7 * MPlayer is free software; you can redistribute it and/or modify |
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8 * it under the terms of the GNU General Public License as published by |
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9 * the Free Software Foundation; either version 2 of the License, or |
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10 * (at your option) any later version. |
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11 * |
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12 * MPlayer is distributed in the hope that it will be useful, |
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13 * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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15 * GNU General Public License for more details. |
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16 * |
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17 * You should have received a copy of the GNU General Public License along |
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18 * with MPlayer; if not, write to the Free Software Foundation, Inc., |
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19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. |
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20 */ |
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21 |
28290 | 22 #if !HAVE_SSE2 |
1123 | 23 /* |
24 P3 processor has only one SSE decoder so can execute only 1 sse insn per | |
25 cpu clock, but it has 3 mmx decoders (include load/store unit) | |
26 and executes 3 mmx insns per cpu clock. | |
27 P4 processor has some chances, but after reading: | |
28 http://www.emulators.com/pentium4.htm | |
29 I have doubts. Anyway SSE2 version of this code can be written better. | |
30 */ | |
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31 #undef HAVE_SSE |
28290 | 32 #define HAVE_SSE 0 |
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33 #endif |
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34 |
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35 |
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36 /* |
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37 This part of code was taken by me from Linux-2.4.3 and slightly modified |
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38 for MMX, MMX2, SSE instruction set. I have done it since linux uses page aligned |
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39 blocks but mplayer uses weakly ordered data and original sources can not |
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40 speedup them. Only using PREFETCHNTA and MOVNTQ together have effect! |
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41 |
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42 >From IA-32 Intel Architecture Software Developer's Manual Volume 1, |
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43 |
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44 Order Number 245470: |
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45 "10.4.6. Cacheability Control, Prefetch, and Memory Ordering Instructions" |
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46 |
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47 Data referenced by a program can be temporal (data will be used again) or |
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48 non-temporal (data will be referenced once and not reused in the immediate |
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49 future). To make efficient use of the processor's caches, it is generally |
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50 desirable to cache temporal data and not cache non-temporal data. Overloading |
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51 the processor's caches with non-temporal data is sometimes referred to as |
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52 "polluting the caches". |
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53 The non-temporal data is written to memory with Write-Combining semantics. |
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54 |
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55 The PREFETCHh instructions permits a program to load data into the processor |
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56 at a suggested cache level, so that it is closer to the processors load and |
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57 store unit when it is needed. If the data is already present in a level of |
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58 the cache hierarchy that is closer to the processor, the PREFETCHh instruction |
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59 will not result in any data movement. |
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60 But we should you PREFETCHNTA: Non-temporal data fetch data into location |
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61 close to the processor, minimizing cache pollution. |
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62 |
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63 The MOVNTQ (store quadword using non-temporal hint) instruction stores |
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64 packed integer data from an MMX register to memory, using a non-temporal hint. |
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65 The MOVNTPS (store packed single-precision floating-point values using |
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66 non-temporal hint) instruction stores packed floating-point data from an |
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67 XMM register to memory, using a non-temporal hint. |
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68 |
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69 The SFENCE (Store Fence) instruction controls write ordering by creating a |
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70 fence for memory store operations. This instruction guarantees that the results |
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71 of every store instruction that precedes the store fence in program order is |
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72 globally visible before any store instruction that follows the fence. The |
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73 SFENCE instruction provides an efficient way of ensuring ordering between |
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74 procedures that produce weakly-ordered data and procedures that consume that |
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75 data. |
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76 |
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77 If you have questions please contact with me: Nick Kurshev: nickols_k@mail.ru. |
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78 */ |
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79 |
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80 // 3dnow memcpy support from kernel 2.4.2 |
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81 // by Pontscho/fresh!mindworkz |
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82 |
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83 #include "libavutil/x86_cpu.h" |
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84 |
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85 #undef HAVE_ONLY_MMX1 |
28335 | 86 #if HAVE_MMX && !HAVE_MMX2 && !HAVE_AMD3DNOW && !HAVE_SSE |
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87 /* means: mmx v.1. Note: Since we added alignment of destinition it speedups |
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88 of memory copying on PentMMX, Celeron-1 and P2 upto 12% versus |
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89 standard (non MMX-optimized) version. |
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90 Note: on K6-2+ it speedups memory copying upto 25% and |
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91 on K7 and P3 about 500% (5 times). */ |
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92 #define HAVE_ONLY_MMX1 |
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93 #endif |
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94 |
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95 |
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96 #undef HAVE_K6_2PLUS |
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98 #define HAVE_K6_2PLUS |
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99 #endif |
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100 |
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101 /* for small memory blocks (<256 bytes) this version is faster */ |
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102 #define small_memcpy(to,from,n)\ |
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103 {\ |
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104 register x86_reg dummy;\ |
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105 __asm__ volatile(\ |
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106 "rep; movsb"\ |
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107 :"=&D"(to), "=&S"(from), "=&c"(dummy)\ |
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108 /* It's most portable way to notify compiler */\ |
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109 /* that edi, esi and ecx are clobbered in asm block. */\ |
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110 /* Thanks to A'rpi for hint!!! */\ |
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111 :"0" (to), "1" (from),"2" (n)\ |
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112 : "memory");\ |
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113 } |
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114 |
3393 | 115 #undef MMREG_SIZE |
28290 | 116 #if HAVE_SSE |
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117 #define MMREG_SIZE 16 |
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118 #else |
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119 #define MMREG_SIZE 64 //8 |
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120 #endif |
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121 |
3393 | 122 #undef PREFETCH |
123 #undef EMMS | |
5660 | 124 |
28290 | 125 #if HAVE_MMX2 |
5662 | 126 #define PREFETCH "prefetchnta" |
28335 | 127 #elif HAVE_AMD3DNOW |
5660 | 128 #define PREFETCH "prefetch" |
129 #else | |
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130 #define PREFETCH " # nop" |
5660 | 131 #endif |
132 | |
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133 /* On K6 femms is faster of emms. On K7 femms is directly mapped on emms. */ |
28335 | 134 #if HAVE_AMD3DNOW |
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135 #define EMMS "femms" |
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136 #else |
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137 #define EMMS "emms" |
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138 #endif |
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139 |
3393 | 140 #undef MOVNTQ |
28290 | 141 #if HAVE_MMX2 |
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142 #define MOVNTQ "movntq" |
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143 #else |
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144 #define MOVNTQ "movq" |
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145 #endif |
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146 |
3393 | 147 #undef MIN_LEN |
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148 #ifdef HAVE_ONLY_MMX1 |
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149 #define MIN_LEN 0x800 /* 2K blocks */ |
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150 #else |
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151 #define MIN_LEN 0x40 /* 64-byte blocks */ |
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152 #endif |
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153 |
7072 | 154 static void * RENAME(fast_memcpy)(void * to, const void * from, size_t len) |
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155 { |
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156 void *retval; |
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157 size_t i; |
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158 retval = to; |
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159 #ifdef STATISTICS |
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160 { |
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161 static int freq[33]; |
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162 static int t=0; |
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163 int i; |
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164 for(i=0; len>(1<<i); i++); |
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165 freq[i]++; |
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166 t++; |
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167 if(1024*1024*1024 % t == 0) |
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168 for(i=0; i<32; i++) |
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169 printf("freq < %8d %4d\n", 1<<i, freq[i]); |
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170 } |
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171 #endif |
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172 #ifndef HAVE_ONLY_MMX1 |
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173 /* PREFETCH has effect even for MOVSB instruction ;) */ |
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174 __asm__ volatile ( |
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175 PREFETCH" (%0)\n" |
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176 PREFETCH" 64(%0)\n" |
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177 PREFETCH" 128(%0)\n" |
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178 PREFETCH" 192(%0)\n" |
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179 PREFETCH" 256(%0)\n" |
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180 : : "r" (from) ); |
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181 #endif |
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182 if(len >= MIN_LEN) |
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183 { |
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184 register x86_reg delta; |
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185 /* Align destinition to MMREG_SIZE -boundary */ |
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186 delta = ((intptr_t)to)&(MMREG_SIZE-1); |
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187 if(delta) |
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188 { |
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189 delta=MMREG_SIZE-delta; |
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190 len -= delta; |
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191 small_memcpy(to, from, delta); |
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192 } |
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193 i = len >> 6; /* len/64 */ |
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194 len&=63; |
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195 /* |
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196 This algorithm is top effective when the code consequently |
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197 reads and writes blocks which have size of cache line. |
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198 Size of cache line is processor-dependent. |
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199 It will, however, be a minimum of 32 bytes on any processors. |
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200 It would be better to have a number of instructions which |
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201 perform reading and writing to be multiple to a number of |
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202 processor's decoders, but it's not always possible. |
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203 */ |
28290 | 204 #if HAVE_SSE /* Only P3 (may be Cyrix3) */ |
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205 if(((intptr_t)from) & 15) |
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206 /* if SRC is misaligned */ |
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207 for(; i>0; i--) |
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208 { |
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209 __asm__ volatile ( |
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210 PREFETCH" 320(%0)\n" |
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211 "movups (%0), %%xmm0\n" |
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212 "movups 16(%0), %%xmm1\n" |
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213 "movups 32(%0), %%xmm2\n" |
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214 "movups 48(%0), %%xmm3\n" |
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215 "movntps %%xmm0, (%1)\n" |
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216 "movntps %%xmm1, 16(%1)\n" |
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217 "movntps %%xmm2, 32(%1)\n" |
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218 "movntps %%xmm3, 48(%1)\n" |
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219 :: "r" (from), "r" (to) : "memory"); |
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220 from=((const unsigned char *) from)+64; |
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221 to=((unsigned char *)to)+64; |
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222 } |
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223 else |
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224 /* |
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225 Only if SRC is aligned on 16-byte boundary. |
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226 It allows to use movaps instead of movups, which required data |
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227 to be aligned or a general-protection exception (#GP) is generated. |
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228 */ |
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229 for(; i>0; i--) |
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230 { |
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231 __asm__ volatile ( |
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232 PREFETCH" 320(%0)\n" |
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233 "movaps (%0), %%xmm0\n" |
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234 "movaps 16(%0), %%xmm1\n" |
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235 "movaps 32(%0), %%xmm2\n" |
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236 "movaps 48(%0), %%xmm3\n" |
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237 "movntps %%xmm0, (%1)\n" |
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238 "movntps %%xmm1, 16(%1)\n" |
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239 "movntps %%xmm2, 32(%1)\n" |
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240 "movntps %%xmm3, 48(%1)\n" |
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241 :: "r" (from), "r" (to) : "memory"); |
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242 from=((const unsigned char *)from)+64; |
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243 to=((unsigned char *)to)+64; |
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244 } |
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245 #else |
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246 // Align destination at BLOCK_SIZE boundary |
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247 for(; ((intptr_t)to & (BLOCK_SIZE-1)) && i>0; i--) |
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248 { |
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249 __asm__ volatile ( |
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250 #ifndef HAVE_ONLY_MMX1 |
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251 PREFETCH" 320(%0)\n" |
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252 #endif |
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253 "movq (%0), %%mm0\n" |
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254 "movq 8(%0), %%mm1\n" |
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255 "movq 16(%0), %%mm2\n" |
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256 "movq 24(%0), %%mm3\n" |
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257 "movq 32(%0), %%mm4\n" |
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258 "movq 40(%0), %%mm5\n" |
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259 "movq 48(%0), %%mm6\n" |
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260 "movq 56(%0), %%mm7\n" |
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10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
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261 MOVNTQ" %%mm0, (%1)\n" |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
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262 MOVNTQ" %%mm1, 8(%1)\n" |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
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263 MOVNTQ" %%mm2, 16(%1)\n" |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
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264 MOVNTQ" %%mm3, 24(%1)\n" |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
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265 MOVNTQ" %%mm4, 32(%1)\n" |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
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266 MOVNTQ" %%mm5, 40(%1)\n" |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
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267 MOVNTQ" %%mm6, 48(%1)\n" |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
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268 MOVNTQ" %%mm7, 56(%1)\n" |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
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269 :: "r" (from), "r" (to) : "memory"); |
15639 | 270 from=((const unsigned char *)from)+64; |
271 to=((unsigned char *)to)+64; | |
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10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
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272 } |
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10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
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273 |
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10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
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274 // printf(" %d %d\n", (int)from&1023, (int)to&1023); |
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10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
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275 // Pure Assembly cuz gcc is a bit unpredictable ;) |
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10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
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276 if(i>=BLOCK_SIZE/64) |
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Change all occurrences of asm and __asm to __asm__, same as was done for FFmpeg.
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277 __asm__ volatile( |
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278 "xor %%"REG_a", %%"REG_a" \n\t" |
25973
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279 ASMALIGN(4) |
3077
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10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
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280 "1: \n\t" |
29645
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Use ecx instead of ebx to avoid unnecessary issues with PIC.
reimar
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281 "movl (%0, %%"REG_a"), %%ecx \n\t" |
7eb282a13214
Use ecx instead of ebx to avoid unnecessary issues with PIC.
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282 "movl 32(%0, %%"REG_a"), %%ecx \n\t" |
7eb282a13214
Use ecx instead of ebx to avoid unnecessary issues with PIC.
reimar
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283 "movl 64(%0, %%"REG_a"), %%ecx \n\t" |
7eb282a13214
Use ecx instead of ebx to avoid unnecessary issues with PIC.
reimar
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284 "movl 96(%0, %%"REG_a"), %%ecx \n\t" |
13720
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285 "add $128, %%"REG_a" \n\t" |
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286 "cmp %3, %%"REG_a" \n\t" |
3077
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
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287 " jb 1b \n\t" |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
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288 |
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289 "xor %%"REG_a", %%"REG_a" \n\t" |
3077
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
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290 |
25973
ef4297ed0d12
libvo: change asm syntax to use ASMALIGN and " # nop"
uau
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291 ASMALIGN(4) |
3077
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
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292 "2: \n\t" |
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293 "movq (%0, %%"REG_a"), %%mm0\n" |
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294 "movq 8(%0, %%"REG_a"), %%mm1\n" |
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295 "movq 16(%0, %%"REG_a"), %%mm2\n" |
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296 "movq 24(%0, %%"REG_a"), %%mm3\n" |
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297 "movq 32(%0, %%"REG_a"), %%mm4\n" |
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298 "movq 40(%0, %%"REG_a"), %%mm5\n" |
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299 "movq 48(%0, %%"REG_a"), %%mm6\n" |
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300 "movq 56(%0, %%"REG_a"), %%mm7\n" |
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301 MOVNTQ" %%mm0, (%1, %%"REG_a")\n" |
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302 MOVNTQ" %%mm1, 8(%1, %%"REG_a")\n" |
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adapting existing mmx/mmx2/sse/3dnow optimizations so they work on x86_64
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303 MOVNTQ" %%mm2, 16(%1, %%"REG_a")\n" |
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304 MOVNTQ" %%mm3, 24(%1, %%"REG_a")\n" |
821f464b4d90
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305 MOVNTQ" %%mm4, 32(%1, %%"REG_a")\n" |
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306 MOVNTQ" %%mm5, 40(%1, %%"REG_a")\n" |
821f464b4d90
adapting existing mmx/mmx2/sse/3dnow optimizations so they work on x86_64
aurel
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307 MOVNTQ" %%mm6, 48(%1, %%"REG_a")\n" |
821f464b4d90
adapting existing mmx/mmx2/sse/3dnow optimizations so they work on x86_64
aurel
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308 MOVNTQ" %%mm7, 56(%1, %%"REG_a")\n" |
821f464b4d90
adapting existing mmx/mmx2/sse/3dnow optimizations so they work on x86_64
aurel
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309 "add $64, %%"REG_a" \n\t" |
821f464b4d90
adapting existing mmx/mmx2/sse/3dnow optimizations so they work on x86_64
aurel
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310 "cmp %3, %%"REG_a" \n\t" |
3077
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
michael
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311 "jb 2b \n\t" |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
michael
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312 |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
michael
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313 #if CONFUSION_FACTOR > 0 |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
michael
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314 // a few percent speedup on out of order executing CPUs |
13720
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aurel
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315 "mov %5, %%"REG_a" \n\t" |
3077
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
michael
parents:
1123
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|
316 "2: \n\t" |
29645
7eb282a13214
Use ecx instead of ebx to avoid unnecessary issues with PIC.
reimar
parents:
28446
diff
changeset
|
317 "movl (%0), %%ecx \n\t" |
7eb282a13214
Use ecx instead of ebx to avoid unnecessary issues with PIC.
reimar
parents:
28446
diff
changeset
|
318 "movl (%0), %%ecx \n\t" |
7eb282a13214
Use ecx instead of ebx to avoid unnecessary issues with PIC.
reimar
parents:
28446
diff
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|
319 "movl (%0), %%ecx \n\t" |
7eb282a13214
Use ecx instead of ebx to avoid unnecessary issues with PIC.
reimar
parents:
28446
diff
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|
320 "movl (%0), %%ecx \n\t" |
13720
821f464b4d90
adapting existing mmx/mmx2/sse/3dnow optimizations so they work on x86_64
aurel
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321 "dec %%"REG_a" \n\t" |
3077
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
michael
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322 " jnz 2b \n\t" |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
michael
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323 #endif |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
michael
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324 |
13720
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aurel
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325 "xor %%"REG_a", %%"REG_a" \n\t" |
821f464b4d90
adapting existing mmx/mmx2/sse/3dnow optimizations so they work on x86_64
aurel
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326 "add %3, %0 \n\t" |
821f464b4d90
adapting existing mmx/mmx2/sse/3dnow optimizations so they work on x86_64
aurel
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327 "add %3, %1 \n\t" |
821f464b4d90
adapting existing mmx/mmx2/sse/3dnow optimizations so they work on x86_64
aurel
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328 "sub %4, %2 \n\t" |
821f464b4d90
adapting existing mmx/mmx2/sse/3dnow optimizations so they work on x86_64
aurel
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329 "cmp %4, %2 \n\t" |
3077
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
michael
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330 " jae 1b \n\t" |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
michael
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331 : "+r" (from), "+r" (to), "+r" (i) |
30135
807fce7a4bb3
Do not assume that "long" is the size of a register.
reimar
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332 : "r" ((x86_reg)BLOCK_SIZE), "i" (BLOCK_SIZE/64), "i" ((x86_reg)CONFUSION_FACTOR) |
29645
7eb282a13214
Use ecx instead of ebx to avoid unnecessary issues with PIC.
reimar
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333 : "%"REG_a, "%ecx" |
3077
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
michael
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|
334 ); |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
michael
parents:
1123
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|
335 |
698
f0fbf1a9bf31
Moving fast_memcpy to separate file (Size optimization)
nickols_k
parents:
diff
changeset
|
336 for(; i>0; i--) |
f0fbf1a9bf31
Moving fast_memcpy to separate file (Size optimization)
nickols_k
parents:
diff
changeset
|
337 { |
27757
b5a46071062a
Replace all occurrences of '__volatile__' and '__volatile' by plain 'volatile'.
diego
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27754
diff
changeset
|
338 __asm__ volatile ( |
23378
ef54df9f07d3
HAVE_MMX1 -> HAVE_ONLY_MMX1 (makes more sense ...)
michael
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15639
diff
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|
339 #ifndef HAVE_ONLY_MMX1 |
698
f0fbf1a9bf31
Moving fast_memcpy to separate file (Size optimization)
nickols_k
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diff
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|
340 PREFETCH" 320(%0)\n" |
f0fbf1a9bf31
Moving fast_memcpy to separate file (Size optimization)
nickols_k
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diff
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|
341 #endif |
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Moving fast_memcpy to separate file (Size optimization)
nickols_k
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diff
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|
342 "movq (%0), %%mm0\n" |
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Moving fast_memcpy to separate file (Size optimization)
nickols_k
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diff
changeset
|
343 "movq 8(%0), %%mm1\n" |
f0fbf1a9bf31
Moving fast_memcpy to separate file (Size optimization)
nickols_k
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diff
changeset
|
344 "movq 16(%0), %%mm2\n" |
f0fbf1a9bf31
Moving fast_memcpy to separate file (Size optimization)
nickols_k
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345 "movq 24(%0), %%mm3\n" |
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Moving fast_memcpy to separate file (Size optimization)
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346 "movq 32(%0), %%mm4\n" |
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Moving fast_memcpy to separate file (Size optimization)
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347 "movq 40(%0), %%mm5\n" |
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348 "movq 48(%0), %%mm6\n" |
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349 "movq 56(%0), %%mm7\n" |
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Moving fast_memcpy to separate file (Size optimization)
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350 MOVNTQ" %%mm0, (%1)\n" |
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351 MOVNTQ" %%mm1, 8(%1)\n" |
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352 MOVNTQ" %%mm2, 16(%1)\n" |
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Moving fast_memcpy to separate file (Size optimization)
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353 MOVNTQ" %%mm3, 24(%1)\n" |
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Moving fast_memcpy to separate file (Size optimization)
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354 MOVNTQ" %%mm4, 32(%1)\n" |
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Moving fast_memcpy to separate file (Size optimization)
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355 MOVNTQ" %%mm5, 40(%1)\n" |
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356 MOVNTQ" %%mm6, 48(%1)\n" |
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357 MOVNTQ" %%mm7, 56(%1)\n" |
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358 :: "r" (from), "r" (to) : "memory"); |
15639 | 359 from=((const unsigned char *)from)+64; |
360 to=((unsigned char *)to)+64; | |
698
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Moving fast_memcpy to separate file (Size optimization)
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361 } |
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10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
michael
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362 |
698
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Moving fast_memcpy to separate file (Size optimization)
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363 #endif /* Have SSE */ |
28290 | 364 #if HAVE_MMX2 |
698
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Moving fast_memcpy to separate file (Size optimization)
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365 /* since movntq is weakly-ordered, a "sfence" |
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Moving fast_memcpy to separate file (Size optimization)
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366 * is needed to become ordered again. */ |
27757
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Replace all occurrences of '__volatile__' and '__volatile' by plain 'volatile'.
diego
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367 __asm__ volatile ("sfence":::"memory"); |
698
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368 #endif |
28290 | 369 #if !HAVE_SSE |
698
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Moving fast_memcpy to separate file (Size optimization)
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370 /* enables to use FPU */ |
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371 __asm__ volatile (EMMS:::"memory"); |
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10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
michael
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372 #endif |
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Moving fast_memcpy to separate file (Size optimization)
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373 } |
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Moving fast_memcpy to separate file (Size optimization)
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374 /* |
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Moving fast_memcpy to separate file (Size optimization)
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375 * Now do the tail of the block |
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Moving fast_memcpy to separate file (Size optimization)
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376 */ |
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377 if(len) small_memcpy(to, from, len); |
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378 return retval; |
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Moving fast_memcpy to separate file (Size optimization)
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379 } |
4681 | 380 |
381 /** | |
382 * special copy routine for mem -> agp/pci copy (based upon fast_memcpy) | |
383 */ | |
7072 | 384 static void * RENAME(mem2agpcpy)(void * to, const void * from, size_t len) |
4681 | 385 { |
386 void *retval; | |
387 size_t i; | |
388 retval = to; | |
389 #ifdef STATISTICS | |
390 { | |
391 static int freq[33]; | |
392 static int t=0; | |
393 int i; | |
394 for(i=0; len>(1<<i); i++); | |
395 freq[i]++; | |
396 t++; | |
397 if(1024*1024*1024 % t == 0) | |
398 for(i=0; i<32; i++) | |
399 printf("mem2agp freq < %8d %4d\n", 1<<i, freq[i]); | |
400 } | |
401 #endif | |
402 if(len >= MIN_LEN) | |
403 { | |
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Do not assume that "long" is the size of a register.
reimar
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404 register x86_reg delta; |
4681 | 405 /* Align destinition to MMREG_SIZE -boundary */ |
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Do not assume that "long" is the size of a register.
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406 delta = ((intptr_t)to)&7; |
4681 | 407 if(delta) |
408 { | |
409 delta=8-delta; | |
410 len -= delta; | |
411 small_memcpy(to, from, delta); | |
412 } | |
413 i = len >> 6; /* len/64 */ | |
414 len &= 63; | |
415 /* | |
416 This algorithm is top effective when the code consequently | |
417 reads and writes blocks which have size of cache line. | |
418 Size of cache line is processor-dependent. | |
419 It will, however, be a minimum of 32 bytes on any processors. | |
420 It would be better to have a number of instructions which | |
421 perform reading and writing to be multiple to a number of | |
422 processor's decoders, but it's not always possible. | |
423 */ | |
424 for(; i>0; i--) | |
425 { | |
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diego
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426 __asm__ volatile ( |
4681 | 427 PREFETCH" 320(%0)\n" |
428 "movq (%0), %%mm0\n" | |
429 "movq 8(%0), %%mm1\n" | |
430 "movq 16(%0), %%mm2\n" | |
431 "movq 24(%0), %%mm3\n" | |
432 "movq 32(%0), %%mm4\n" | |
433 "movq 40(%0), %%mm5\n" | |
434 "movq 48(%0), %%mm6\n" | |
435 "movq 56(%0), %%mm7\n" | |
436 MOVNTQ" %%mm0, (%1)\n" | |
437 MOVNTQ" %%mm1, 8(%1)\n" | |
438 MOVNTQ" %%mm2, 16(%1)\n" | |
439 MOVNTQ" %%mm3, 24(%1)\n" | |
440 MOVNTQ" %%mm4, 32(%1)\n" | |
441 MOVNTQ" %%mm5, 40(%1)\n" | |
442 MOVNTQ" %%mm6, 48(%1)\n" | |
443 MOVNTQ" %%mm7, 56(%1)\n" | |
444 :: "r" (from), "r" (to) : "memory"); | |
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Make this file compile with gcc-4.0.0. The old code was invalid C.
gpoirier
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445 from=((const unsigned char *)from)+64; |
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Make this file compile with gcc-4.0.0. The old code was invalid C.
gpoirier
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446 to=((unsigned char *)to)+64; |
4681 | 447 } |
28290 | 448 #if HAVE_MMX2 |
4681 | 449 /* since movntq is weakly-ordered, a "sfence" |
450 * is needed to become ordered again. */ | |
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diego
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451 __asm__ volatile ("sfence":::"memory"); |
4681 | 452 #endif |
453 /* enables to use FPU */ | |
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diego
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454 __asm__ volatile (EMMS:::"memory"); |
4681 | 455 } |
456 /* | |
457 * Now do the tail of the block | |
458 */ | |
459 if(len) small_memcpy(to, from, len); | |
460 return retval; | |
461 } |