Mercurial > mplayer.hg
annotate cpudetect.h @ 28737:156052eef5f0
Fix 10l typo in ADD_ALL_EXESUFS function name.
author | diego |
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date | Sun, 01 Mar 2009 11:22:31 +0000 |
parents | b089d639e810 |
children | e1b7d9bf263b |
rev | line source |
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26029 | 1 #ifndef MPLAYER_CPUDETECT_H |
2 #define MPLAYER_CPUDETECT_H | |
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cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
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3 |
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Add necessary header for ARCH_X86_64 preprocessor check.
diego
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4 #include "config.h" |
b089d639e810
Add necessary header for ARCH_X86_64 preprocessor check.
diego
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5 |
2281 | 6 #define CPUTYPE_I386 3 |
7 #define CPUTYPE_I486 4 | |
8 #define CPUTYPE_I586 5 | |
9 #define CPUTYPE_I686 6 | |
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cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
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10 |
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Fix first handful of #if vs. #ifdef for ARCH_, HAVE_SSE etc.
reimar
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11 #if ARCH_X86_64 |
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adapting existing mmx/mmx2/sse/3dnow optimizations so they work on x86_64
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12 # define REGa rax |
821f464b4d90
adapting existing mmx/mmx2/sse/3dnow optimizations so they work on x86_64
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13 # define REGb rbx |
18391 | 14 # define REGBP rbp |
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adapting existing mmx/mmx2/sse/3dnow optimizations so they work on x86_64
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15 # define REGSP rsp |
821f464b4d90
adapting existing mmx/mmx2/sse/3dnow optimizations so they work on x86_64
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16 # define REG_a "rax" |
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adapting existing mmx/mmx2/sse/3dnow optimizations so they work on x86_64
aurel
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17 # define REG_b "rbx" |
821f464b4d90
adapting existing mmx/mmx2/sse/3dnow optimizations so they work on x86_64
aurel
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18 # define REG_c "rcx" |
821f464b4d90
adapting existing mmx/mmx2/sse/3dnow optimizations so they work on x86_64
aurel
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19 # define REG_d "rdx" |
821f464b4d90
adapting existing mmx/mmx2/sse/3dnow optimizations so they work on x86_64
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20 # define REG_S "rsi" |
821f464b4d90
adapting existing mmx/mmx2/sse/3dnow optimizations so they work on x86_64
aurel
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21 # define REG_D "rdi" |
821f464b4d90
adapting existing mmx/mmx2/sse/3dnow optimizations so they work on x86_64
aurel
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22 # define REG_SP "rsp" |
821f464b4d90
adapting existing mmx/mmx2/sse/3dnow optimizations so they work on x86_64
aurel
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23 # define REG_BP "rbp" |
821f464b4d90
adapting existing mmx/mmx2/sse/3dnow optimizations so they work on x86_64
aurel
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24 #else |
821f464b4d90
adapting existing mmx/mmx2/sse/3dnow optimizations so they work on x86_64
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25 # define REGa eax |
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adapting existing mmx/mmx2/sse/3dnow optimizations so they work on x86_64
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26 # define REGb ebx |
18391 | 27 # define REGBP ebp |
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adapting existing mmx/mmx2/sse/3dnow optimizations so they work on x86_64
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28 # define REGSP esp |
821f464b4d90
adapting existing mmx/mmx2/sse/3dnow optimizations so they work on x86_64
aurel
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29 # define REG_a "eax" |
821f464b4d90
adapting existing mmx/mmx2/sse/3dnow optimizations so they work on x86_64
aurel
parents:
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30 # define REG_b "ebx" |
821f464b4d90
adapting existing mmx/mmx2/sse/3dnow optimizations so they work on x86_64
aurel
parents:
10885
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31 # define REG_c "ecx" |
821f464b4d90
adapting existing mmx/mmx2/sse/3dnow optimizations so they work on x86_64
aurel
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32 # define REG_d "edx" |
821f464b4d90
adapting existing mmx/mmx2/sse/3dnow optimizations so they work on x86_64
aurel
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33 # define REG_S "esi" |
821f464b4d90
adapting existing mmx/mmx2/sse/3dnow optimizations so they work on x86_64
aurel
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34 # define REG_D "edi" |
821f464b4d90
adapting existing mmx/mmx2/sse/3dnow optimizations so they work on x86_64
aurel
parents:
10885
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35 # define REG_SP "esp" |
821f464b4d90
adapting existing mmx/mmx2/sse/3dnow optimizations so they work on x86_64
aurel
parents:
10885
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36 # define REG_BP "ebp" |
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adapting existing mmx/mmx2/sse/3dnow optimizations so they work on x86_64
aurel
parents:
10885
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37 #endif |
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adapting existing mmx/mmx2/sse/3dnow optimizations so they work on x86_64
aurel
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38 |
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cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
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39 typedef struct cpucaps_s { |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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40 int cpuType; |
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Retrieve CPU built-in namestring, and if it exists, print it during cpu detection; t it doesn't exist, fallback to the cpu table. Patch by Zuxy Meng
gpoirier
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41 int cpuModel; |
3403 | 42 int cpuStepping; |
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cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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43 int hasMMX; |
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cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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44 int hasMMX2; |
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cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
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45 int has3DNow; |
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cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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46 int has3DNowExt; |
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cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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47 int hasSSE; |
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cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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48 int hasSSE2; |
27926
a02c39208d49
Add detection of x86 CPU features SSSE3 and SSE4a.
gpoirier
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49 int hasSSSE3; |
a02c39208d49
Add detection of x86 CPU features SSSE3 and SSE4a.
gpoirier
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50 int hasSSE4a; |
3146
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non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
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51 int isX86; |
8860 | 52 unsigned cl_size; /* size of cache line */ |
9003 | 53 int hasAltiVec; |
10885
685c416f12b5
cpuspeed detection for X86 TSC capable CPUs (also added TSC detection, should best be verified by some people with TSC/nonTSC capable CPUs)
atmos4
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54 int hasTSC; |
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cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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55 } CpuCaps; |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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56 |
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cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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57 extern CpuCaps gCpuCaps; |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
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58 |
2301 | 59 void GetCpuCaps(CpuCaps *caps); |
2303 | 60 |
61 /* returned value is malloc()'ed so free() it after use */ | |
2301 | 62 char *GetCpuFriendlyName(unsigned int regs[], unsigned int regs2[]); |
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arpi
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63 |
26029 | 64 #endif /* MPLAYER_CPUDETECT_H */ |