Mercurial > mplayer.hg
annotate vidix/drivers/savage_regs.h @ 20393:15c01d3248c1
sync w/ r20408
author | gpoirier |
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date | Mon, 23 Oct 2006 11:13:49 +0000 |
parents | 8be9b0f1e4b6 |
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rev | line source |
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1 /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/savage/savage_regs.h,v 1.10 2001/11/04 22:17:48 alanh Exp $ */ |
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2 |
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3 #ifndef _SAVAGE_REGS_H |
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4 #define _SAVAGE_REGS_H |
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5 |
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6 /* These are here until xf86PciInfo.h is updated. */ |
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7 |
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8 #ifndef PCI_CHIP_S3TWISTER_P |
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9 #define PCI_CHIP_S3TWISTER_P 0x8d01 |
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10 #endif |
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11 #ifndef PCI_CHIP_S3TWISTER_K |
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12 #define PCI_CHIP_S3TWISTER_K 0x8d02 |
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13 #endif |
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14 #ifndef PCI_CHIP_SUPSAV_MX128 |
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15 #define PCI_CHIP_SUPSAV_MX128 0x8c22 |
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16 #define PCI_CHIP_SUPSAV_MX64 0x8c24 |
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17 #define PCI_CHIP_SUPSAV_MX64C 0x8c26 |
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18 #define PCI_CHIP_SUPSAV_IX128SDR 0x8c2a |
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19 #define PCI_CHIP_SUPSAV_IX128DDR 0x8c2b |
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20 #define PCI_CHIP_SUPSAV_IX64SDR 0x8c2c |
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21 #define PCI_CHIP_SUPSAV_IX64DDR 0x8c2d |
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22 #define PCI_CHIP_SUPSAV_IXCSDR 0x8c2e |
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23 #define PCI_CHIP_SUPSAV_IXCDDR 0x8c2f |
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24 #endif |
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25 #ifndef PCI_CHIP_PROSAVAGE_DDR |
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26 #define PCI_CHIP_PROSAVAGE_DDR 0x8d03 |
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27 #define PCI_CHIP_PROSAVAGE_DDRK 0x8d04 |
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28 #endif |
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29 |
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30 #define S3_SAVAGE3D_SERIES(chip) ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE_MX)) |
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31 |
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32 #define S3_SAVAGE4_SERIES(chip) ((chip==S3_SAVAGE4) || (chip==S3_PROSAVAGE)) |
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33 |
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34 #define S3_SAVAGE_MOBILE_SERIES(chip) ((chip==S3_SAVAGE_MX) || (chip==S3_SUPERSAVAGE)) |
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35 |
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36 #define S3_SAVAGE_SERIES(chip) ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE2000)) |
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37 |
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38 |
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39 /* Chip tags. These are used to group the adapters into |
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40 * related families. |
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41 */ |
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42 |
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43 |
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44 enum S3CHIPTAGS { |
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45 S3_UNKNOWN = 0, |
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46 S3_SAVAGE3D, |
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47 S3_SAVAGE_MX, |
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48 S3_SAVAGE4, |
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49 S3_PROSAVAGE, |
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50 S3_SUPERSAVAGE, |
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51 S3_SAVAGE2000, |
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52 S3_LAST |
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53 }; |
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54 |
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55 typedef struct { |
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56 unsigned int mode, refresh; |
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57 unsigned char SR08, SR0E, SR0F; |
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58 unsigned char SR10, SR11, SR12, SR13, SR15, SR18, SR1B, SR29, SR30; |
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59 unsigned char SR54[8]; |
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60 unsigned char Clock; |
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61 unsigned char CR31, CR32, CR33, CR34, CR36, CR3A, CR3B, CR3C; |
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62 unsigned char CR40, CR41, CR42, CR43, CR45; |
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63 unsigned char CR50, CR51, CR53, CR55, CR58, CR5B, CR5D, CR5E; |
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64 unsigned char CR60, CR63, CR65, CR66, CR67, CR68, CR69, CR6D, CR6F; |
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65 unsigned char CR86, CR88; |
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66 unsigned char CR90, CR91, CRB0; |
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67 unsigned int STREAMS[22]; /* yuck, streams regs */ |
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68 unsigned int MMPR0, MMPR1, MMPR2, MMPR3; |
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69 } SavageRegRec, *SavageRegPtr; |
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70 |
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71 |
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72 |
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73 #define BIOS_BSIZE 1024 |
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74 #define BIOS_BASE 0xc0000 |
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75 |
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76 #define SAVAGE_NEWMMIO_REGBASE_S3 0x1000000 /* 16MB */ |
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77 #define SAVAGE_NEWMMIO_REGBASE_S4 0x0000000 |
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78 #define SAVAGE_NEWMMIO_REGSIZE 0x0080000 /* 512kb */ |
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79 #define SAVAGE_NEWMMIO_VGABASE 0x8000 |
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80 |
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81 #define BASE_FREQ 14.31818 |
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82 |
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83 #define FIFO_CONTROL_REG 0x8200 |
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84 #define MIU_CONTROL_REG 0x8204 |
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85 #define STREAMS_TIMEOUT_REG 0x8208 |
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86 #define MISC_TIMEOUT_REG 0x820c |
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87 |
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88 /* Stream Processor 1 */ |
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89 |
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90 /* Primary Stream 1 Frame Buffer Address 0 */ |
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91 #define PRI_STREAM_FBUF_ADDR0 0x81c0 |
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92 /* Primary Stream 1 Frame Buffer Address 0 */ |
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93 #define PRI_STREAM_FBUF_ADDR1 0x81c4 |
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94 /* Primary Stream 1 Stride */ |
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95 #define PRI_STREAM_STRIDE 0x81c8 |
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96 /* Primary Stream 1 Frame Buffer Size */ |
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97 #define PRI_STREAM_BUFFERSIZE 0x8214 |
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98 |
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99 /* Secondary stream 1 Color/Chroma Key Control */ |
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100 #define SEC_STREAM_CKEY_LOW 0x8184 |
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101 /* Secondary stream 1 Chroma Key Upper Bound */ |
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102 #define SEC_STREAM_CKEY_UPPER 0x8194 |
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103 /* Blend Control of Secondary Stream 1 & 2 */ |
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104 #define BLEND_CONTROL 0x8190 |
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105 /* Secondary Stream 1 Color conversion/Adjustment 1 */ |
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106 #define SEC_STREAM_COLOR_CONVERT1 0x8198 |
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107 /* Secondary Stream 1 Color conversion/Adjustment 2 */ |
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108 #define SEC_STREAM_COLOR_CONVERT2 0x819c |
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109 /* Secondary Stream 1 Color conversion/Adjustment 3 */ |
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110 #define SEC_STREAM_COLOR_CONVERT3 0x81e4 |
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111 /* Secondary Stream 1 Horizontal Scaling */ |
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112 #define SEC_STREAM_HSCALING 0x81a0 |
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113 /* Secondary Stream 1 Frame Buffer Size */ |
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114 #define SEC_STREAM_BUFFERSIZE 0x81a8 |
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115 /* Secondary Stream 1 Horizontal Scaling Normalization (2K only) */ |
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116 #define SEC_STREAM_HSCALE_NORMALIZE 0x81ac |
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117 /* Secondary Stream 1 Horizontal Scaling */ |
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118 #define SEC_STREAM_VSCALING 0x81e8 |
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119 /* Secondary Stream 1 Frame Buffer Address 0 */ |
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120 #define SEC_STREAM_FBUF_ADDR0 0x81d0 |
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121 /* Secondary Stream 1 Frame Buffer Address 1 */ |
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122 #define SEC_STREAM_FBUF_ADDR1 0x81d4 |
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123 /* Secondary Stream 1 Frame Buffer Address 2 */ |
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124 #define SEC_STREAM_FBUF_ADDR2 0x81ec |
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125 /* Secondary Stream 1 Stride */ |
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126 #define SEC_STREAM_STRIDE 0x81d8 |
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127 /* Secondary Stream 1 Window Start Coordinates */ |
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128 #define SEC_STREAM_WINDOW_START 0x81f8 |
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129 /* Secondary Stream 1 Window Size */ |
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130 #define SEC_STREAM_WINDOW_SZ 0x81fc |
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131 /* Secondary Streams Tile Offset */ |
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132 #define SEC_STREAM_TILE_OFF 0x821c |
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133 /* Secondary Stream 1 Opaque Overlay Control */ |
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134 #define SEC_STREAM_OPAQUE_OVERLAY 0x81dc |
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135 |
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136 |
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137 /* Stream Processor 2 */ |
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138 |
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139 /* Primary Stream 2 Frame Buffer Address 0 */ |
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140 #define PRI_STREAM2_FBUF_ADDR0 0x81b0 |
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141 /* Primary Stream 2 Frame Buffer Address 1 */ |
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142 #define PRI_STREAM2_FBUF_ADDR1 0x81b4 |
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143 /* Primary Stream 2 Stride */ |
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144 #define PRI_STREAM2_STRIDE 0x81b8 |
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145 /* Primary Stream 2 Frame Buffer Size */ |
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146 #define PRI_STREAM2_BUFFERSIZE 0x8218 |
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147 |
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148 /* Secondary Stream 2 Color/Chroma Key Control */ |
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149 #define SEC_STREAM2_CKEY_LOW 0x8188 |
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150 /* Secondary Stream 2 Chroma Key Upper Bound */ |
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151 #define SEC_STREAM2_CKEY_UPPER 0x818c |
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152 /* Secondary Stream 2 Horizontal Scaling */ |
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153 #define SEC_STREAM2_HSCALING 0x81a4 |
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154 /* Secondary Stream 2 Horizontal Scaling */ |
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155 #define SEC_STREAM2_VSCALING 0x8204 |
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156 /* Secondary Stream 2 Frame Buffer Size */ |
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157 #define SEC_STREAM2_BUFFERSIZE 0x81ac |
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158 /* Secondary Stream 2 Frame Buffer Address 0 */ |
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159 #define SEC_STREAM2_FBUF_ADDR0 0x81bc |
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160 /* Secondary Stream 2 Frame Buffer Address 1 */ |
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161 #define SEC_STREAM2_FBUF_ADDR1 0x81e0 |
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162 /* Secondary Stream 2 Frame Buffer Address 2 */ |
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163 #define SEC_STREAM2_FBUF_ADDR2 0x8208 |
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164 /* Multiple Buffer/LPB and Secondary Stream 2 Stride */ |
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165 #define SEC_STREAM2_STRIDE_LPB 0x81cc |
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166 /* Secondary Stream 2 Color conversion/Adjustment 1 */ |
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167 #define SEC_STREAM2_COLOR_CONVERT1 0x81f0 |
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168 /* Secondary Stream 2 Color conversion/Adjustment 2 */ |
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169 #define SEC_STREAM2_COLOR_CONVERT2 0x81f4 |
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170 /* Secondary Stream 2 Color conversion/Adjustment 3 */ |
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171 #define SEC_STREAM2_COLOR_CONVERT3 0x8200 |
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172 /* Secondary Stream 2 Window Start Coordinates */ |
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173 #define SEC_STREAM2_WINDOW_START 0x820c |
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174 /* Secondary Stream 2 Window Size */ |
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175 #define SEC_STREAM2_WINDOW_SZ 0x8210 |
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176 /* Secondary Stream 2 Opaque Overlay Control */ |
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177 #define SEC_STREAM2_OPAQUE_OVERLAY 0x8180 |
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178 |
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179 |
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180 /* savage 2000 */ |
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181 #define SEC_STREAM_COLOR_CONVERT0_2000 0x8198 |
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182 #define SEC_STREAM_COLOR_CONVERT1_2000 0x819c |
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183 #define SEC_STREAM_COLOR_CONVERT2_2000 0x81e0 |
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184 #define SEC_STREAM_COLOR_CONVERT3_2000 0x81e4 |
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185 |
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186 #define SUBSYS_STAT_REG 0x8504 |
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187 |
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188 #define SRC_BASE 0xa4d4 |
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189 #define DEST_BASE 0xa4d8 |
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190 #define CLIP_L_R 0xa4dc |
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191 #define CLIP_T_B 0xa4e0 |
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192 #define DEST_SRC_STR 0xa4e4 |
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193 #define MONO_PAT_0 0xa4e8 |
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194 #define MONO_PAT_1 0xa4ec |
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195 |
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196 /* Constants for CR69. */ |
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197 |
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198 #define CRT_ACTIVE 0x01 |
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199 #define LCD_ACTIVE 0x02 |
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200 #define TV_ACTIVE 0x04 |
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201 #define CRT_ATTACHED 0x10 |
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202 #define LCD_ATTACHED 0x20 |
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203 #define TV_ATTACHED 0x40 |
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204 |
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205 |
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206 /* |
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207 * reads from SUBSYS_STAT |
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208 */ |
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209 #define STATUS_WORD0 (INREG(0x48C00)) |
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210 #define ALT_STATUS_WORD0 (INREG(0x48C60)) |
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211 #define MAXLOOP 0xffffff |
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212 #define IN_SUBSYS_STAT() (INREG(SUBSYS_STAT_REG)) |
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213 |
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214 #define MAXFIFO 0x7f00 |
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215 |
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216 /* |
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217 * NOTE: don't remove 'VGAIN8(vgaCRIndex);'. |
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218 * If not present it will cause lockups on Savage4. |
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219 * Ask S3, why. |
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220 */ |
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221 /*#define VerticalRetraceWait() \ |
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222 { \ |
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223 VGAIN8(0x3d0+4); \ |
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224 VGAOUT8(0x3d0+4, 0x17); \ |
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225 if (VGAIN8(0x3d0+5) & 0x80) { \ |
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226 while ((VGAIN8(0x3d0 + 0x0a) & 0x08) == 0x08) ; \ |
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227 while ((VGAIN8(0x3d0 + 0x0a) & 0x08) == 0x00) ; \ |
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228 } \ |
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229 } |
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230 */ |
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231 |
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232 #define VerticalRetraceWait() \ |
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233 do { \ |
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234 VGAIN8(0x3d4); \ |
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235 VGAOUT8(0x3d4, 0x17); \ |
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236 if (VGAIN8(0x3d5) & 0x80) { \ |
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237 int i = 0x10000; \ |
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238 while ((VGAIN8(0x3da) & 0x08) == 0x08 && i--) ; \ |
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239 i = 0x10000; \ |
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240 while ((VGAIN8(0x3da) & 0x08) == 0x00 && i--) ; \ |
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241 } \ |
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242 } while (0) |
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243 |
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244 |
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245 #define I2C_REG 0xa0 |
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246 #define InI2CREG(a) \ |
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247 { \ |
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248 VGAOUT8(0x3d0 + 4, I2C_REG); \ |
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249 a = VGAIN8(0x3d0 + 5); \ |
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250 } |
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251 |
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252 #define OutI2CREG(a) \ |
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253 { \ |
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254 VGAOUT8(0x3d0 + 4, I2C_REG); \ |
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255 VGAOUT8(0x3d0 + 5, a); \ |
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256 } |
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257 |
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258 #define HZEXP_COMP_1 0x54 |
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259 #define HZEXP_BORDER 0x58 |
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260 #define HZEXP_FACTOR_IGA1 0x59 |
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261 |
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262 #define VTEXP_COMP_1 0x56 |
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263 #define VTEXP_BORDER 0x5a |
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264 #define VTEXP_FACTOR_IGA1 0x5b |
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265 |
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266 #define EC1_CENTER_ON 0x10 |
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267 #define EC1_EXPAND_ON 0x0c |
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268 |
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269 #define MODE_24 24 |
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270 |
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271 #if (MODE_24 == 32) |
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272 # define BYTES_PP24 4 |
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273 #else |
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274 # define BYTES_PP24 3 |
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275 #endif |
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276 |
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277 #define OVERLAY_DEPTH 16 |
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278 |
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279 #define STREAMS_MODE32 0x7 |
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280 #define STREAMS_MODE24 0x6 |
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281 #define STREAMS_MODE16 0x5 /* @@@ */ |
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282 |
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283 |
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284 #define DEPTH_BPP(depth) (depth == 24 ? (BYTES_PP24 << 3) : (depth + 7) & ~0x7) |
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285 #define DEPTH_2ND(depth) (depth > 8 ? depth\ |
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286 : OVERLAY_DEPTH) |
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287 #define SSTREAMS_MODE(bpp) (bpp > 16 ? (bpp > 24 ? STREAMS_MODE32 :\ |
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288 STREAMS_MODE24) : STREAMS_MODE16) |
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289 |
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290 #define HSCALING_Shift 0 |
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291 #define HSCALING_Mask (((1L << 16)-1) << HSCALING_Shift) |
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292 #define HSCALING(w0,w1) ((((unsigned int)(((double)w0/(double)w1) * (1 << 15))) \ |
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293 << HSCALING_Shift) \ |
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294 & HSCALING_Mask) |
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295 |
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296 #define VSCALING_Shift 0 |
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297 #define VSCALING_Mask (((1L << 20)-1) << VSCALING_Shift) |
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298 #define VSCALING(h0,h1) ((((unsigned int) (((double)h0/(double)h1) * (1 << 15))) \ |
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299 << VSCALING_Shift) \ |
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300 & VSCALING_Mask) |
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301 |
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302 |
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303 #endif /* _SAVAGE_REGS_H */ |