Mercurial > mplayer.hg
annotate libvo/aclib_template.c @ 25563:1e9ef4ed8e8f
Relicense file to GPL v2 or later with the permission of Rudolf Marek,
the author and update his email contact address.
author | diego |
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date | Wed, 02 Jan 2008 23:35:19 +0000 |
parents | ef54df9f07d3 |
children | ef4297ed0d12 |
rev | line source |
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1 /* |
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2 aclib - advanced C library ;) |
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3 This file contains functions which improve and expand standard C-library |
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4 */ |
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5 |
1123 | 6 #ifndef HAVE_SSE2 |
7 /* | |
8 P3 processor has only one SSE decoder so can execute only 1 sse insn per | |
9 cpu clock, but it has 3 mmx decoders (include load/store unit) | |
10 and executes 3 mmx insns per cpu clock. | |
11 P4 processor has some chances, but after reading: | |
12 http://www.emulators.com/pentium4.htm | |
13 I have doubts. Anyway SSE2 version of this code can be written better. | |
14 */ | |
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15 #undef HAVE_SSE |
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16 #endif |
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17 |
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18 |
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19 /* |
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20 This part of code was taken by me from Linux-2.4.3 and slightly modified |
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21 for MMX, MMX2, SSE instruction set. I have done it since linux uses page aligned |
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22 blocks but mplayer uses weakly ordered data and original sources can not |
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23 speedup them. Only using PREFETCHNTA and MOVNTQ together have effect! |
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24 |
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25 >From IA-32 Intel Architecture Software Developer's Manual Volume 1, |
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26 |
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27 Order Number 245470: |
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28 "10.4.6. Cacheability Control, Prefetch, and Memory Ordering Instructions" |
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29 |
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30 Data referenced by a program can be temporal (data will be used again) or |
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31 non-temporal (data will be referenced once and not reused in the immediate |
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32 future). To make efficient use of the processor's caches, it is generally |
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33 desirable to cache temporal data and not cache non-temporal data. Overloading |
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34 the processor's caches with non-temporal data is sometimes referred to as |
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35 "polluting the caches". |
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36 The non-temporal data is written to memory with Write-Combining semantics. |
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37 |
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38 The PREFETCHh instructions permits a program to load data into the processor |
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39 at a suggested cache level, so that it is closer to the processors load and |
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40 store unit when it is needed. If the data is already present in a level of |
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41 the cache hierarchy that is closer to the processor, the PREFETCHh instruction |
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42 will not result in any data movement. |
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43 But we should you PREFETCHNTA: Non-temporal data fetch data into location |
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44 close to the processor, minimizing cache pollution. |
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45 |
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46 The MOVNTQ (store quadword using non-temporal hint) instruction stores |
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47 packed integer data from an MMX register to memory, using a non-temporal hint. |
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48 The MOVNTPS (store packed single-precision floating-point values using |
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49 non-temporal hint) instruction stores packed floating-point data from an |
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50 XMM register to memory, using a non-temporal hint. |
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51 |
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52 The SFENCE (Store Fence) instruction controls write ordering by creating a |
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53 fence for memory store operations. This instruction guarantees that the results |
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54 of every store instruction that precedes the store fence in program order is |
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55 globally visible before any store instruction that follows the fence. The |
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56 SFENCE instruction provides an efficient way of ensuring ordering between |
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57 procedures that produce weakly-ordered data and procedures that consume that |
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58 data. |
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59 |
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60 If you have questions please contact with me: Nick Kurshev: nickols_k@mail.ru. |
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61 */ |
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62 |
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63 // 3dnow memcpy support from kernel 2.4.2 |
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64 // by Pontscho/fresh!mindworkz |
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65 |
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66 |
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67 #undef HAVE_ONLY_MMX1 |
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68 #if defined(HAVE_MMX) && !defined(HAVE_MMX2) && !defined(HAVE_3DNOW) && !defined(HAVE_SSE) |
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69 /* means: mmx v.1. Note: Since we added alignment of destinition it speedups |
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70 of memory copying on PentMMX, Celeron-1 and P2 upto 12% versus |
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71 standard (non MMX-optimized) version. |
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72 Note: on K6-2+ it speedups memory copying upto 25% and |
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73 on K7 and P3 about 500% (5 times). */ |
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74 #define HAVE_ONLY_MMX1 |
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75 #endif |
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76 |
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77 |
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78 #undef HAVE_K6_2PLUS |
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79 #if !defined( HAVE_MMX2) && defined( HAVE_3DNOW) |
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80 #define HAVE_K6_2PLUS |
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81 #endif |
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82 |
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83 /* for small memory blocks (<256 bytes) this version is faster */ |
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84 #define small_memcpy(to,from,n)\ |
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85 {\ |
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86 register unsigned long int dummy;\ |
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87 __asm__ __volatile__(\ |
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88 "rep; movsb"\ |
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89 :"=&D"(to), "=&S"(from), "=&c"(dummy)\ |
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90 /* It's most portable way to notify compiler */\ |
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91 /* that edi, esi and ecx are clobbered in asm block. */\ |
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92 /* Thanks to A'rpi for hint!!! */\ |
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93 :"0" (to), "1" (from),"2" (n)\ |
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94 : "memory");\ |
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95 } |
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96 |
3393 | 97 #undef MMREG_SIZE |
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98 #ifdef HAVE_SSE |
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99 #define MMREG_SIZE 16 |
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100 #else |
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101 #define MMREG_SIZE 64 //8 |
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102 #endif |
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103 |
3393 | 104 #undef PREFETCH |
105 #undef EMMS | |
5660 | 106 |
5662 | 107 #ifdef HAVE_MMX2 |
108 #define PREFETCH "prefetchnta" | |
109 #elif defined ( HAVE_3DNOW ) | |
5660 | 110 #define PREFETCH "prefetch" |
111 #else | |
112 #define PREFETCH "/nop" | |
113 #endif | |
114 | |
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115 /* On K6 femms is faster of emms. On K7 femms is directly mapped on emms. */ |
5660 | 116 #ifdef HAVE_3DNOW |
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117 #define EMMS "femms" |
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118 #else |
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119 #define EMMS "emms" |
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120 #endif |
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121 |
3393 | 122 #undef MOVNTQ |
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123 #ifdef HAVE_MMX2 |
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124 #define MOVNTQ "movntq" |
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125 #else |
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126 #define MOVNTQ "movq" |
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127 #endif |
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128 |
3393 | 129 #undef MIN_LEN |
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130 #ifdef HAVE_ONLY_MMX1 |
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131 #define MIN_LEN 0x800 /* 2K blocks */ |
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132 #else |
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133 #define MIN_LEN 0x40 /* 64-byte blocks */ |
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134 #endif |
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135 |
7072 | 136 static void * RENAME(fast_memcpy)(void * to, const void * from, size_t len) |
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137 { |
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138 void *retval; |
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139 size_t i; |
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140 retval = to; |
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141 #ifdef STATISTICS |
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142 { |
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143 static int freq[33]; |
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144 static int t=0; |
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145 int i; |
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146 for(i=0; len>(1<<i); i++); |
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147 freq[i]++; |
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148 t++; |
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149 if(1024*1024*1024 % t == 0) |
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150 for(i=0; i<32; i++) |
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151 printf("freq < %8d %4d\n", 1<<i, freq[i]); |
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152 } |
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153 #endif |
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154 #ifndef HAVE_ONLY_MMX1 |
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155 /* PREFETCH has effect even for MOVSB instruction ;) */ |
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156 __asm__ __volatile__ ( |
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157 PREFETCH" (%0)\n" |
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158 PREFETCH" 64(%0)\n" |
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159 PREFETCH" 128(%0)\n" |
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160 PREFETCH" 192(%0)\n" |
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161 PREFETCH" 256(%0)\n" |
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162 : : "r" (from) ); |
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163 #endif |
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164 if(len >= MIN_LEN) |
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165 { |
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166 register unsigned long int delta; |
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167 /* Align destinition to MMREG_SIZE -boundary */ |
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168 delta = ((unsigned long int)to)&(MMREG_SIZE-1); |
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169 if(delta) |
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170 { |
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171 delta=MMREG_SIZE-delta; |
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172 len -= delta; |
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173 small_memcpy(to, from, delta); |
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174 } |
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175 i = len >> 6; /* len/64 */ |
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176 len&=63; |
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177 /* |
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178 This algorithm is top effective when the code consequently |
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179 reads and writes blocks which have size of cache line. |
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180 Size of cache line is processor-dependent. |
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181 It will, however, be a minimum of 32 bytes on any processors. |
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182 It would be better to have a number of instructions which |
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183 perform reading and writing to be multiple to a number of |
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184 processor's decoders, but it's not always possible. |
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185 */ |
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186 #ifdef HAVE_SSE /* Only P3 (may be Cyrix3) */ |
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187 if(((unsigned long)from) & 15) |
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188 /* if SRC is misaligned */ |
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189 for(; i>0; i--) |
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190 { |
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191 __asm__ __volatile__ ( |
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192 PREFETCH" 320(%0)\n" |
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193 "movups (%0), %%xmm0\n" |
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194 "movups 16(%0), %%xmm1\n" |
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195 "movups 32(%0), %%xmm2\n" |
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196 "movups 48(%0), %%xmm3\n" |
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197 "movntps %%xmm0, (%1)\n" |
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198 "movntps %%xmm1, 16(%1)\n" |
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199 "movntps %%xmm2, 32(%1)\n" |
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200 "movntps %%xmm3, 48(%1)\n" |
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201 :: "r" (from), "r" (to) : "memory"); |
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202 from=((const unsigned char *) from)+64; |
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203 to=((unsigned char *)to)+64; |
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204 } |
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205 else |
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206 /* |
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207 Only if SRC is aligned on 16-byte boundary. |
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208 It allows to use movaps instead of movups, which required data |
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209 to be aligned or a general-protection exception (#GP) is generated. |
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210 */ |
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211 for(; i>0; i--) |
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212 { |
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213 __asm__ __volatile__ ( |
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214 PREFETCH" 320(%0)\n" |
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215 "movaps (%0), %%xmm0\n" |
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216 "movaps 16(%0), %%xmm1\n" |
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217 "movaps 32(%0), %%xmm2\n" |
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218 "movaps 48(%0), %%xmm3\n" |
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219 "movntps %%xmm0, (%1)\n" |
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220 "movntps %%xmm1, 16(%1)\n" |
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221 "movntps %%xmm2, 32(%1)\n" |
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222 "movntps %%xmm3, 48(%1)\n" |
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223 :: "r" (from), "r" (to) : "memory"); |
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224 from=((const unsigned char *)from)+64; |
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225 to=((unsigned char *)to)+64; |
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226 } |
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227 #else |
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228 // Align destination at BLOCK_SIZE boundary |
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229 for(; ((int)to & (BLOCK_SIZE-1)) && i>0; i--) |
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230 { |
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231 __asm__ __volatile__ ( |
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232 #ifndef HAVE_ONLY_MMX1 |
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233 PREFETCH" 320(%0)\n" |
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234 #endif |
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235 "movq (%0), %%mm0\n" |
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236 "movq 8(%0), %%mm1\n" |
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237 "movq 16(%0), %%mm2\n" |
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238 "movq 24(%0), %%mm3\n" |
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239 "movq 32(%0), %%mm4\n" |
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240 "movq 40(%0), %%mm5\n" |
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241 "movq 48(%0), %%mm6\n" |
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242 "movq 56(%0), %%mm7\n" |
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243 MOVNTQ" %%mm0, (%1)\n" |
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244 MOVNTQ" %%mm1, 8(%1)\n" |
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245 MOVNTQ" %%mm2, 16(%1)\n" |
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246 MOVNTQ" %%mm3, 24(%1)\n" |
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247 MOVNTQ" %%mm4, 32(%1)\n" |
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248 MOVNTQ" %%mm5, 40(%1)\n" |
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249 MOVNTQ" %%mm6, 48(%1)\n" |
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250 MOVNTQ" %%mm7, 56(%1)\n" |
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251 :: "r" (from), "r" (to) : "memory"); |
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253 to=((unsigned char *)to)+64; | |
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254 } |
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255 |
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256 // printf(" %d %d\n", (int)from&1023, (int)to&1023); |
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257 // Pure Assembly cuz gcc is a bit unpredictable ;) |
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258 if(i>=BLOCK_SIZE/64) |
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259 asm volatile( |
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260 "xor %%"REG_a", %%"REG_a" \n\t" |
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261 ".balign 16 \n\t" |
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262 "1: \n\t" |
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263 "movl (%0, %%"REG_a"), %%ebx \n\t" |
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264 "movl 32(%0, %%"REG_a"), %%ebx \n\t" |
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265 "movl 64(%0, %%"REG_a"), %%ebx \n\t" |
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266 "movl 96(%0, %%"REG_a"), %%ebx \n\t" |
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267 "add $128, %%"REG_a" \n\t" |
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268 "cmp %3, %%"REG_a" \n\t" |
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269 " jb 1b \n\t" |
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270 |
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271 "xor %%"REG_a", %%"REG_a" \n\t" |
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272 |
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273 ".balign 16 \n\t" |
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274 "2: \n\t" |
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275 "movq (%0, %%"REG_a"), %%mm0\n" |
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276 "movq 8(%0, %%"REG_a"), %%mm1\n" |
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277 "movq 16(%0, %%"REG_a"), %%mm2\n" |
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278 "movq 24(%0, %%"REG_a"), %%mm3\n" |
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279 "movq 32(%0, %%"REG_a"), %%mm4\n" |
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280 "movq 40(%0, %%"REG_a"), %%mm5\n" |
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281 "movq 48(%0, %%"REG_a"), %%mm6\n" |
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282 "movq 56(%0, %%"REG_a"), %%mm7\n" |
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283 MOVNTQ" %%mm0, (%1, %%"REG_a")\n" |
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284 MOVNTQ" %%mm1, 8(%1, %%"REG_a")\n" |
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285 MOVNTQ" %%mm2, 16(%1, %%"REG_a")\n" |
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286 MOVNTQ" %%mm3, 24(%1, %%"REG_a")\n" |
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287 MOVNTQ" %%mm4, 32(%1, %%"REG_a")\n" |
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288 MOVNTQ" %%mm5, 40(%1, %%"REG_a")\n" |
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289 MOVNTQ" %%mm6, 48(%1, %%"REG_a")\n" |
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290 MOVNTQ" %%mm7, 56(%1, %%"REG_a")\n" |
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291 "add $64, %%"REG_a" \n\t" |
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292 "cmp %3, %%"REG_a" \n\t" |
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293 "jb 2b \n\t" |
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294 |
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295 #if CONFUSION_FACTOR > 0 |
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296 // a few percent speedup on out of order executing CPUs |
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297 "mov %5, %%"REG_a" \n\t" |
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298 "2: \n\t" |
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299 "movl (%0), %%ebx \n\t" |
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300 "movl (%0), %%ebx \n\t" |
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301 "movl (%0), %%ebx \n\t" |
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302 "movl (%0), %%ebx \n\t" |
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303 "dec %%"REG_a" \n\t" |
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304 " jnz 2b \n\t" |
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305 #endif |
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306 |
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307 "xor %%"REG_a", %%"REG_a" \n\t" |
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308 "add %3, %0 \n\t" |
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309 "add %3, %1 \n\t" |
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310 "sub %4, %2 \n\t" |
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311 "cmp %4, %2 \n\t" |
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312 " jae 1b \n\t" |
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313 : "+r" (from), "+r" (to), "+r" (i) |
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314 : "r" ((long)BLOCK_SIZE), "i" (BLOCK_SIZE/64), "i" ((long)CONFUSION_FACTOR) |
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315 : "%"REG_a, "%ebx" |
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316 ); |
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317 |
698
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318 for(; i>0; i--) |
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319 { |
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320 __asm__ __volatile__ ( |
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321 #ifndef HAVE_ONLY_MMX1 |
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322 PREFETCH" 320(%0)\n" |
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323 #endif |
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324 "movq (%0), %%mm0\n" |
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325 "movq 8(%0), %%mm1\n" |
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326 "movq 16(%0), %%mm2\n" |
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327 "movq 24(%0), %%mm3\n" |
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328 "movq 32(%0), %%mm4\n" |
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329 "movq 40(%0), %%mm5\n" |
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330 "movq 48(%0), %%mm6\n" |
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331 "movq 56(%0), %%mm7\n" |
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332 MOVNTQ" %%mm0, (%1)\n" |
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333 MOVNTQ" %%mm1, 8(%1)\n" |
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334 MOVNTQ" %%mm2, 16(%1)\n" |
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335 MOVNTQ" %%mm3, 24(%1)\n" |
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336 MOVNTQ" %%mm4, 32(%1)\n" |
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337 MOVNTQ" %%mm5, 40(%1)\n" |
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338 MOVNTQ" %%mm6, 48(%1)\n" |
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339 MOVNTQ" %%mm7, 56(%1)\n" |
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340 :: "r" (from), "r" (to) : "memory"); |
15639 | 341 from=((const unsigned char *)from)+64; |
342 to=((unsigned char *)to)+64; | |
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343 } |
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344 |
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345 #endif /* Have SSE */ |
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346 #ifdef HAVE_MMX2 |
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347 /* since movntq is weakly-ordered, a "sfence" |
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348 * is needed to become ordered again. */ |
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349 __asm__ __volatile__ ("sfence":::"memory"); |
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350 #endif |
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351 #ifndef HAVE_SSE |
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352 /* enables to use FPU */ |
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353 __asm__ __volatile__ (EMMS:::"memory"); |
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354 #endif |
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355 } |
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356 /* |
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357 * Now do the tail of the block |
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358 */ |
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359 if(len) small_memcpy(to, from, len); |
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360 return retval; |
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361 } |
4681 | 362 |
363 /** | |
364 * special copy routine for mem -> agp/pci copy (based upon fast_memcpy) | |
365 */ | |
7072 | 366 static void * RENAME(mem2agpcpy)(void * to, const void * from, size_t len) |
4681 | 367 { |
368 void *retval; | |
369 size_t i; | |
370 retval = to; | |
371 #ifdef STATISTICS | |
372 { | |
373 static int freq[33]; | |
374 static int t=0; | |
375 int i; | |
376 for(i=0; len>(1<<i); i++); | |
377 freq[i]++; | |
378 t++; | |
379 if(1024*1024*1024 % t == 0) | |
380 for(i=0; i<32; i++) | |
381 printf("mem2agp freq < %8d %4d\n", 1<<i, freq[i]); | |
382 } | |
383 #endif | |
384 if(len >= MIN_LEN) | |
385 { | |
386 register unsigned long int delta; | |
387 /* Align destinition to MMREG_SIZE -boundary */ | |
388 delta = ((unsigned long int)to)&7; | |
389 if(delta) | |
390 { | |
391 delta=8-delta; | |
392 len -= delta; | |
393 small_memcpy(to, from, delta); | |
394 } | |
395 i = len >> 6; /* len/64 */ | |
396 len &= 63; | |
397 /* | |
398 This algorithm is top effective when the code consequently | |
399 reads and writes blocks which have size of cache line. | |
400 Size of cache line is processor-dependent. | |
401 It will, however, be a minimum of 32 bytes on any processors. | |
402 It would be better to have a number of instructions which | |
403 perform reading and writing to be multiple to a number of | |
404 processor's decoders, but it's not always possible. | |
405 */ | |
406 for(; i>0; i--) | |
407 { | |
408 __asm__ __volatile__ ( | |
409 PREFETCH" 320(%0)\n" | |
410 "movq (%0), %%mm0\n" | |
411 "movq 8(%0), %%mm1\n" | |
412 "movq 16(%0), %%mm2\n" | |
413 "movq 24(%0), %%mm3\n" | |
414 "movq 32(%0), %%mm4\n" | |
415 "movq 40(%0), %%mm5\n" | |
416 "movq 48(%0), %%mm6\n" | |
417 "movq 56(%0), %%mm7\n" | |
418 MOVNTQ" %%mm0, (%1)\n" | |
419 MOVNTQ" %%mm1, 8(%1)\n" | |
420 MOVNTQ" %%mm2, 16(%1)\n" | |
421 MOVNTQ" %%mm3, 24(%1)\n" | |
422 MOVNTQ" %%mm4, 32(%1)\n" | |
423 MOVNTQ" %%mm5, 40(%1)\n" | |
424 MOVNTQ" %%mm6, 48(%1)\n" | |
425 MOVNTQ" %%mm7, 56(%1)\n" | |
426 :: "r" (from), "r" (to) : "memory"); | |
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427 from=((const unsigned char *)from)+64; |
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428 to=((unsigned char *)to)+64; |
4681 | 429 } |
430 #ifdef HAVE_MMX2 | |
431 /* since movntq is weakly-ordered, a "sfence" | |
432 * is needed to become ordered again. */ | |
433 __asm__ __volatile__ ("sfence":::"memory"); | |
434 #endif | |
435 /* enables to use FPU */ | |
436 __asm__ __volatile__ (EMMS:::"memory"); | |
437 } | |
438 /* | |
439 * Now do the tail of the block | |
440 */ | |
441 if(len) small_memcpy(to, from, len); | |
442 return retval; | |
443 } | |
444 |