annotate drivers/3dfx.h @ 28101:231f008859b9

Warning fixes for demux_nut
author ods15
date Fri, 12 Dec 2008 05:08:28 +0000
parents 0b4d8e4d4ed7
children a6b506faeb34
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1 /*
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2 * Copyright (C) Colin Cross Apr 2000
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3 * changed by zsteva Aug/Sep 2001, see vo_3dfx.c
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4 *
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5 * This file is part of MPlayer.
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6 *
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7 * MPlayer is free software; you can redistribute it and/or modify
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8 * it under the terms of the GNU General Public License as published by
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9 * the Free Software Foundation; either version 2 of the License, or
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10 * (at your option) any later version.
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11 *
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12 * MPlayer is distributed in the hope that it will be useful,
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13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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15 * GNU General Public License for more details.
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16 *
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17 * You should have received a copy of the GNU General Public License along
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18 * with MPlayer; if not, write to the Free Software Foundation, Inc.,
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19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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20 */
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21
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22 #ifndef MPLAYER_3DFX_H
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23 #define MPLAYER_3DFX_H
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24
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25 #define VOODOO_IO_REG_OFFSET ((unsigned long int)0x0000000)
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26 #define VOODOO_YUV_REG_OFFSET ((unsigned long int)0x0080100)
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27 #define VOODOO_AGP_REG_OFFSET ((unsigned long int)0x0080000)
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28 #define VOODOO_2D_REG_OFFSET ((unsigned long int)0x0100000)
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29 #define VOODOO_YUV_PLANE_OFFSET ((unsigned long int)0x0C00000)
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30
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31 #define VOODOO_BLT_FORMAT_YUYV (8<<16)
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32 #define VOODOO_BLT_FORMAT_UYVY (9<<16)
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33 #define VOODOO_BLT_FORMAT_16 (3<<16)
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34 #define VOODOO_BLT_FORMAT_24 (4<<16)
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35 #define VOODOO_BLT_FORMAT_32 (5<<16)
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36
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37 #define VOODOO_YUV_STRIDE (1024>>2)
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38
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39 struct voodoo_yuv_fb_t {
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40 uint32_t Y[0x0040000];
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41 uint32_t U[0x0040000];
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42 uint32_t V[0x0040000];
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43 };
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44
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45 struct voodoo_yuv_reg_t {
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46 uint32_t yuvBaseAddr;
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47 uint32_t yuvStride;
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48 };
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49
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50 struct voodoo_2d_reg_t {
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51 uint32_t status;
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52 uint32_t intCtrl;
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53 uint32_t clip0Min;
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54 uint32_t clip0Max;
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55 uint32_t dstBaseAddr;
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56 uint32_t dstFormat;
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57 uint32_t srcColorkeyMin;
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58 uint32_t srcColorkeyMax;
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59 uint32_t dstColorkeyMin;
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60 uint32_t dstColorkeyMax;
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61 signed long bresError0;
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62 signed long bresError1;
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63 uint32_t rop;
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64 uint32_t srcBaseAddr;
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65 uint32_t commandExtra;
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66 uint32_t lineStipple;
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67 uint32_t lineStyle;
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68 uint32_t pattern0Alias;
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69 uint32_t pattern1Alias;;
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70 uint32_t clip1Min;
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71 uint32_t clip1Max;
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72 uint32_t srcFormat;
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73 uint32_t srcSize;
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74 uint32_t srcXY;
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75 uint32_t colorBack;
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76 uint32_t colorFore;
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77 uint32_t dstSize;
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78 uint32_t dstXY;
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79 uint32_t command;
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80 uint32_t RESERVED1;
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81 uint32_t RESERVED2;
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82 uint32_t RESERVED3;
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83 uint8_t launchArea[128];
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84 };
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85
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86
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87 struct voodoo_io_reg_t {
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88 uint32_t status;
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89 uint32_t pciInit0;
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90 uint32_t sipMonitor;
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91 uint32_t lfbMemoryConfig;
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92 uint32_t miscInit0;
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93 uint32_t miscInit1;
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94 uint32_t dramInit0;
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95 uint32_t dramInit1;
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96 uint32_t agpInit;
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97 uint32_t tmuGbeInit;
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98 uint32_t vgaInit0;
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99 uint32_t vgaInit1;
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100 uint32_t dramCommand;
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101 uint32_t dramData;
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102 uint32_t RESERVED1;
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103 uint32_t RESERVED2;
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104
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105 uint32_t pllCtrl0;
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106 uint32_t pllCtrl1;
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107 uint32_t pllCtrl2;
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108 uint32_t dacMode;
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109 uint32_t dacAddr;
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110 uint32_t dacData;
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111
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112 uint32_t rgbMaxDelta;
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113 uint32_t vidProcCfg;
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114 uint32_t hwCurPatAddr;
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115 uint32_t hwCurLoc;
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116 uint32_t hwCurC0;
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117 uint32_t hwCurC1;
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118 uint32_t vidInFormat;
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119 uint32_t vidInStatus;
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120 uint32_t vidSerialParallelPort;
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121 uint32_t vidInXDecimDeltas;
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122 uint32_t vidInDecimInitErrs;
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123 uint32_t vidInYDecimDeltas;
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124 uint32_t vidPixelBufThold;
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125 uint32_t vidChromaMin;
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126 uint32_t vidChromaMax;
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127 uint32_t vidCurrentLine;
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128 uint32_t vidScreenSize;
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129 uint32_t vidOverlayStartCoords;
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130 uint32_t vidOverlayEndScreenCoord;
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131 uint32_t vidOverlayDudx;
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132 uint32_t vidOverlayDudxOffsetSrcWidth;
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133 uint32_t vidOverlayDvdy;
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134
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135 uint32_t vga_registers_not_mem_mapped[12];
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136 uint32_t vidOverlayDvdyOffset;
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137 uint32_t vidDesktopStartAddr;
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138 uint32_t vidDesktopOverlayStride;
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139 uint32_t vidInAddr0;
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140 uint32_t vidInAddr1;
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141 uint32_t vidInAddr2;
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142 uint32_t vidInStride;
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143 uint32_t vidCurrOverlayStartAddr;
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144 };
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145
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146
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147 struct pioData_t {
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148 short port;
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149 short size;
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150 int device;
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151 void *value;
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152 };
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153
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154 typedef struct pioData_t pioData;
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155 typedef struct voodoo_2d_reg_t voodoo_2d_reg;
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156 typedef struct voodoo_io_reg_t voodoo_io_reg;
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157 typedef struct voodoo_yuv_reg_t voodoo_yuv_reg;
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158 typedef struct voodoo_yuv_fb_t voodoo_yuv_fb;
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159
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160
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161 /* from linux/driver/video/tdfxfb.c, definition for 3dfx registers.
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162 *
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163 * author: Hannu Mallat <hmallat@cc.hut.fi>
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164 */
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165
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166 #ifndef PCI_DEVICE_ID_3DFX_VOODOO5
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167 #define PCI_DEVICE_ID_3DFX_VOODOO5 0x0009
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168 #endif
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169
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170 /* membase0 register offsets */
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171 #define STATUS 0x00
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172 #define PCIINIT0 0x04
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173 #define SIPMONITOR 0x08
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174 #define LFBMEMORYCONFIG 0x0c
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175 #define MISCINIT0 0x10
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176 #define MISCINIT1 0x14
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177 #define DRAMINIT0 0x18
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178 #define DRAMINIT1 0x1c
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179 #define AGPINIT 0x20
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180 #define TMUGBEINIT 0x24
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181 #define VGAINIT0 0x28
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182 #define VGAINIT1 0x2c
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183 #define DRAMCOMMAND 0x30
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184 #define DRAMDATA 0x34
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185 /* reserved 0x38 */
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186 /* reserved 0x3c */
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187 #define PLLCTRL0 0x40
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188 #define PLLCTRL1 0x44
4a08e7ac3f59 tdfxfb yuv driver by Zeljko Stevanovic <zsteva@ptt.yu>
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189 #define PLLCTRL2 0x48
4a08e7ac3f59 tdfxfb yuv driver by Zeljko Stevanovic <zsteva@ptt.yu>
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190 #define DACMODE 0x4c
4a08e7ac3f59 tdfxfb yuv driver by Zeljko Stevanovic <zsteva@ptt.yu>
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191 #define DACADDR 0x50
4a08e7ac3f59 tdfxfb yuv driver by Zeljko Stevanovic <zsteva@ptt.yu>
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192 #define DACDATA 0x54
4a08e7ac3f59 tdfxfb yuv driver by Zeljko Stevanovic <zsteva@ptt.yu>
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193 #define RGBMAXDELTA 0x58
4a08e7ac3f59 tdfxfb yuv driver by Zeljko Stevanovic <zsteva@ptt.yu>
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194 #define VIDPROCCFG 0x5c
4a08e7ac3f59 tdfxfb yuv driver by Zeljko Stevanovic <zsteva@ptt.yu>
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195 #define HWCURPATADDR 0x60
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196 #define HWCURLOC 0x64
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197 #define HWCURC0 0x68
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198 #define HWCURC1 0x6c
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199 #define VIDINFORMAT 0x70
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200 #define VIDINSTATUS 0x74
4a08e7ac3f59 tdfxfb yuv driver by Zeljko Stevanovic <zsteva@ptt.yu>
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201 #define VIDSERPARPORT 0x78
4a08e7ac3f59 tdfxfb yuv driver by Zeljko Stevanovic <zsteva@ptt.yu>
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202 #define VIDINXDELTA 0x7c
4a08e7ac3f59 tdfxfb yuv driver by Zeljko Stevanovic <zsteva@ptt.yu>
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203 #define VIDININITERR 0x80
4a08e7ac3f59 tdfxfb yuv driver by Zeljko Stevanovic <zsteva@ptt.yu>
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204 #define VIDINYDELTA 0x84
4a08e7ac3f59 tdfxfb yuv driver by Zeljko Stevanovic <zsteva@ptt.yu>
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205 #define VIDPIXBUFTHOLD 0x88
4a08e7ac3f59 tdfxfb yuv driver by Zeljko Stevanovic <zsteva@ptt.yu>
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206 #define VIDCHRMIN 0x8c
4a08e7ac3f59 tdfxfb yuv driver by Zeljko Stevanovic <zsteva@ptt.yu>
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207 #define VIDCHRMAX 0x90
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208 #define VIDCURLIN 0x94
4a08e7ac3f59 tdfxfb yuv driver by Zeljko Stevanovic <zsteva@ptt.yu>
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209 #define VIDSCREENSIZE 0x98
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210 #define VIDOVRSTARTCRD 0x9c
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211 #define VIDOVRENDCRD 0xa0
4a08e7ac3f59 tdfxfb yuv driver by Zeljko Stevanovic <zsteva@ptt.yu>
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212 #define VIDOVRDUDX 0xa4
4a08e7ac3f59 tdfxfb yuv driver by Zeljko Stevanovic <zsteva@ptt.yu>
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213 #define VIDOVRDUDXOFF 0xa8
4a08e7ac3f59 tdfxfb yuv driver by Zeljko Stevanovic <zsteva@ptt.yu>
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214 #define VIDOVRDVDY 0xac
4a08e7ac3f59 tdfxfb yuv driver by Zeljko Stevanovic <zsteva@ptt.yu>
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215 /* ... */
4a08e7ac3f59 tdfxfb yuv driver by Zeljko Stevanovic <zsteva@ptt.yu>
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216 #define VIDOVRDVDYOFF 0xe0
4a08e7ac3f59 tdfxfb yuv driver by Zeljko Stevanovic <zsteva@ptt.yu>
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217 #define VIDDESKSTART 0xe4
4a08e7ac3f59 tdfxfb yuv driver by Zeljko Stevanovic <zsteva@ptt.yu>
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218 #define VIDDESKSTRIDE 0xe8
4a08e7ac3f59 tdfxfb yuv driver by Zeljko Stevanovic <zsteva@ptt.yu>
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219 #define VIDINADDR0 0xec
4a08e7ac3f59 tdfxfb yuv driver by Zeljko Stevanovic <zsteva@ptt.yu>
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220 #define VIDINADDR1 0xf0
4a08e7ac3f59 tdfxfb yuv driver by Zeljko Stevanovic <zsteva@ptt.yu>
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221 #define VIDINADDR2 0xf4
4a08e7ac3f59 tdfxfb yuv driver by Zeljko Stevanovic <zsteva@ptt.yu>
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222 #define VIDINSTRIDE 0xf8
4a08e7ac3f59 tdfxfb yuv driver by Zeljko Stevanovic <zsteva@ptt.yu>
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223 #define VIDCUROVRSTART 0xfc
4a08e7ac3f59 tdfxfb yuv driver by Zeljko Stevanovic <zsteva@ptt.yu>
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224
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225 #define INTCTRL (0x00100000 + 0x04)
4a08e7ac3f59 tdfxfb yuv driver by Zeljko Stevanovic <zsteva@ptt.yu>
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226 #define CLIP0MIN (0x00100000 + 0x08)
4a08e7ac3f59 tdfxfb yuv driver by Zeljko Stevanovic <zsteva@ptt.yu>
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227 #define CLIP0MAX (0x00100000 + 0x0c)
4a08e7ac3f59 tdfxfb yuv driver by Zeljko Stevanovic <zsteva@ptt.yu>
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228 #define DSTBASE (0x00100000 + 0x10)
4a08e7ac3f59 tdfxfb yuv driver by Zeljko Stevanovic <zsteva@ptt.yu>
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229 #define DSTFORMAT (0x00100000 + 0x14)
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230 #define SRCCOLORKEYMIN (0x00100000 + 0x18)
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231 #define SRCCOLORKEYMAX (0x00100000 + 0x1c)
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232 #define DSTCOLORKEYMIN (0x00100000 + 0x20)
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233 #define DSTCOLORKEYMAX (0x00100000 + 0x24)
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234 #define ROP123 (0x00100000 + 0x30)
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4a08e7ac3f59 tdfxfb yuv driver by Zeljko Stevanovic <zsteva@ptt.yu>
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235 #define SRCBASE (0x00100000 + 0x34)
4a08e7ac3f59 tdfxfb yuv driver by Zeljko Stevanovic <zsteva@ptt.yu>
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236 #define COMMANDEXTRA_2D (0x00100000 + 0x38)
4a08e7ac3f59 tdfxfb yuv driver by Zeljko Stevanovic <zsteva@ptt.yu>
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237 #define CLIP1MIN (0x00100000 + 0x4c)
4a08e7ac3f59 tdfxfb yuv driver by Zeljko Stevanovic <zsteva@ptt.yu>
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238 #define CLIP1MAX (0x00100000 + 0x50)
4a08e7ac3f59 tdfxfb yuv driver by Zeljko Stevanovic <zsteva@ptt.yu>
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239 #define SRCFORMAT (0x00100000 + 0x54)
4a08e7ac3f59 tdfxfb yuv driver by Zeljko Stevanovic <zsteva@ptt.yu>
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240 #define SRCSIZE (0x00100000 + 0x58)
4a08e7ac3f59 tdfxfb yuv driver by Zeljko Stevanovic <zsteva@ptt.yu>
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241 #define SRCXY (0x00100000 + 0x5c)
4a08e7ac3f59 tdfxfb yuv driver by Zeljko Stevanovic <zsteva@ptt.yu>
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242 #define COLORBACK (0x00100000 + 0x60)
4a08e7ac3f59 tdfxfb yuv driver by Zeljko Stevanovic <zsteva@ptt.yu>
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243 #define COLORFORE (0x00100000 + 0x64)
4a08e7ac3f59 tdfxfb yuv driver by Zeljko Stevanovic <zsteva@ptt.yu>
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244 #define DSTSIZE (0x00100000 + 0x68)
4a08e7ac3f59 tdfxfb yuv driver by Zeljko Stevanovic <zsteva@ptt.yu>
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245 #define DSTXY (0x00100000 + 0x6c)
4a08e7ac3f59 tdfxfb yuv driver by Zeljko Stevanovic <zsteva@ptt.yu>
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246 #define COMMAND_2D (0x00100000 + 0x70)
4a08e7ac3f59 tdfxfb yuv driver by Zeljko Stevanovic <zsteva@ptt.yu>
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247 #define LAUNCH_2D (0x00100000 + 0x80)
4a08e7ac3f59 tdfxfb yuv driver by Zeljko Stevanovic <zsteva@ptt.yu>
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248
4a08e7ac3f59 tdfxfb yuv driver by Zeljko Stevanovic <zsteva@ptt.yu>
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249 #define COMMAND_3D (0x00200000 + 0x120)
4a08e7ac3f59 tdfxfb yuv driver by Zeljko Stevanovic <zsteva@ptt.yu>
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250
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251 #define SWAPBUFCMD (0x00200000 + 0x128)
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252 #define SWAPPENDING (0x00200000 + 0x24C)
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253 #define LEFTOVBUF (0x00200000 + 0x250)
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254 #define RIGHTOVBUF (0x00200000 + 0x254)
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255 #define FBISWAPBUFHIST (0x00200000 + 0x258)
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256
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4a08e7ac3f59 tdfxfb yuv driver by Zeljko Stevanovic <zsteva@ptt.yu>
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257 /* register bitfields (not all, only as needed) */
4a08e7ac3f59 tdfxfb yuv driver by Zeljko Stevanovic <zsteva@ptt.yu>
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258
4a08e7ac3f59 tdfxfb yuv driver by Zeljko Stevanovic <zsteva@ptt.yu>
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259 #define BIT(x) (1UL << (x))
4a08e7ac3f59 tdfxfb yuv driver by Zeljko Stevanovic <zsteva@ptt.yu>
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260
4a08e7ac3f59 tdfxfb yuv driver by Zeljko Stevanovic <zsteva@ptt.yu>
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261 /* COMMAND_2D reg. values */
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262 #define TDFXFB_ROP_COPY 0xcc // src
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263 #define TDFXFB_ROP_INVERT 0x55 // NOT dst
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264 #define TDFXFB_ROP_XOR 0x66 // src XOR dst
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265 #define TDFXFB_ROP_OR 0xee // src | dst
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266
4a08e7ac3f59 tdfxfb yuv driver by Zeljko Stevanovic <zsteva@ptt.yu>
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267 #define AUTOINC_DSTX BIT(10)
4a08e7ac3f59 tdfxfb yuv driver by Zeljko Stevanovic <zsteva@ptt.yu>
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268 #define AUTOINC_DSTY BIT(11)
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269
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270
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271 #define COMMAND_2D_S2S_BITBLT 0x01 // screen to screen
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272 #define COMMAND_2D_S2S_STRECH_BLT 0x02 // BLT + Strech
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273 #define COMMAND_2D_H2S_BITBLT 0x03 // host to screen
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274 #define COMMAND_2D_FILLRECT 0x05
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275
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276 #define COMMAND_2D_DO_IMMED BIT(8) // Do it immediatly
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277
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278
4a08e7ac3f59 tdfxfb yuv driver by Zeljko Stevanovic <zsteva@ptt.yu>
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279
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280 #define COMMAND_3D_NOP 0x00
4a08e7ac3f59 tdfxfb yuv driver by Zeljko Stevanovic <zsteva@ptt.yu>
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281 #define STATUS_RETRACE BIT(6)
4a08e7ac3f59 tdfxfb yuv driver by Zeljko Stevanovic <zsteva@ptt.yu>
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282 #define STATUS_BUSY BIT(9)
4a08e7ac3f59 tdfxfb yuv driver by Zeljko Stevanovic <zsteva@ptt.yu>
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283 #define MISCINIT1_CLUT_INV BIT(0)
4a08e7ac3f59 tdfxfb yuv driver by Zeljko Stevanovic <zsteva@ptt.yu>
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284 #define MISCINIT1_2DBLOCK_DIS BIT(15)
4a08e7ac3f59 tdfxfb yuv driver by Zeljko Stevanovic <zsteva@ptt.yu>
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285 #define DRAMINIT0_SGRAM_NUM BIT(26)
4a08e7ac3f59 tdfxfb yuv driver by Zeljko Stevanovic <zsteva@ptt.yu>
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286 #define DRAMINIT0_SGRAM_TYPE BIT(27)
4a08e7ac3f59 tdfxfb yuv driver by Zeljko Stevanovic <zsteva@ptt.yu>
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287 #define DRAMINIT1_MEM_SDRAM BIT(30)
4a08e7ac3f59 tdfxfb yuv driver by Zeljko Stevanovic <zsteva@ptt.yu>
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288 #define VGAINIT0_VGA_DISABLE BIT(0)
4a08e7ac3f59 tdfxfb yuv driver by Zeljko Stevanovic <zsteva@ptt.yu>
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289 #define VGAINIT0_EXT_TIMING BIT(1)
4a08e7ac3f59 tdfxfb yuv driver by Zeljko Stevanovic <zsteva@ptt.yu>
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290 #define VGAINIT0_8BIT_DAC BIT(2)
4a08e7ac3f59 tdfxfb yuv driver by Zeljko Stevanovic <zsteva@ptt.yu>
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291 #define VGAINIT0_EXT_ENABLE BIT(6)
4a08e7ac3f59 tdfxfb yuv driver by Zeljko Stevanovic <zsteva@ptt.yu>
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292 #define VGAINIT0_WAKEUP_3C3 BIT(8)
4a08e7ac3f59 tdfxfb yuv driver by Zeljko Stevanovic <zsteva@ptt.yu>
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293 #define VGAINIT0_LEGACY_DISABLE BIT(9)
4a08e7ac3f59 tdfxfb yuv driver by Zeljko Stevanovic <zsteva@ptt.yu>
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294 #define VGAINIT0_ALT_READBACK BIT(10)
4a08e7ac3f59 tdfxfb yuv driver by Zeljko Stevanovic <zsteva@ptt.yu>
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295 #define VGAINIT0_FAST_BLINK BIT(11)
4a08e7ac3f59 tdfxfb yuv driver by Zeljko Stevanovic <zsteva@ptt.yu>
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296 #define VGAINIT0_EXTSHIFTOUT BIT(12)
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297 #define VGAINIT0_DECODE_3C6 BIT(13)
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298 #define VGAINIT0_SGRAM_HBLANK_DISABLE BIT(22)
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299 #define VGAINIT1_MASK 0x1fffff
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300 #define VIDCFG_VIDPROC_ENABLE BIT(0)
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301 #define VIDCFG_CURS_X11 BIT(1)
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302 #define VIDCFG_HALF_MODE BIT(4)
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303 #define VIDCFG_DESK_ENABLE BIT(7)
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304 #define VIDCFG_CLUT_BYPASS BIT(10)
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305 #define VIDCFG_2X BIT(26)
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306 #define VIDCFG_HWCURSOR_ENABLE BIT(27)
4a08e7ac3f59 tdfxfb yuv driver by Zeljko Stevanovic <zsteva@ptt.yu>
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307 #define VIDCFG_PIXFMT_SHIFT 18
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308 #define DACMODE_2X BIT(0)
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309
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310 /* AGP registers */
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311 #define AGPREQSIZE (0x0080000 + 0x00)
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312 #define AGPHOSTADDRESSLOW (0x0080000 + 0x04)
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313 #define AGPHOSTADDRESSHIGH (0x0080000 + 0x08)
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314 #define AGPGRAPHICSADDRESS (0x0080000 + 0x0C)
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315 #define AGPGRAPHICSSTRIDE (0x0080000 + 0x10)
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316 #define AGPMOVECMD (0x0080000 + 0x14)
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317
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318 /* FIFO registers */
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319 #define CMDBASEADDR0 (0x0080000 + 0x20)
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320 #define CMDBASESIZE0 (0x0080000 + 0x24)
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321 #define CMDBUMP0 (0x0080000 + 0x28)
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322 #define CMDRDPTRL0 (0x0080000 + 0x2C)
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323 #define CMDRDPTRH0 (0x0080000 + 0x30)
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324 #define CMDAMIN0 (0x0080000 + 0x34)
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325 #define CMDAMAX0 (0x0080000 + 0x38)
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326 #define CMDFIFODEPTH0 (0x0080000 + 0x44)
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327 #define CMDHOLECNT0 (0x0080000 + 0x48)
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328
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329
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330 /* YUV reisters */
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331 #define YUVBASEADDRESS (0x0080000 + 0x100)
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332 #define YUVSTRIDE (0x0080000 + 0x104)
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333
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4a08e7ac3f59 tdfxfb yuv driver by Zeljko Stevanovic <zsteva@ptt.yu>
arpi
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334 /* VGA rubbish, need to change this for multihead support */
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335 #define MISC_W 0x3c2
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336 #define MISC_R 0x3cc
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337 #define SEQ_I 0x3c4
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338 #define SEQ_D 0x3c5
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339 #define CRT_I 0x3d4
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340 #define CRT_D 0x3d5
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341 #define ATT_IW 0x3c0
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342 #define RAMDAC_R 0x3c7
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343 #define RAMDAC_W 0x3c8
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344 #define RAMDAC_D 0x3c9
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345 #define IS1_R 0x3da
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346 #define GRA_I 0x3ce
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347 #define GRA_D 0x3cf
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348
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349 #ifndef FB_ACCEL_3DFX_BANSHEE
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350 #define FB_ACCEL_3DFX_BANSHEE 31
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351 #endif
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352
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353 #define TDFXF_HSYNC_ACT_HIGH 0x01
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354 #define TDFXF_HSYNC_ACT_LOW 0x02
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355 #define TDFXF_VSYNC_ACT_HIGH 0x04
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356 #define TDFXF_VSYNC_ACT_LOW 0x08
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357 #define TDFXF_LINE_DOUBLE 0x10
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358 #define TDFXF_VIDEO_ENABLE 0x20
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359
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360 #define TDFXF_HSYNC_MASK 0x03
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361 #define TDFXF_VSYNC_MASK 0x0c
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362
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363 #define XYREG(x,y) (((((unsigned long)y) & 0x1FFF) << 16) | (((unsigned long)x) & 0x1FFF))
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364
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365 //#define TDFXFB_DEBUG
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366 #ifdef TDFXFB_DEBUG
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367 #define DPRINTK(a,b...) printk(KERN_DEBUG "fb: %s: " a, __FUNCTION__ , ## b)
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368 #else
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369 #define DPRINTK(a,b...)
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370 #endif
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371
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372 /* ------------------------------------------------------------------------- */
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373
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374 #endif /* MPLAYER_3DFX_H */