annotate libvo/aclib.c @ 1572:25c2ee4de8b1

vo_font SEGFAULT fixed
author arpi
date Fri, 17 Aug 2001 10:18:27 +0000
parents 5b69dabe5823
children 99f6db3255aa
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1 #include "../config.h"
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2
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3 #ifdef USE_FASTMEMCPY
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4 /*
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5 aclib - advanced C library ;)
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6 This file contains functions which improve and expand standard C-library
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7 */
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8
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9 #include <stddef.h>
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10
1123
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11 #ifndef HAVE_SSE2
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12 /*
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13 P3 processor has only one SSE decoder so can execute only 1 sse insn per
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14 cpu clock, but it has 3 mmx decoders (include load/store unit)
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15 and executes 3 mmx insns per cpu clock.
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16 P4 processor has some chances, but after reading:
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17 http://www.emulators.com/pentium4.htm
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18 I have doubts. Anyway SSE2 version of this code can be written better.
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19 */
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20 #undef HAVE_SSE
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21 #endif
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22
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23
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24 /*
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25 This part of code was taken by me from Linux-2.4.3 and slightly modified
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26 for MMX, MMX2, SSE instruction set. I have done it since linux uses page aligned
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27 blocks but mplayer uses weakly ordered data and original sources can not
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28 speedup them. Only using PREFETCHNTA and MOVNTQ together have effect!
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29
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30 >From IA-32 Intel Architecture Software Developer's Manual Volume 1,
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31
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32 Order Number 245470:
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33 "10.4.6. Cacheability Control, Prefetch, and Memory Ordering Instructions"
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34
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35 Data referenced by a program can be temporal (data will be used again) or
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36 non-temporal (data will be referenced once and not reused in the immediate
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37 future). To make efficient use of the processor's caches, it is generally
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38 desirable to cache temporal data and not cache non-temporal data. Overloading
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39 the processor's caches with non-temporal data is sometimes referred to as
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40 "polluting the caches".
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41 The non-temporal data is written to memory with Write-Combining semantics.
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42
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43 The PREFETCHh instructions permits a program to load data into the processor
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44 at a suggested cache level, so that it is closer to the processors load and
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45 store unit when it is needed. If the data is already present in a level of
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46 the cache hierarchy that is closer to the processor, the PREFETCHh instruction
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47 will not result in any data movement.
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48 But we should you PREFETCHNTA: Non-temporal data fetch data into location
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49 close to the processor, minimizing cache pollution.
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50
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51 The MOVNTQ (store quadword using non-temporal hint) instruction stores
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52 packed integer data from an MMX register to memory, using a non-temporal hint.
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53 The MOVNTPS (store packed single-precision floating-point values using
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54 non-temporal hint) instruction stores packed floating-point data from an
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55 XMM register to memory, using a non-temporal hint.
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56
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57 The SFENCE (Store Fence) instruction controls write ordering by creating a
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58 fence for memory store operations. This instruction guarantees that the results
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59 of every store instruction that precedes the store fence in program order is
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60 globally visible before any store instruction that follows the fence. The
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61 SFENCE instruction provides an efficient way of ensuring ordering between
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62 procedures that produce weakly-ordered data and procedures that consume that
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63 data.
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64
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65 If you have questions please contact with me: Nick Kurshev: nickols_k@mail.ru.
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66 */
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67
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68 // 3dnow memcpy support from kernel 2.4.2
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69 // by Pontscho/fresh!mindworkz
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70
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71 #if defined( HAVE_MMX2 ) || defined( HAVE_3DNOW ) || defined( HAVE_MMX )
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72
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73 #undef HAVE_MMX1
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74 #if defined(HAVE_MMX) && !defined(HAVE_MMX2) && !defined(HAVE_3DNOW) && !defined(HAVE_SSE)
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75 /* means: mmx v.1. Note: Since we added alignment of destinition it speedups
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76 of memory copying on PentMMX, Celeron-1 and P2 upto 12% versus
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77 standard (non MMX-optimized) version.
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78 Note: on K6-2+ it speedups memory copying upto 25% and
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79 on K7 and P3 about 500% (5 times). */
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80 #define HAVE_MMX1
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81 #endif
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82
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83
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84 #undef HAVE_K6_2PLUS
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85 #if !defined( HAVE_MMX2) && defined( HAVE_3DNOW)
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86 #define HAVE_K6_2PLUS
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87 #endif
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88
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89 /* for small memory blocks (<256 bytes) this version is faster */
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90 #define small_memcpy(to,from,n)\
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91 {\
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92 register unsigned long int dummy;\
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93 __asm__ __volatile__(\
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94 "rep; movsb"\
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95 :"=&D"(to), "=&S"(from), "=&c"(dummy)\
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96 /* It's most portable way to notify compiler */\
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97 /* that edi, esi and ecx are clobbered in asm block. */\
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98 /* Thanks to A'rpi for hint!!! */\
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99 :"0" (to), "1" (from),"2" (n)\
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100 : "memory");\
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101 }
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102
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103 #ifdef HAVE_SSE
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104 #define MMREG_SIZE 16
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105 #else
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106 #define MMREG_SIZE 8
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107 #endif
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108
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109 /* Small defines (for readability only) ;) */
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110 #ifdef HAVE_K6_2PLUS
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111 #define PREFETCH "prefetch"
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112 /* On K6 femms is faster of emms. On K7 femms is directly mapped on emms. */
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113 #define EMMS "femms"
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114 #else
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115 #define PREFETCH "prefetchnta"
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116 #define EMMS "emms"
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117 #endif
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118
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119 #ifdef HAVE_MMX2
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120 #define MOVNTQ "movntq"
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121 #else
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122 #define MOVNTQ "movq"
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123 #endif
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124
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125 #ifdef HAVE_MMX1
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126 #define MIN_LEN 0x800 /* 2K blocks */
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127 #else
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128 #define MIN_LEN 0x40 /* 64-byte blocks */
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129 #endif
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130
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131 void * fast_memcpy(void * to, const void * from, size_t len)
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132 {
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133 void *retval;
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134 size_t i;
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135 retval = to;
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136 #ifndef HAVE_MMX1
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137 /* PREFETCH has effect even for MOVSB instruction ;) */
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138 __asm__ __volatile__ (
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139 PREFETCH" (%0)\n"
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140 PREFETCH" 64(%0)\n"
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141 PREFETCH" 128(%0)\n"
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142 PREFETCH" 192(%0)\n"
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143 PREFETCH" 256(%0)\n"
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144 : : "r" (from) );
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145 #endif
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146 if(len >= MIN_LEN)
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147 {
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148 register unsigned long int delta;
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149 /* Align destinition to MMREG_SIZE -boundary */
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150 delta = ((unsigned long int)to)&(MMREG_SIZE-1);
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151 if(delta)
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152 {
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153 delta=MMREG_SIZE-delta;
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154 len -= delta;
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155 small_memcpy(to, from, delta);
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156 }
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157 i = len >> 6; /* len/64 */
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158 len&=63;
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159 /*
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160 This algorithm is top effective when the code consequently
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161 reads and writes blocks which have size of cache line.
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162 Size of cache line is processor-dependent.
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163 It will, however, be a minimum of 32 bytes on any processors.
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164 It would be better to have a number of instructions which
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165 perform reading and writing to be multiple to a number of
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166 processor's decoders, but it's not always possible.
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167 */
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168 #ifdef HAVE_SSE /* Only P3 (may be Cyrix3) */
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169 if(((unsigned long)from) & 15)
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170 /* if SRC is misaligned */
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171 for(; i>0; i--)
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172 {
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173 __asm__ __volatile__ (
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174 PREFETCH" 320(%0)\n"
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175 "movups (%0), %%xmm0\n"
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176 "movups 16(%0), %%xmm1\n"
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177 "movups 32(%0), %%xmm2\n"
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178 "movups 48(%0), %%xmm3\n"
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179 "movntps %%xmm0, (%1)\n"
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180 "movntps %%xmm1, 16(%1)\n"
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181 "movntps %%xmm2, 32(%1)\n"
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182 "movntps %%xmm3, 48(%1)\n"
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183 :: "r" (from), "r" (to) : "memory");
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184 ((const unsigned char *)from)+=64;
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185 ((unsigned char *)to)+=64;
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186 }
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187 else
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188 /*
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189 Only if SRC is aligned on 16-byte boundary.
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190 It allows to use movaps instead of movups, which required data
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191 to be aligned or a general-protection exception (#GP) is generated.
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192 */
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193 for(; i>0; i--)
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194 {
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195 __asm__ __volatile__ (
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196 PREFETCH" 320(%0)\n"
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197 "movaps (%0), %%xmm0\n"
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198 "movaps 16(%0), %%xmm1\n"
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199 "movaps 32(%0), %%xmm2\n"
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200 "movaps 48(%0), %%xmm3\n"
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201 "movntps %%xmm0, (%1)\n"
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202 "movntps %%xmm1, 16(%1)\n"
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203 "movntps %%xmm2, 32(%1)\n"
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204 "movntps %%xmm3, 48(%1)\n"
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205 :: "r" (from), "r" (to) : "memory");
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206 ((const unsigned char *)from)+=64;
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207 ((unsigned char *)to)+=64;
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208 }
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209 #else
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210 for(; i>0; i--)
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211 {
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212 __asm__ __volatile__ (
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213 #ifndef HAVE_MMX1
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214 PREFETCH" 320(%0)\n"
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215 #endif
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216 "movq (%0), %%mm0\n"
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217 "movq 8(%0), %%mm1\n"
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218 "movq 16(%0), %%mm2\n"
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219 "movq 24(%0), %%mm3\n"
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220 "movq 32(%0), %%mm4\n"
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221 "movq 40(%0), %%mm5\n"
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222 "movq 48(%0), %%mm6\n"
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223 "movq 56(%0), %%mm7\n"
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224 MOVNTQ" %%mm0, (%1)\n"
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225 MOVNTQ" %%mm1, 8(%1)\n"
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226 MOVNTQ" %%mm2, 16(%1)\n"
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227 MOVNTQ" %%mm3, 24(%1)\n"
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228 MOVNTQ" %%mm4, 32(%1)\n"
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229 MOVNTQ" %%mm5, 40(%1)\n"
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230 MOVNTQ" %%mm6, 48(%1)\n"
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231 MOVNTQ" %%mm7, 56(%1)\n"
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232 :: "r" (from), "r" (to) : "memory");
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233 ((const unsigned char *)from)+=64;
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234 ((unsigned char *)to)+=64;
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235 }
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236 #endif /* Have SSE */
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237 #ifdef HAVE_MMX2
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238 /* since movntq is weakly-ordered, a "sfence"
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239 * is needed to become ordered again. */
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240 __asm__ __volatile__ ("sfence":::"memory");
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241 #endif
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242 #ifndef HAVE_SSE
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243 /* enables to use FPU */
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244 __asm__ __volatile__ (EMMS:::"memory");
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245 #endif
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246 }
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247 /*
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248 * Now do the tail of the block
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249 */
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250 if(len) small_memcpy(to, from, len);
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251 return retval;
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252 }
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253
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254
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255 #endif /* #if defined( HAVE_MMX2 ) || defined( HAVE_3DNOW ) || defined( HAVE_MMX ) */
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256 #endif /* USE_FASTMEMCPY */