annotate libmpeg2/motion_comp_arm_s.S @ 23930:282a634da284

Extend OpenGL configure test to also check for glx/wgl and proper linking.
author reimar
date Mon, 30 Jul 2007 19:02:45 +0000
parents f0ddd02aec27
children 62abac0c8637
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rev   line source
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1 @ motion_comp_arm_s.S
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2 @ Copyright (C) 2004 AGAWA Koji <i (AT) atty (DOT) jp>
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3 @
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4 @ This file is part of mpeg2dec, a free MPEG-2 video stream decoder.
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5 @ See http://libmpeg2.sourceforge.net/ for updates.
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6 @
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7 @ mpeg2dec is free software; you can redistribute it and/or modify
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8 @ it under the terms of the GNU General Public License as published by
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9 @ the Free Software Foundation; either version 2 of the License, or
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10 @ (at your option) any later version.
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11 @
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12 @ mpeg2dec is distributed in the hope that it will be useful,
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13 @ but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 @ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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15 @ GNU General Public License for more details.
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16 @
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17 @ You should have received a copy of the GNU General Public License
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18 @ along with this program; if not, write to the Free Software
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19 @ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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20
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21 .text
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22
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23 @ ----------------------------------------------------------------
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24 .align
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25 .global MC_put_o_16_arm
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26 MC_put_o_16_arm:
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27 @@ void func(uint8_t * dest, const uint8_t * ref, int stride, int height)
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28 pld [r1]
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29 stmfd sp!, {r4-r11, lr} @ R14 is also called LR
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30 and r4, r1, #3
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31 adr r5, MC_put_o_16_arm_align_jt
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32 add r5, r5, r4, lsl #2
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33 ldr pc, [r5]
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34
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35 MC_put_o_16_arm_align0:
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36 ldmia r1, {r4-r7}
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37 add r1, r1, r2
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38 pld [r1]
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39 stmia r0, {r4-r7}
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40 subs r3, r3, #1
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41 add r0, r0, r2
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42 bne MC_put_o_16_arm_align0
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43 ldmfd sp!, {r4-r11, pc} @@ update PC with LR content.
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44
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45 .macro PROC shift
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46 ldmia r1, {r4-r8}
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47 add r1, r1, r2
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48 mov r9, r4, lsr #(\shift)
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49 pld [r1]
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50 mov r10, r5, lsr #(\shift)
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51 orr r9, r9, r5, lsl #(32-\shift)
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52 mov r11, r6, lsr #(\shift)
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53 orr r10, r10, r6, lsl #(32-\shift)
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54 mov r12, r7, lsr #(\shift)
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55 orr r11, r11, r7, lsl #(32-\shift)
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56 orr r12, r12, r8, lsl #(32-\shift)
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57 stmia r0, {r9-r12}
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58 subs r3, r3, #1
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59 add r0, r0, r2
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60 .endm
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61
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62 MC_put_o_16_arm_align1:
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63 and r1, r1, #0xFFFFFFFC
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64 1: PROC(8)
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65 bne 1b
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66 ldmfd sp!, {r4-r11, pc} @@ update PC with LR content.
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67 MC_put_o_16_arm_align2:
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68 and r1, r1, #0xFFFFFFFC
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69 1: PROC(16)
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70 bne 1b
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71 ldmfd sp!, {r4-r11, pc} @@ update PC with LR content.
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72 MC_put_o_16_arm_align3:
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73 and r1, r1, #0xFFFFFFFC
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74 1: PROC(24)
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75 bne 1b
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76 ldmfd sp!, {r4-r11, pc} @@ update PC with LR content.
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77 MC_put_o_16_arm_align_jt:
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78 .word MC_put_o_16_arm_align0
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79 .word MC_put_o_16_arm_align1
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80 .word MC_put_o_16_arm_align2
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81 .word MC_put_o_16_arm_align3
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82
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83 @ ----------------------------------------------------------------
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84 .align
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85 .global MC_put_o_8_arm
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86 MC_put_o_8_arm:
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87 @@ void func(uint8_t * dest, const uint8_t * ref, int stride, int height)
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88 pld [r1]
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89 stmfd sp!, {r4-r10, lr} @ R14 is also called LR
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90 and r4, r1, #3
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91 adr r5, MC_put_o_8_arm_align_jt
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92 add r5, r5, r4, lsl #2
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93 ldr pc, [r5]
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94 MC_put_o_8_arm_align0:
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95 ldmia r1, {r4-r5}
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96 add r1, r1, r2
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97 pld [r1]
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98 stmia r0, {r4-r5}
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99 add r0, r0, r2
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100 subs r3, r3, #1
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101 bne MC_put_o_8_arm_align0
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102 ldmfd sp!, {r4-r10, pc} @@ update PC with LR content.
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103
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104 .macro PROC8 shift
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105 ldmia r1, {r4-r6}
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106 add r1, r1, r2
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107 mov r9, r4, lsr #(\shift)
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108 pld [r1]
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109 mov r10, r5, lsr #(\shift)
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110 orr r9, r9, r5, lsl #(32-\shift)
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111 orr r10, r10, r6, lsl #(32-\shift)
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112 stmia r0, {r9-r10}
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113 subs r3, r3, #1
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114 add r0, r0, r2
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115 .endm
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116
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117 MC_put_o_8_arm_align1:
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118 and r1, r1, #0xFFFFFFFC
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119 1: PROC8(8)
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120 bne 1b
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121 ldmfd sp!, {r4-r10, pc} @@ update PC with LR content.
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122
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123 MC_put_o_8_arm_align2:
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124 and r1, r1, #0xFFFFFFFC
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125 1: PROC8(16)
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126 bne 1b
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127 ldmfd sp!, {r4-r10, pc} @@ update PC with LR content.
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128
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129 MC_put_o_8_arm_align3:
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130 and r1, r1, #0xFFFFFFFC
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131 1: PROC8(24)
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132 bne 1b
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133 ldmfd sp!, {r4-r10, pc} @@ update PC with LR content.
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134
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135 MC_put_o_8_arm_align_jt:
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136 .word MC_put_o_8_arm_align0
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137 .word MC_put_o_8_arm_align1
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138 .word MC_put_o_8_arm_align2
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139 .word MC_put_o_8_arm_align3
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140
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141 @ ----------------------------------------------------------------
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142 .macro AVG_PW rW1, rW2
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143 mov \rW2, \rW2, lsl #24
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144 orr \rW2, \rW2, \rW1, lsr #8
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145 eor r9, \rW1, \rW2
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146 and \rW2, \rW1, \rW2
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147 and r10, r9, r12
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148 add \rW2, \rW2, r10, lsr #1
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149 and r10, r9, r11
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150 add \rW2, \rW2, r10
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151 .endm
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152
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153 .align
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154 .global MC_put_x_16_arm
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155 MC_put_x_16_arm:
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156 @@ void func(uint8_t * dest, const uint8_t * ref, int stride, int height)
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157 pld [r1]
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158 stmfd sp!, {r4-r11,lr} @ R14 is also called LR
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159 and r4, r1, #3
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160 adr r5, MC_put_x_16_arm_align_jt
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161 ldr r11, [r5]
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162 mvn r12, r11
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163 add r5, r5, r4, lsl #2
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164 ldr pc, [r5, #4]
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165
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166 .macro ADJ_ALIGN_QW shift, R0, R1, R2, R3, R4
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167 mov \R0, \R0, lsr #(\shift)
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168 orr \R0, \R0, \R1, lsl #(32 - \shift)
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169 mov \R1, \R1, lsr #(\shift)
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170 orr \R1, \R1, \R2, lsl #(32 - \shift)
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171 mov \R2, \R2, lsr #(\shift)
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172 orr \R2, \R2, \R3, lsl #(32 - \shift)
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173 mov \R3, \R3, lsr #(\shift)
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174 orr \R3, \R3, \R4, lsl #(32 - \shift)
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175 mov \R4, \R4, lsr #(\shift)
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176 @ and \R4, \R4, #0xFF
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177 .endm
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178
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179 MC_put_x_16_arm_align0:
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180 ldmia r1, {r4-r8}
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181 add r1, r1, r2
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182 pld [r1]
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183 AVG_PW r7, r8
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184 AVG_PW r6, r7
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185 AVG_PW r5, r6
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186 AVG_PW r4, r5
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187 stmia r0, {r5-r8}
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188 subs r3, r3, #1
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189 add r0, r0, r2
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190 bne MC_put_x_16_arm_align0
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191 ldmfd sp!, {r4-r11,pc} @@ update PC with LR content.
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192 MC_put_x_16_arm_align1:
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193 and r1, r1, #0xFFFFFFFC
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194 1: ldmia r1, {r4-r8}
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195 add r1, r1, r2
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196 pld [r1]
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197 ADJ_ALIGN_QW 8, r4, r5, r6, r7, r8
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198 AVG_PW r7, r8
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199 AVG_PW r6, r7
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200 AVG_PW r5, r6
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201 AVG_PW r4, r5
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202 stmia r0, {r5-r8}
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203 subs r3, r3, #1
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204 add r0, r0, r2
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205 bne 1b
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206 ldmfd sp!, {r4-r11,pc} @@ update PC with LR content.
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207 MC_put_x_16_arm_align2:
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208 and r1, r1, #0xFFFFFFFC
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209 1: ldmia r1, {r4-r8}
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210 add r1, r1, r2
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211 pld [r1]
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212 ADJ_ALIGN_QW 16, r4, r5, r6, r7, r8
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213 AVG_PW r7, r8
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214 AVG_PW r6, r7
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215 AVG_PW r5, r6
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216 AVG_PW r4, r5
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217 stmia r0, {r5-r8}
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218 subs r3, r3, #1
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219 add r0, r0, r2
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220 bne 1b
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221 ldmfd sp!, {r4-r11,pc} @@ update PC with LR content.
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222 MC_put_x_16_arm_align3:
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223 and r1, r1, #0xFFFFFFFC
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224 1: ldmia r1, {r4-r8}
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225 add r1, r1, r2
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226 pld [r1]
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227 ADJ_ALIGN_QW 24, r4, r5, r6, r7, r8
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228 AVG_PW r7, r8
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229 AVG_PW r6, r7
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230 AVG_PW r5, r6
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231 AVG_PW r4, r5
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232 stmia r0, {r5-r8}
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233 subs r3, r3, #1
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234 add r0, r0, r2
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235 bne 1b
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236 ldmfd sp!, {r4-r11,pc} @@ update PC with LR content.
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237 MC_put_x_16_arm_align_jt:
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238 .word 0x01010101
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239 .word MC_put_x_16_arm_align0
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240 .word MC_put_x_16_arm_align1
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241 .word MC_put_x_16_arm_align2
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242 .word MC_put_x_16_arm_align3
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243
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244 @ ----------------------------------------------------------------
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245 .align
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246 .global MC_put_x_8_arm
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247 MC_put_x_8_arm:
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248 @@ void func(uint8_t * dest, const uint8_t * ref, int stride, int height)
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249 pld [r1]
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250 stmfd sp!, {r4-r11,lr} @ R14 is also called LR
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251 and r4, r1, #3
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252 adr r5, MC_put_x_8_arm_align_jt
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253 ldr r11, [r5]
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254 mvn r12, r11
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255 add r5, r5, r4, lsl #2
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256 ldr pc, [r5, #4]
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257
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258 .macro ADJ_ALIGN_DW shift, R0, R1, R2
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259 mov \R0, \R0, lsr #(\shift)
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260 orr \R0, \R0, \R1, lsl #(32 - \shift)
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261 mov \R1, \R1, lsr #(\shift)
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262 orr \R1, \R1, \R2, lsl #(32 - \shift)
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263 mov \R2, \R2, lsr #(\shift)
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264 @ and \R4, \R4, #0xFF
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265 .endm
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266
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267 MC_put_x_8_arm_align0:
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268 ldmia r1, {r4-r6}
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269 add r1, r1, r2
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270 pld [r1]
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271 AVG_PW r5, r6
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272 AVG_PW r4, r5
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273 stmia r0, {r5-r6}
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274 subs r3, r3, #1
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275 add r0, r0, r2
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276 bne MC_put_x_8_arm_align0
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277 ldmfd sp!, {r4-r11,pc} @@ update PC with LR content.
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278 MC_put_x_8_arm_align1:
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279 and r1, r1, #0xFFFFFFFC
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280 1: ldmia r1, {r4-r6}
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281 add r1, r1, r2
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282 pld [r1]
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283 ADJ_ALIGN_DW 8, r4, r5, r6
f0ddd02aec27 iWMMXt-accelerated DCT and motion compensation for ARM processors
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284 AVG_PW r5, r6
f0ddd02aec27 iWMMXt-accelerated DCT and motion compensation for ARM processors
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285 AVG_PW r4, r5
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gpoirier
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286 stmia r0, {r5-r6}
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287 subs r3, r3, #1
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288 add r0, r0, r2
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289 bne 1b
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290 ldmfd sp!, {r4-r11,pc} @@ update PC with LR content.
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291 MC_put_x_8_arm_align2:
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292 and r1, r1, #0xFFFFFFFC
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293 1: ldmia r1, {r4-r6}
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294 add r1, r1, r2
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295 pld [r1]
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296 ADJ_ALIGN_DW 16, r4, r5, r6
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297 AVG_PW r5, r6
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298 AVG_PW r4, r5
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299 stmia r0, {r5-r6}
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300 subs r3, r3, #1
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301 add r0, r0, r2
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302 bne 1b
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303 ldmfd sp!, {r4-r11,pc} @@ update PC with LR content.
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304 MC_put_x_8_arm_align3:
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305 and r1, r1, #0xFFFFFFFC
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306 1: ldmia r1, {r4-r6}
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307 add r1, r1, r2
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308 pld [r1]
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309 ADJ_ALIGN_DW 24, r4, r5, r6
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310 AVG_PW r5, r6
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311 AVG_PW r4, r5
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312 stmia r0, {r5-r6}
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313 subs r3, r3, #1
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314 add r0, r0, r2
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315 bne 1b
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316 ldmfd sp!, {r4-r11,pc} @@ update PC with LR content.
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317 MC_put_x_8_arm_align_jt:
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318 .word 0x01010101
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319 .word MC_put_x_8_arm_align0
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320 .word MC_put_x_8_arm_align1
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321 .word MC_put_x_8_arm_align2
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322 .word MC_put_x_8_arm_align3