annotate mp3lib/dct12.c @ 14419:320876fbfe65

Sync with 1.846 + spelling corrections : x264: disable subq=0 (the huge bitrate penalty wasn't worth the speed), and set default subq to best. wording. renumber direct_pred (temporal seems to be best) NOTE: the wording of the subq section seems akward: further work needed.
author gpoirier
date Fri, 07 Jan 2005 22:16:46 +0000
parents 3b5f5d1c5041
children 0f1b5b68af32
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1 /*
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2 * new DCT12
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3 */
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4 static void dct12(real *in,real *rawout1,real *rawout2,register real *wi,register real *ts)
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5 {
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6 #define DCT12_PART1 \
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7 in5 = in[5*3]; \
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8 in5 += (in4 = in[4*3]); \
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9 in4 += (in3 = in[3*3]); \
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10 in3 += (in2 = in[2*3]); \
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11 in2 += (in1 = in[1*3]); \
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12 in1 += (in0 = in[0*3]); \
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13 \
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14 in5 += in3; in3 += in1; \
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15 \
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16 in2 *= COS6_1; \
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17 in3 *= COS6_1; \
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18
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19 #define DCT12_PART2 \
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20 in0 += in4 * COS6_2; \
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21 \
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22 in4 = in0 + in2; \
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23 in0 -= in2; \
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24 \
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25 in1 += in5 * COS6_2; \
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26 \
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27 in5 = (in1 + in3) * tfcos12[0]; \
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28 in1 = (in1 - in3) * tfcos12[2]; \
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29 \
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30 in3 = in4 + in5; \
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31 in4 -= in5; \
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32 \
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33 in2 = in0 + in1; \
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34 in0 -= in1;
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35
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36
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37 {
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38 real in0,in1,in2,in3,in4,in5;
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39 register real *out1 = rawout1;
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40 ts[SBLIMIT*0] = out1[0]; ts[SBLIMIT*1] = out1[1]; ts[SBLIMIT*2] = out1[2];
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41 ts[SBLIMIT*3] = out1[3]; ts[SBLIMIT*4] = out1[4]; ts[SBLIMIT*5] = out1[5];
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42
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43 DCT12_PART1
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44
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45 {
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46 real tmp0,tmp1 = (in0 - in4);
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47 {
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48 real tmp2 = (in1 - in5) * tfcos12[1];
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49 tmp0 = tmp1 + tmp2;
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50 tmp1 -= tmp2;
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51 }
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52 ts[(17-1)*SBLIMIT] = out1[17-1] + tmp0 * wi[11-1];
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53 ts[(12+1)*SBLIMIT] = out1[12+1] + tmp0 * wi[6+1];
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54 ts[(6 +1)*SBLIMIT] = out1[6 +1] + tmp1 * wi[1];
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55 ts[(11-1)*SBLIMIT] = out1[11-1] + tmp1 * wi[5-1];
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56 }
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57
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58 DCT12_PART2
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59
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60 ts[(17-0)*SBLIMIT] = out1[17-0] + in2 * wi[11-0];
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61 ts[(12+0)*SBLIMIT] = out1[12+0] + in2 * wi[6+0];
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62 ts[(12+2)*SBLIMIT] = out1[12+2] + in3 * wi[6+2];
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63 ts[(17-2)*SBLIMIT] = out1[17-2] + in3 * wi[11-2];
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64
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65 ts[(6+0)*SBLIMIT] = out1[6+0] + in0 * wi[0];
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66 ts[(11-0)*SBLIMIT] = out1[11-0] + in0 * wi[5-0];
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67 ts[(6+2)*SBLIMIT] = out1[6+2] + in4 * wi[2];
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68 ts[(11-2)*SBLIMIT] = out1[11-2] + in4 * wi[5-2];
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69 }
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70
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71 in++;
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72
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73 {
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74 real in0,in1,in2,in3,in4,in5;
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75 register real *out2 = rawout2;
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76
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77 DCT12_PART1
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78
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79 {
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80 real tmp0,tmp1 = (in0 - in4);
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81 {
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82 real tmp2 = (in1 - in5) * tfcos12[1];
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83 tmp0 = tmp1 + tmp2;
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84 tmp1 -= tmp2;
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85 }
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86 out2[5-1] = tmp0 * wi[11-1];
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87 out2[0+1] = tmp0 * wi[6+1];
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88 ts[(12+1)*SBLIMIT] += tmp1 * wi[1];
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89 ts[(17-1)*SBLIMIT] += tmp1 * wi[5-1];
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90 }
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91
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92 DCT12_PART2
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93
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94 out2[5-0] = in2 * wi[11-0];
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95 out2[0+0] = in2 * wi[6+0];
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96 out2[0+2] = in3 * wi[6+2];
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97 out2[5-2] = in3 * wi[11-2];
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98
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99 ts[(12+0)*SBLIMIT] += in0 * wi[0];
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100 ts[(17-0)*SBLIMIT] += in0 * wi[5-0];
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101 ts[(12+2)*SBLIMIT] += in4 * wi[2];
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102 ts[(17-2)*SBLIMIT] += in4 * wi[5-2];
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103 }
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104
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105 in++;
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106
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107 {
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108 real in0,in1,in2,in3,in4,in5;
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109 register real *out2 = rawout2;
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110 out2[12]=out2[13]=out2[14]=out2[15]=out2[16]=out2[17]=0.0;
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111
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112 DCT12_PART1
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113
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114 {
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115 real tmp0,tmp1 = (in0 - in4);
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116 {
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117 real tmp2 = (in1 - in5) * tfcos12[1];
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118 tmp0 = tmp1 + tmp2;
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119 tmp1 -= tmp2;
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120 }
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121 out2[11-1] = tmp0 * wi[11-1];
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122 out2[6 +1] = tmp0 * wi[6+1];
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123 out2[0+1] += tmp1 * wi[1];
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124 out2[5-1] += tmp1 * wi[5-1];
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125 }
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126
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127 DCT12_PART2
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128
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129 out2[11-0] = in2 * wi[11-0];
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130 out2[6 +0] = in2 * wi[6+0];
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131 out2[6 +2] = in3 * wi[6+2];
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132 out2[11-2] = in3 * wi[11-2];
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133
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134 out2[0+0] += in0 * wi[0];
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135 out2[5-0] += in0 * wi[5-0];
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136 out2[0+2] += in4 * wi[2];
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137 out2[5-2] += in4 * wi[5-2];
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138 }
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139 }