Mercurial > mplayer.hg
annotate libvo/aclib_template.c @ 3721:66da035c4ee2
some quick updates for the prerelease
author | gabucino |
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date | Mon, 24 Dec 2001 23:00:07 +0000 |
parents | 3624cd351618 |
children | 8db59073127e |
rev | line source |
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10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
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1 /* |
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2 aclib - advanced C library ;) |
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3 This file contains functions which improve and expand standard C-library |
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4 */ |
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5 |
1123 | 6 #ifndef HAVE_SSE2 |
7 /* | |
8 P3 processor has only one SSE decoder so can execute only 1 sse insn per | |
9 cpu clock, but it has 3 mmx decoders (include load/store unit) | |
10 and executes 3 mmx insns per cpu clock. | |
11 P4 processor has some chances, but after reading: | |
12 http://www.emulators.com/pentium4.htm | |
13 I have doubts. Anyway SSE2 version of this code can be written better. | |
14 */ | |
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15 #undef HAVE_SSE |
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16 #endif |
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17 |
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18 |
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19 /* |
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20 This part of code was taken by me from Linux-2.4.3 and slightly modified |
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21 for MMX, MMX2, SSE instruction set. I have done it since linux uses page aligned |
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22 blocks but mplayer uses weakly ordered data and original sources can not |
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23 speedup them. Only using PREFETCHNTA and MOVNTQ together have effect! |
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24 |
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25 >From IA-32 Intel Architecture Software Developer's Manual Volume 1, |
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26 |
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27 Order Number 245470: |
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28 "10.4.6. Cacheability Control, Prefetch, and Memory Ordering Instructions" |
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29 |
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30 Data referenced by a program can be temporal (data will be used again) or |
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31 non-temporal (data will be referenced once and not reused in the immediate |
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32 future). To make efficient use of the processor's caches, it is generally |
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33 desirable to cache temporal data and not cache non-temporal data. Overloading |
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34 the processor's caches with non-temporal data is sometimes referred to as |
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35 "polluting the caches". |
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36 The non-temporal data is written to memory with Write-Combining semantics. |
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37 |
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38 The PREFETCHh instructions permits a program to load data into the processor |
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39 at a suggested cache level, so that it is closer to the processors load and |
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40 store unit when it is needed. If the data is already present in a level of |
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41 the cache hierarchy that is closer to the processor, the PREFETCHh instruction |
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42 will not result in any data movement. |
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43 But we should you PREFETCHNTA: Non-temporal data fetch data into location |
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44 close to the processor, minimizing cache pollution. |
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45 |
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46 The MOVNTQ (store quadword using non-temporal hint) instruction stores |
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47 packed integer data from an MMX register to memory, using a non-temporal hint. |
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48 The MOVNTPS (store packed single-precision floating-point values using |
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49 non-temporal hint) instruction stores packed floating-point data from an |
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50 XMM register to memory, using a non-temporal hint. |
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51 |
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52 The SFENCE (Store Fence) instruction controls write ordering by creating a |
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53 fence for memory store operations. This instruction guarantees that the results |
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54 of every store instruction that precedes the store fence in program order is |
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55 globally visible before any store instruction that follows the fence. The |
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56 SFENCE instruction provides an efficient way of ensuring ordering between |
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57 procedures that produce weakly-ordered data and procedures that consume that |
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58 data. |
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59 |
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60 If you have questions please contact with me: Nick Kurshev: nickols_k@mail.ru. |
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61 */ |
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62 |
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63 // 3dnow memcpy support from kernel 2.4.2 |
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64 // by Pontscho/fresh!mindworkz |
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65 |
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66 |
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67 #undef HAVE_MMX1 |
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68 #if defined(HAVE_MMX) && !defined(HAVE_MMX2) && !defined(HAVE_3DNOW) && !defined(HAVE_SSE) |
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69 /* means: mmx v.1. Note: Since we added alignment of destinition it speedups |
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70 of memory copying on PentMMX, Celeron-1 and P2 upto 12% versus |
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71 standard (non MMX-optimized) version. |
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72 Note: on K6-2+ it speedups memory copying upto 25% and |
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73 on K7 and P3 about 500% (5 times). */ |
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74 #define HAVE_MMX1 |
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75 #endif |
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76 |
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77 |
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78 #undef HAVE_K6_2PLUS |
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79 #if !defined( HAVE_MMX2) && defined( HAVE_3DNOW) |
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80 #define HAVE_K6_2PLUS |
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81 #endif |
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82 |
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83 /* for small memory blocks (<256 bytes) this version is faster */ |
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84 #define small_memcpy(to,from,n)\ |
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85 {\ |
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86 register unsigned long int dummy;\ |
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87 __asm__ __volatile__(\ |
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88 "rep; movsb"\ |
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89 :"=&D"(to), "=&S"(from), "=&c"(dummy)\ |
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90 /* It's most portable way to notify compiler */\ |
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91 /* that edi, esi and ecx are clobbered in asm block. */\ |
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92 /* Thanks to A'rpi for hint!!! */\ |
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93 :"0" (to), "1" (from),"2" (n)\ |
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94 : "memory");\ |
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95 } |
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96 |
3393 | 97 #undef MMREG_SIZE |
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98 #ifdef HAVE_SSE |
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99 #define MMREG_SIZE 16 |
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100 #else |
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101 #define MMREG_SIZE 64 //8 |
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102 #endif |
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103 |
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104 /* Small defines (for readability only) ;) */ |
3393 | 105 #undef PREFETCH |
106 #undef EMMS | |
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107 #ifdef HAVE_K6_2PLUS |
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108 #define PREFETCH "prefetch" |
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109 /* On K6 femms is faster of emms. On K7 femms is directly mapped on emms. */ |
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110 #define EMMS "femms" |
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111 #else |
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112 #define PREFETCH "prefetchnta" |
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113 #define EMMS "emms" |
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114 #endif |
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115 |
3393 | 116 #undef MOVNTQ |
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117 #ifdef HAVE_MMX2 |
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118 #define MOVNTQ "movntq" |
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119 #else |
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120 #define MOVNTQ "movq" |
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121 #endif |
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122 |
3393 | 123 #undef MIN_LEN |
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124 #ifdef HAVE_MMX1 |
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125 #define MIN_LEN 0x800 /* 2K blocks */ |
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126 #else |
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127 #define MIN_LEN 0x40 /* 64-byte blocks */ |
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128 #endif |
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129 |
3393 | 130 static inline void * RENAME(fast_memcpy)(void * to, const void * from, size_t len) |
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131 { |
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132 void *retval; |
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133 size_t i; |
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134 retval = to; |
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135 #ifdef STATISTICS |
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136 { |
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137 static int freq[33]; |
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138 static int t=0; |
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139 int i; |
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140 for(i=0; len>(1<<i); i++); |
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141 freq[i]++; |
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142 t++; |
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143 if(1024*1024*1024 % t == 0) |
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144 for(i=0; i<32; i++) |
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145 printf("freq < %8d %4d\n", 1<<i, freq[i]); |
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146 } |
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147 #endif |
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148 #ifndef HAVE_MMX1 |
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149 /* PREFETCH has effect even for MOVSB instruction ;) */ |
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150 __asm__ __volatile__ ( |
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151 PREFETCH" (%0)\n" |
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152 PREFETCH" 64(%0)\n" |
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153 PREFETCH" 128(%0)\n" |
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154 PREFETCH" 192(%0)\n" |
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155 PREFETCH" 256(%0)\n" |
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156 : : "r" (from) ); |
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157 #endif |
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158 if(len >= MIN_LEN) |
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159 { |
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160 register unsigned long int delta; |
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161 /* Align destinition to MMREG_SIZE -boundary */ |
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162 delta = ((unsigned long int)to)&(MMREG_SIZE-1); |
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163 if(delta) |
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164 { |
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165 delta=MMREG_SIZE-delta; |
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166 len -= delta; |
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167 small_memcpy(to, from, delta); |
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168 } |
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169 i = len >> 6; /* len/64 */ |
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170 len&=63; |
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171 /* |
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172 This algorithm is top effective when the code consequently |
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173 reads and writes blocks which have size of cache line. |
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174 Size of cache line is processor-dependent. |
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175 It will, however, be a minimum of 32 bytes on any processors. |
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176 It would be better to have a number of instructions which |
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177 perform reading and writing to be multiple to a number of |
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178 processor's decoders, but it's not always possible. |
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179 */ |
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180 #ifdef HAVE_SSE /* Only P3 (may be Cyrix3) */ |
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181 if(((unsigned long)from) & 15) |
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182 /* if SRC is misaligned */ |
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183 for(; i>0; i--) |
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184 { |
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185 __asm__ __volatile__ ( |
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186 PREFETCH" 320(%0)\n" |
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187 "movups (%0), %%xmm0\n" |
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188 "movups 16(%0), %%xmm1\n" |
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189 "movups 32(%0), %%xmm2\n" |
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190 "movups 48(%0), %%xmm3\n" |
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191 "movntps %%xmm0, (%1)\n" |
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192 "movntps %%xmm1, 16(%1)\n" |
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193 "movntps %%xmm2, 32(%1)\n" |
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194 "movntps %%xmm3, 48(%1)\n" |
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195 :: "r" (from), "r" (to) : "memory"); |
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196 ((const unsigned char *)from)+=64; |
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197 ((unsigned char *)to)+=64; |
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198 } |
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199 else |
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200 /* |
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201 Only if SRC is aligned on 16-byte boundary. |
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202 It allows to use movaps instead of movups, which required data |
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203 to be aligned or a general-protection exception (#GP) is generated. |
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204 */ |
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205 for(; i>0; i--) |
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206 { |
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207 __asm__ __volatile__ ( |
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208 PREFETCH" 320(%0)\n" |
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209 "movaps (%0), %%xmm0\n" |
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210 "movaps 16(%0), %%xmm1\n" |
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211 "movaps 32(%0), %%xmm2\n" |
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212 "movaps 48(%0), %%xmm3\n" |
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213 "movntps %%xmm0, (%1)\n" |
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214 "movntps %%xmm1, 16(%1)\n" |
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215 "movntps %%xmm2, 32(%1)\n" |
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216 "movntps %%xmm3, 48(%1)\n" |
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217 :: "r" (from), "r" (to) : "memory"); |
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218 ((const unsigned char *)from)+=64; |
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219 ((unsigned char *)to)+=64; |
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220 } |
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221 #else |
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222 // Align destination at BLOCK_SIZE boundary |
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223 for(; ((int)to & (BLOCK_SIZE-1)) && i>0; i--) |
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224 { |
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225 __asm__ __volatile__ ( |
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226 #ifndef HAVE_MMX1 |
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227 PREFETCH" 320(%0)\n" |
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228 #endif |
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229 "movq (%0), %%mm0\n" |
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230 "movq 8(%0), %%mm1\n" |
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231 "movq 16(%0), %%mm2\n" |
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232 "movq 24(%0), %%mm3\n" |
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233 "movq 32(%0), %%mm4\n" |
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234 "movq 40(%0), %%mm5\n" |
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235 "movq 48(%0), %%mm6\n" |
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236 "movq 56(%0), %%mm7\n" |
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237 MOVNTQ" %%mm0, (%1)\n" |
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238 MOVNTQ" %%mm1, 8(%1)\n" |
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239 MOVNTQ" %%mm2, 16(%1)\n" |
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240 MOVNTQ" %%mm3, 24(%1)\n" |
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241 MOVNTQ" %%mm4, 32(%1)\n" |
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242 MOVNTQ" %%mm5, 40(%1)\n" |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
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243 MOVNTQ" %%mm6, 48(%1)\n" |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
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244 MOVNTQ" %%mm7, 56(%1)\n" |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
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245 :: "r" (from), "r" (to) : "memory"); |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
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246 ((const unsigned char *)from)+=64; |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
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247 ((unsigned char *)to)+=64; |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
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248 } |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
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249 |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
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250 // printf(" %d %d\n", (int)from&1023, (int)to&1023); |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
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251 // Pure Assembly cuz gcc is a bit unpredictable ;) |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
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252 if(i>=BLOCK_SIZE/64) |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
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253 asm volatile( |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
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254 "xorl %%eax, %%eax \n\t" |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
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255 ".balign 16 \n\t" |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
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256 "1: \n\t" |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
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257 "movl (%0, %%eax), %%ebx \n\t" |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
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258 "movl 32(%0, %%eax), %%ebx \n\t" |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
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259 "movl 64(%0, %%eax), %%ebx \n\t" |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
michael
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260 "movl 96(%0, %%eax), %%ebx \n\t" |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
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261 "addl $128, %%eax \n\t" |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
michael
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262 "cmpl %3, %%eax \n\t" |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
michael
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263 " jb 1b \n\t" |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
michael
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|
264 |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
michael
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265 "xorl %%eax, %%eax \n\t" |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
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266 |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
michael
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267 ".balign 16 \n\t" |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
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268 "2: \n\t" |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
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269 "movq (%0, %%eax), %%mm0\n" |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
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270 "movq 8(%0, %%eax), %%mm1\n" |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
michael
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271 "movq 16(%0, %%eax), %%mm2\n" |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
michael
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272 "movq 24(%0, %%eax), %%mm3\n" |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
michael
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273 "movq 32(%0, %%eax), %%mm4\n" |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
michael
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274 "movq 40(%0, %%eax), %%mm5\n" |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
michael
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275 "movq 48(%0, %%eax), %%mm6\n" |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
michael
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276 "movq 56(%0, %%eax), %%mm7\n" |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
michael
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277 MOVNTQ" %%mm0, (%1, %%eax)\n" |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
michael
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278 MOVNTQ" %%mm1, 8(%1, %%eax)\n" |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
michael
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279 MOVNTQ" %%mm2, 16(%1, %%eax)\n" |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
michael
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280 MOVNTQ" %%mm3, 24(%1, %%eax)\n" |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
michael
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281 MOVNTQ" %%mm4, 32(%1, %%eax)\n" |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
michael
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|
282 MOVNTQ" %%mm5, 40(%1, %%eax)\n" |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
michael
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|
283 MOVNTQ" %%mm6, 48(%1, %%eax)\n" |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
michael
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|
284 MOVNTQ" %%mm7, 56(%1, %%eax)\n" |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
michael
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|
285 "addl $64, %%eax \n\t" |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
michael
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|
286 "cmpl %3, %%eax \n\t" |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
michael
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287 "jb 2b \n\t" |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
michael
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|
288 |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
michael
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289 #if CONFUSION_FACTOR > 0 |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
michael
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290 // a few percent speedup on out of order executing CPUs |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
michael
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|
291 "movl %5, %%eax \n\t" |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
michael
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|
292 "2: \n\t" |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
michael
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|
293 "movl (%0), %%ebx \n\t" |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
michael
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|
294 "movl (%0), %%ebx \n\t" |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
michael
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|
295 "movl (%0), %%ebx \n\t" |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
michael
parents:
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|
296 "movl (%0), %%ebx \n\t" |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
michael
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297 "decl %%eax \n\t" |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
michael
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|
298 " jnz 2b \n\t" |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
michael
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|
299 #endif |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
michael
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|
300 |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
michael
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301 "xorl %%eax, %%eax \n\t" |
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302 "addl %3, %0 \n\t" |
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303 "addl %3, %1 \n\t" |
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304 "subl %4, %2 \n\t" |
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305 "cmpl %4, %2 \n\t" |
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306 " jae 1b \n\t" |
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307 : "+r" (from), "+r" (to), "+r" (i) |
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308 : "r" (BLOCK_SIZE), "i" (BLOCK_SIZE/64), "i" (CONFUSION_FACTOR) |
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309 : "%eax", "%ebx" |
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310 ); |
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311 |
698
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312 for(; i>0; i--) |
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313 { |
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314 __asm__ __volatile__ ( |
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315 #ifndef HAVE_MMX1 |
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316 PREFETCH" 320(%0)\n" |
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317 #endif |
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318 "movq (%0), %%mm0\n" |
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319 "movq 8(%0), %%mm1\n" |
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320 "movq 16(%0), %%mm2\n" |
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321 "movq 24(%0), %%mm3\n" |
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322 "movq 32(%0), %%mm4\n" |
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323 "movq 40(%0), %%mm5\n" |
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324 "movq 48(%0), %%mm6\n" |
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325 "movq 56(%0), %%mm7\n" |
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326 MOVNTQ" %%mm0, (%1)\n" |
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327 MOVNTQ" %%mm1, 8(%1)\n" |
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328 MOVNTQ" %%mm2, 16(%1)\n" |
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329 MOVNTQ" %%mm3, 24(%1)\n" |
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330 MOVNTQ" %%mm4, 32(%1)\n" |
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331 MOVNTQ" %%mm5, 40(%1)\n" |
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332 MOVNTQ" %%mm6, 48(%1)\n" |
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333 MOVNTQ" %%mm7, 56(%1)\n" |
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334 :: "r" (from), "r" (to) : "memory"); |
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335 ((const unsigned char *)from)+=64; |
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336 ((unsigned char *)to)+=64; |
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337 } |
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338 |
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339 #endif /* Have SSE */ |
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340 #ifdef HAVE_MMX2 |
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341 /* since movntq is weakly-ordered, a "sfence" |
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342 * is needed to become ordered again. */ |
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343 __asm__ __volatile__ ("sfence":::"memory"); |
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344 #endif |
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345 #ifndef HAVE_SSE |
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346 /* enables to use FPU */ |
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347 __asm__ __volatile__ (EMMS:::"memory"); |
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348 #endif |
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349 } |
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350 /* |
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351 * Now do the tail of the block |
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352 */ |
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353 if(len) small_memcpy(to, from, len); |
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354 return retval; |
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355 } |