Mercurial > mplayer.hg
annotate libvo/aclib_template.c @ 31342:996166ae509d
Remove unnecessary get_path() declaration.
author | diego |
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date | Mon, 14 Jun 2010 11:39:22 +0000 |
parents | 32725ca88fed |
children | 4e2f4bd081ce |
rev | line source |
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10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
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1 /* |
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2 * aclib - advanced C library ;) |
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3 * functions which improve and expand the standard C library |
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4 * |
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5 * This file is part of MPlayer. |
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6 * |
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7 * MPlayer is free software; you can redistribute it and/or modify |
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8 * it under the terms of the GNU General Public License as published by |
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9 * the Free Software Foundation; either version 2 of the License, or |
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10 * (at your option) any later version. |
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11 * |
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12 * MPlayer is distributed in the hope that it will be useful, |
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13 * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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15 * GNU General Public License for more details. |
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16 * |
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17 * You should have received a copy of the GNU General Public License along |
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18 * with MPlayer; if not, write to the Free Software Foundation, Inc., |
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19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. |
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20 */ |
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21 |
28290 | 22 #if !HAVE_SSE2 |
1123 | 23 /* |
24 P3 processor has only one SSE decoder so can execute only 1 sse insn per | |
25 cpu clock, but it has 3 mmx decoders (include load/store unit) | |
26 and executes 3 mmx insns per cpu clock. | |
27 P4 processor has some chances, but after reading: | |
28 http://www.emulators.com/pentium4.htm | |
29 I have doubts. Anyway SSE2 version of this code can be written better. | |
30 */ | |
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31 #undef HAVE_SSE |
28290 | 32 #define HAVE_SSE 0 |
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33 #endif |
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34 |
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35 |
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36 /* |
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37 This part of code was taken by me from Linux-2.4.3 and slightly modified |
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38 for MMX, MMX2, SSE instruction set. I have done it since linux uses page aligned |
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39 blocks but mplayer uses weakly ordered data and original sources can not |
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40 speedup them. Only using PREFETCHNTA and MOVNTQ together have effect! |
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41 |
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42 >From IA-32 Intel Architecture Software Developer's Manual Volume 1, |
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43 |
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44 Order Number 245470: |
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45 "10.4.6. Cacheability Control, Prefetch, and Memory Ordering Instructions" |
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46 |
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47 Data referenced by a program can be temporal (data will be used again) or |
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48 non-temporal (data will be referenced once and not reused in the immediate |
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49 future). To make efficient use of the processor's caches, it is generally |
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50 desirable to cache temporal data and not cache non-temporal data. Overloading |
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51 the processor's caches with non-temporal data is sometimes referred to as |
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52 "polluting the caches". |
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53 The non-temporal data is written to memory with Write-Combining semantics. |
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54 |
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55 The PREFETCHh instructions permits a program to load data into the processor |
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56 at a suggested cache level, so that it is closer to the processors load and |
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57 store unit when it is needed. If the data is already present in a level of |
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58 the cache hierarchy that is closer to the processor, the PREFETCHh instruction |
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59 will not result in any data movement. |
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60 But we should you PREFETCHNTA: Non-temporal data fetch data into location |
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61 close to the processor, minimizing cache pollution. |
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62 |
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63 The MOVNTQ (store quadword using non-temporal hint) instruction stores |
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64 packed integer data from an MMX register to memory, using a non-temporal hint. |
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65 The MOVNTPS (store packed single-precision floating-point values using |
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66 non-temporal hint) instruction stores packed floating-point data from an |
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67 XMM register to memory, using a non-temporal hint. |
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68 |
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69 The SFENCE (Store Fence) instruction controls write ordering by creating a |
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70 fence for memory store operations. This instruction guarantees that the results |
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71 of every store instruction that precedes the store fence in program order is |
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72 globally visible before any store instruction that follows the fence. The |
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73 SFENCE instruction provides an efficient way of ensuring ordering between |
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74 procedures that produce weakly-ordered data and procedures that consume that |
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75 data. |
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76 |
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77 If you have questions please contact with me: Nick Kurshev: nickols_k@mail.ru. |
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78 */ |
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79 |
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80 // 3dnow memcpy support from kernel 2.4.2 |
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81 // by Pontscho/fresh!mindworkz |
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82 |
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83 |
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84 #undef HAVE_ONLY_MMX1 |
28335 | 85 #if HAVE_MMX && !HAVE_MMX2 && !HAVE_AMD3DNOW && !HAVE_SSE |
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86 /* means: mmx v.1. Note: Since we added alignment of destinition it speedups |
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87 of memory copying on PentMMX, Celeron-1 and P2 upto 12% versus |
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88 standard (non MMX-optimized) version. |
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89 Note: on K6-2+ it speedups memory copying upto 25% and |
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90 on K7 and P3 about 500% (5 times). */ |
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91 #define HAVE_ONLY_MMX1 |
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92 #endif |
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93 |
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94 |
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95 #undef HAVE_K6_2PLUS |
28335 | 96 #if !HAVE_MMX2 && HAVE_AMD3DNOW |
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97 #define HAVE_K6_2PLUS |
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98 #endif |
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99 |
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100 /* for small memory blocks (<256 bytes) this version is faster */ |
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101 #define small_memcpy(to,from,n)\ |
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102 {\ |
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103 register x86_reg dummy;\ |
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104 __asm__ volatile(\ |
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105 "rep; movsb"\ |
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106 :"=&D"(to), "=&S"(from), "=&c"(dummy)\ |
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107 /* It's most portable way to notify compiler */\ |
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108 /* that edi, esi and ecx are clobbered in asm block. */\ |
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109 /* Thanks to A'rpi for hint!!! */\ |
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110 :"0" (to), "1" (from),"2" (n)\ |
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111 : "memory");\ |
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112 } |
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113 |
3393 | 114 #undef MMREG_SIZE |
28290 | 115 #if HAVE_SSE |
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116 #define MMREG_SIZE 16 |
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117 #else |
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118 #define MMREG_SIZE 64 //8 |
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119 #endif |
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120 |
3393 | 121 #undef PREFETCH |
122 #undef EMMS | |
5660 | 123 |
28290 | 124 #if HAVE_MMX2 |
5662 | 125 #define PREFETCH "prefetchnta" |
28335 | 126 #elif HAVE_AMD3DNOW |
5660 | 127 #define PREFETCH "prefetch" |
128 #else | |
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129 #define PREFETCH " # nop" |
5660 | 130 #endif |
131 | |
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132 /* On K6 femms is faster of emms. On K7 femms is directly mapped on emms. */ |
28335 | 133 #if HAVE_AMD3DNOW |
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134 #define EMMS "femms" |
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135 #else |
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136 #define EMMS "emms" |
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137 #endif |
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138 |
3393 | 139 #undef MOVNTQ |
28290 | 140 #if HAVE_MMX2 |
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141 #define MOVNTQ "movntq" |
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142 #else |
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143 #define MOVNTQ "movq" |
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144 #endif |
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145 |
3393 | 146 #undef MIN_LEN |
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147 #ifdef HAVE_ONLY_MMX1 |
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148 #define MIN_LEN 0x800 /* 2K blocks */ |
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149 #else |
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150 #define MIN_LEN 0x40 /* 64-byte blocks */ |
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151 #endif |
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152 |
7072 | 153 static void * RENAME(fast_memcpy)(void * to, const void * from, size_t len) |
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154 { |
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155 void *retval; |
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156 size_t i; |
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157 retval = to; |
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158 #ifdef STATISTICS |
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159 { |
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160 static int freq[33]; |
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161 static int t=0; |
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162 int i; |
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163 for(i=0; len>(1<<i); i++); |
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164 freq[i]++; |
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165 t++; |
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166 if(1024*1024*1024 % t == 0) |
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167 for(i=0; i<32; i++) |
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168 printf("freq < %8d %4d\n", 1<<i, freq[i]); |
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169 } |
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170 #endif |
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171 #ifndef HAVE_ONLY_MMX1 |
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172 /* PREFETCH has effect even for MOVSB instruction ;) */ |
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173 __asm__ volatile ( |
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174 PREFETCH" (%0)\n" |
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175 PREFETCH" 64(%0)\n" |
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176 PREFETCH" 128(%0)\n" |
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177 PREFETCH" 192(%0)\n" |
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178 PREFETCH" 256(%0)\n" |
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179 : : "r" (from) ); |
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180 #endif |
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181 if(len >= MIN_LEN) |
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182 { |
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183 register x86_reg delta; |
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184 /* Align destinition to MMREG_SIZE -boundary */ |
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185 delta = ((intptr_t)to)&(MMREG_SIZE-1); |
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186 if(delta) |
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187 { |
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188 delta=MMREG_SIZE-delta; |
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189 len -= delta; |
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190 small_memcpy(to, from, delta); |
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191 } |
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192 i = len >> 6; /* len/64 */ |
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193 len&=63; |
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194 /* |
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195 This algorithm is top effective when the code consequently |
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196 reads and writes blocks which have size of cache line. |
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197 Size of cache line is processor-dependent. |
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198 It will, however, be a minimum of 32 bytes on any processors. |
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199 It would be better to have a number of instructions which |
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200 perform reading and writing to be multiple to a number of |
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201 processor's decoders, but it's not always possible. |
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202 */ |
28290 | 203 #if HAVE_SSE /* Only P3 (may be Cyrix3) */ |
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204 if(((intptr_t)from) & 15) |
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205 /* if SRC is misaligned */ |
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206 for(; i>0; i--) |
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207 { |
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208 __asm__ volatile ( |
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209 PREFETCH" 320(%0)\n" |
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210 "movups (%0), %%xmm0\n" |
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211 "movups 16(%0), %%xmm1\n" |
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212 "movups 32(%0), %%xmm2\n" |
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213 "movups 48(%0), %%xmm3\n" |
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214 "movntps %%xmm0, (%1)\n" |
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215 "movntps %%xmm1, 16(%1)\n" |
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216 "movntps %%xmm2, 32(%1)\n" |
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217 "movntps %%xmm3, 48(%1)\n" |
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218 :: "r" (from), "r" (to) : "memory"); |
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219 from=((const unsigned char *) from)+64; |
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220 to=((unsigned char *)to)+64; |
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221 } |
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222 else |
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223 /* |
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224 Only if SRC is aligned on 16-byte boundary. |
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225 It allows to use movaps instead of movups, which required data |
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226 to be aligned or a general-protection exception (#GP) is generated. |
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227 */ |
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228 for(; i>0; i--) |
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229 { |
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230 __asm__ volatile ( |
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231 PREFETCH" 320(%0)\n" |
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232 "movaps (%0), %%xmm0\n" |
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233 "movaps 16(%0), %%xmm1\n" |
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234 "movaps 32(%0), %%xmm2\n" |
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235 "movaps 48(%0), %%xmm3\n" |
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236 "movntps %%xmm0, (%1)\n" |
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237 "movntps %%xmm1, 16(%1)\n" |
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238 "movntps %%xmm2, 32(%1)\n" |
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239 "movntps %%xmm3, 48(%1)\n" |
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240 :: "r" (from), "r" (to) : "memory"); |
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241 from=((const unsigned char *)from)+64; |
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242 to=((unsigned char *)to)+64; |
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243 } |
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244 #else |
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245 // Align destination at BLOCK_SIZE boundary |
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246 for(; ((intptr_t)to & (BLOCK_SIZE-1)) && i>0; i--) |
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247 { |
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248 __asm__ volatile ( |
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249 #ifndef HAVE_ONLY_MMX1 |
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250 PREFETCH" 320(%0)\n" |
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251 #endif |
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252 "movq (%0), %%mm0\n" |
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253 "movq 8(%0), %%mm1\n" |
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254 "movq 16(%0), %%mm2\n" |
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255 "movq 24(%0), %%mm3\n" |
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256 "movq 32(%0), %%mm4\n" |
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257 "movq 40(%0), %%mm5\n" |
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258 "movq 48(%0), %%mm6\n" |
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259 "movq 56(%0), %%mm7\n" |
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260 MOVNTQ" %%mm0, (%1)\n" |
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10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
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261 MOVNTQ" %%mm1, 8(%1)\n" |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
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262 MOVNTQ" %%mm2, 16(%1)\n" |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
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263 MOVNTQ" %%mm3, 24(%1)\n" |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
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264 MOVNTQ" %%mm4, 32(%1)\n" |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
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265 MOVNTQ" %%mm5, 40(%1)\n" |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
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266 MOVNTQ" %%mm6, 48(%1)\n" |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
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267 MOVNTQ" %%mm7, 56(%1)\n" |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
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268 :: "r" (from), "r" (to) : "memory"); |
15639 | 269 from=((const unsigned char *)from)+64; |
270 to=((unsigned char *)to)+64; | |
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10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
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271 } |
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10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
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272 |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
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273 // printf(" %d %d\n", (int)from&1023, (int)to&1023); |
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10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
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274 // Pure Assembly cuz gcc is a bit unpredictable ;) |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
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275 if(i>=BLOCK_SIZE/64) |
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08d18fe9da52
Change all occurrences of asm and __asm to __asm__, same as was done for FFmpeg.
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276 __asm__ volatile( |
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277 "xor %%"REG_a", %%"REG_a" \n\t" |
25973
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libvo: change asm syntax to use ASMALIGN and " # nop"
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278 ASMALIGN(4) |
3077
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10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
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279 "1: \n\t" |
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Use ecx instead of ebx to avoid unnecessary issues with PIC.
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280 "movl (%0, %%"REG_a"), %%ecx \n\t" |
7eb282a13214
Use ecx instead of ebx to avoid unnecessary issues with PIC.
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281 "movl 32(%0, %%"REG_a"), %%ecx \n\t" |
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Use ecx instead of ebx to avoid unnecessary issues with PIC.
reimar
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282 "movl 64(%0, %%"REG_a"), %%ecx \n\t" |
7eb282a13214
Use ecx instead of ebx to avoid unnecessary issues with PIC.
reimar
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283 "movl 96(%0, %%"REG_a"), %%ecx \n\t" |
13720
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284 "add $128, %%"REG_a" \n\t" |
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285 "cmp %3, %%"REG_a" \n\t" |
3077
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
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286 " jb 1b \n\t" |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
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287 |
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288 "xor %%"REG_a", %%"REG_a" \n\t" |
3077
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
michael
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289 |
25973
ef4297ed0d12
libvo: change asm syntax to use ASMALIGN and " # nop"
uau
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290 ASMALIGN(4) |
3077
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
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291 "2: \n\t" |
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292 "movq (%0, %%"REG_a"), %%mm0\n" |
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293 "movq 8(%0, %%"REG_a"), %%mm1\n" |
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294 "movq 16(%0, %%"REG_a"), %%mm2\n" |
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295 "movq 24(%0, %%"REG_a"), %%mm3\n" |
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296 "movq 32(%0, %%"REG_a"), %%mm4\n" |
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adapting existing mmx/mmx2/sse/3dnow optimizations so they work on x86_64
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297 "movq 40(%0, %%"REG_a"), %%mm5\n" |
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298 "movq 48(%0, %%"REG_a"), %%mm6\n" |
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299 "movq 56(%0, %%"REG_a"), %%mm7\n" |
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300 MOVNTQ" %%mm0, (%1, %%"REG_a")\n" |
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301 MOVNTQ" %%mm1, 8(%1, %%"REG_a")\n" |
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302 MOVNTQ" %%mm2, 16(%1, %%"REG_a")\n" |
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adapting existing mmx/mmx2/sse/3dnow optimizations so they work on x86_64
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303 MOVNTQ" %%mm3, 24(%1, %%"REG_a")\n" |
821f464b4d90
adapting existing mmx/mmx2/sse/3dnow optimizations so they work on x86_64
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304 MOVNTQ" %%mm4, 32(%1, %%"REG_a")\n" |
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adapting existing mmx/mmx2/sse/3dnow optimizations so they work on x86_64
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305 MOVNTQ" %%mm5, 40(%1, %%"REG_a")\n" |
821f464b4d90
adapting existing mmx/mmx2/sse/3dnow optimizations so they work on x86_64
aurel
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306 MOVNTQ" %%mm6, 48(%1, %%"REG_a")\n" |
821f464b4d90
adapting existing mmx/mmx2/sse/3dnow optimizations so they work on x86_64
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307 MOVNTQ" %%mm7, 56(%1, %%"REG_a")\n" |
821f464b4d90
adapting existing mmx/mmx2/sse/3dnow optimizations so they work on x86_64
aurel
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308 "add $64, %%"REG_a" \n\t" |
821f464b4d90
adapting existing mmx/mmx2/sse/3dnow optimizations so they work on x86_64
aurel
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309 "cmp %3, %%"REG_a" \n\t" |
3077
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
michael
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310 "jb 2b \n\t" |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
michael
parents:
1123
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311 |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
michael
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312 #if CONFUSION_FACTOR > 0 |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
michael
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313 // a few percent speedup on out of order executing CPUs |
13720
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aurel
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314 "mov %5, %%"REG_a" \n\t" |
3077
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
michael
parents:
1123
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|
315 "2: \n\t" |
29645
7eb282a13214
Use ecx instead of ebx to avoid unnecessary issues with PIC.
reimar
parents:
28446
diff
changeset
|
316 "movl (%0), %%ecx \n\t" |
7eb282a13214
Use ecx instead of ebx to avoid unnecessary issues with PIC.
reimar
parents:
28446
diff
changeset
|
317 "movl (%0), %%ecx \n\t" |
7eb282a13214
Use ecx instead of ebx to avoid unnecessary issues with PIC.
reimar
parents:
28446
diff
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|
318 "movl (%0), %%ecx \n\t" |
7eb282a13214
Use ecx instead of ebx to avoid unnecessary issues with PIC.
reimar
parents:
28446
diff
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|
319 "movl (%0), %%ecx \n\t" |
13720
821f464b4d90
adapting existing mmx/mmx2/sse/3dnow optimizations so they work on x86_64
aurel
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320 "dec %%"REG_a" \n\t" |
3077
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
michael
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321 " jnz 2b \n\t" |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
michael
parents:
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322 #endif |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
michael
parents:
1123
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323 |
13720
821f464b4d90
adapting existing mmx/mmx2/sse/3dnow optimizations so they work on x86_64
aurel
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324 "xor %%"REG_a", %%"REG_a" \n\t" |
821f464b4d90
adapting existing mmx/mmx2/sse/3dnow optimizations so they work on x86_64
aurel
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325 "add %3, %0 \n\t" |
821f464b4d90
adapting existing mmx/mmx2/sse/3dnow optimizations so they work on x86_64
aurel
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326 "add %3, %1 \n\t" |
821f464b4d90
adapting existing mmx/mmx2/sse/3dnow optimizations so they work on x86_64
aurel
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327 "sub %4, %2 \n\t" |
821f464b4d90
adapting existing mmx/mmx2/sse/3dnow optimizations so they work on x86_64
aurel
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328 "cmp %4, %2 \n\t" |
3077
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
michael
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329 " jae 1b \n\t" |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
michael
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330 : "+r" (from), "+r" (to), "+r" (i) |
30135
807fce7a4bb3
Do not assume that "long" is the size of a register.
reimar
parents:
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diff
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331 : "r" ((x86_reg)BLOCK_SIZE), "i" (BLOCK_SIZE/64), "i" ((x86_reg)CONFUSION_FACTOR) |
29645
7eb282a13214
Use ecx instead of ebx to avoid unnecessary issues with PIC.
reimar
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|
332 : "%"REG_a, "%ecx" |
3077
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
michael
parents:
1123
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|
333 ); |
99f6db3255aa
10-20% faster fastmemcpy :) on my p3 at least but the algo is mostly from "amd athlon processor x86 code optimization guide" so it should be faster for amd chips too, but i fear it might be slower for mem->vram copies (someone should check that, i cant) ... there are 2 #defines to finetune it (BLOCK_SIZE & CONFUSION_FACTOR)
michael
parents:
1123
diff
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|
334 |
698
f0fbf1a9bf31
Moving fast_memcpy to separate file (Size optimization)
nickols_k
parents:
diff
changeset
|
335 for(; i>0; i--) |
f0fbf1a9bf31
Moving fast_memcpy to separate file (Size optimization)
nickols_k
parents:
diff
changeset
|
336 { |
27757
b5a46071062a
Replace all occurrences of '__volatile__' and '__volatile' by plain 'volatile'.
diego
parents:
27754
diff
changeset
|
337 __asm__ volatile ( |
23378
ef54df9f07d3
HAVE_MMX1 -> HAVE_ONLY_MMX1 (makes more sense ...)
michael
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15639
diff
changeset
|
338 #ifndef HAVE_ONLY_MMX1 |
698
f0fbf1a9bf31
Moving fast_memcpy to separate file (Size optimization)
nickols_k
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diff
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|
339 PREFETCH" 320(%0)\n" |
f0fbf1a9bf31
Moving fast_memcpy to separate file (Size optimization)
nickols_k
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diff
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|
340 #endif |
f0fbf1a9bf31
Moving fast_memcpy to separate file (Size optimization)
nickols_k
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diff
changeset
|
341 "movq (%0), %%mm0\n" |
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Moving fast_memcpy to separate file (Size optimization)
nickols_k
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diff
changeset
|
342 "movq 8(%0), %%mm1\n" |
f0fbf1a9bf31
Moving fast_memcpy to separate file (Size optimization)
nickols_k
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diff
changeset
|
343 "movq 16(%0), %%mm2\n" |
f0fbf1a9bf31
Moving fast_memcpy to separate file (Size optimization)
nickols_k
parents:
diff
changeset
|
344 "movq 24(%0), %%mm3\n" |
f0fbf1a9bf31
Moving fast_memcpy to separate file (Size optimization)
nickols_k
parents:
diff
changeset
|
345 "movq 32(%0), %%mm4\n" |
f0fbf1a9bf31
Moving fast_memcpy to separate file (Size optimization)
nickols_k
parents:
diff
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346 "movq 40(%0), %%mm5\n" |
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347 "movq 48(%0), %%mm6\n" |
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348 "movq 56(%0), %%mm7\n" |
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349 MOVNTQ" %%mm0, (%1)\n" |
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350 MOVNTQ" %%mm1, 8(%1)\n" |
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351 MOVNTQ" %%mm2, 16(%1)\n" |
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352 MOVNTQ" %%mm3, 24(%1)\n" |
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353 MOVNTQ" %%mm4, 32(%1)\n" |
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354 MOVNTQ" %%mm5, 40(%1)\n" |
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355 MOVNTQ" %%mm6, 48(%1)\n" |
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356 MOVNTQ" %%mm7, 56(%1)\n" |
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357 :: "r" (from), "r" (to) : "memory"); |
15639 | 358 from=((const unsigned char *)from)+64; |
359 to=((unsigned char *)to)+64; | |
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360 } |
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361 |
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362 #endif /* Have SSE */ |
28290 | 363 #if HAVE_MMX2 |
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364 /* since movntq is weakly-ordered, a "sfence" |
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365 * is needed to become ordered again. */ |
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366 __asm__ volatile ("sfence":::"memory"); |
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367 #endif |
28290 | 368 #if !HAVE_SSE |
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369 /* enables to use FPU */ |
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370 __asm__ volatile (EMMS:::"memory"); |
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371 #endif |
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372 } |
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373 /* |
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374 * Now do the tail of the block |
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375 */ |
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376 if(len) small_memcpy(to, from, len); |
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377 return retval; |
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378 } |
4681 | 379 |
380 /** | |
381 * special copy routine for mem -> agp/pci copy (based upon fast_memcpy) | |
382 */ | |
7072 | 383 static void * RENAME(mem2agpcpy)(void * to, const void * from, size_t len) |
4681 | 384 { |
385 void *retval; | |
386 size_t i; | |
387 retval = to; | |
388 #ifdef STATISTICS | |
389 { | |
390 static int freq[33]; | |
391 static int t=0; | |
392 int i; | |
393 for(i=0; len>(1<<i); i++); | |
394 freq[i]++; | |
395 t++; | |
396 if(1024*1024*1024 % t == 0) | |
397 for(i=0; i<32; i++) | |
398 printf("mem2agp freq < %8d %4d\n", 1<<i, freq[i]); | |
399 } | |
400 #endif | |
401 if(len >= MIN_LEN) | |
402 { | |
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403 register x86_reg delta; |
4681 | 404 /* Align destinition to MMREG_SIZE -boundary */ |
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405 delta = ((intptr_t)to)&7; |
4681 | 406 if(delta) |
407 { | |
408 delta=8-delta; | |
409 len -= delta; | |
410 small_memcpy(to, from, delta); | |
411 } | |
412 i = len >> 6; /* len/64 */ | |
413 len &= 63; | |
414 /* | |
415 This algorithm is top effective when the code consequently | |
416 reads and writes blocks which have size of cache line. | |
417 Size of cache line is processor-dependent. | |
418 It will, however, be a minimum of 32 bytes on any processors. | |
419 It would be better to have a number of instructions which | |
420 perform reading and writing to be multiple to a number of | |
421 processor's decoders, but it's not always possible. | |
422 */ | |
423 for(; i>0; i--) | |
424 { | |
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425 __asm__ volatile ( |
4681 | 426 PREFETCH" 320(%0)\n" |
427 "movq (%0), %%mm0\n" | |
428 "movq 8(%0), %%mm1\n" | |
429 "movq 16(%0), %%mm2\n" | |
430 "movq 24(%0), %%mm3\n" | |
431 "movq 32(%0), %%mm4\n" | |
432 "movq 40(%0), %%mm5\n" | |
433 "movq 48(%0), %%mm6\n" | |
434 "movq 56(%0), %%mm7\n" | |
435 MOVNTQ" %%mm0, (%1)\n" | |
436 MOVNTQ" %%mm1, 8(%1)\n" | |
437 MOVNTQ" %%mm2, 16(%1)\n" | |
438 MOVNTQ" %%mm3, 24(%1)\n" | |
439 MOVNTQ" %%mm4, 32(%1)\n" | |
440 MOVNTQ" %%mm5, 40(%1)\n" | |
441 MOVNTQ" %%mm6, 48(%1)\n" | |
442 MOVNTQ" %%mm7, 56(%1)\n" | |
443 :: "r" (from), "r" (to) : "memory"); | |
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444 from=((const unsigned char *)from)+64; |
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445 to=((unsigned char *)to)+64; |
4681 | 446 } |
28290 | 447 #if HAVE_MMX2 |
4681 | 448 /* since movntq is weakly-ordered, a "sfence" |
449 * is needed to become ordered again. */ | |
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450 __asm__ volatile ("sfence":::"memory"); |
4681 | 451 #endif |
452 /* enables to use FPU */ | |
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453 __asm__ volatile (EMMS:::"memory"); |
4681 | 454 } |
455 /* | |
456 * Now do the tail of the block | |
457 */ | |
458 if(len) small_memcpy(to, from, len); | |
459 return retval; | |
460 } |