Mercurial > mplayer.hg
annotate vidix/s3_regs.h @ 30603:c5d8b7640b7d
Call mpcodecs_config_vo with the proper image format for dmo and dshow codecs.
author | reimar |
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date | Thu, 18 Feb 2010 22:28:55 +0000 |
parents | 0f1b5b68af32 |
children | b11dc6175323 |
rev | line source |
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26972 | 1 /* |
2 * S3 chipsets registers definition. | |
3 * | |
4 * Copyright (C) 2004 Reza Jelveh | |
5 * Thanks to Alex Deucher for Support | |
6 * Trio/Virge support by Michael Kostylev | |
7 * | |
8 * This file is part of MPlayer. | |
9 * | |
10 * MPlayer is free software; you can redistribute it and/or modify | |
11 * it under the terms of the GNU General Public License as published by | |
12 * the Free Software Foundation; either version 2 of the License, or | |
13 * (at your option) any later version. | |
14 * | |
15 * MPlayer is distributed in the hope that it will be useful, | |
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 * GNU General Public License for more details. | |
19 * | |
20 * You should have received a copy of the GNU General Public License along | |
21 * with MPlayer; if not, write to the Free Software Foundation, Inc., | |
22 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. | |
23 */ | |
24 | |
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25 #ifndef MPLAYER_SAVAGE_REGS_H |
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26 #define MPLAYER_SAVAGE_REGS_H |
26096 | 27 |
28 #define S3_SAVAGE3D_SERIES(chip) ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE_MX)) | |
29 #define S3_SAVAGE4_SERIES(chip) ((chip==S3_SAVAGE4) || (chip==S3_PROSAVAGE)) | |
30 #define S3_SAVAGE_MOBILE_SERIES(chip) ((chip==S3_SAVAGE_MX) || (chip==S3_SUPERSAVAGE)) | |
31 #define S3_SAVAGE_SERIES(chip) ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE2000)) | |
32 | |
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33 /* |
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34 * Chip tags. These are used to group the adapters into |
26096 | 35 * related families. |
36 */ | |
37 enum S3CHIPTAGS { | |
38 S3_UNKNOWN = 0, | |
39 S3_TRIO64V, | |
40 S3_VIRGE, | |
41 S3_SAVAGE3D, | |
42 S3_SAVAGE_MX, | |
43 S3_SAVAGE4, | |
44 S3_PROSAVAGE, | |
45 S3_SUPERSAVAGE, | |
46 S3_SAVAGE2000, | |
47 S3_LAST | |
48 }; | |
49 | |
50 #define BIOS_BSIZE 1024 | |
51 #define BIOS_BASE 0xc0000 | |
52 | |
53 #define S3_NEWMMIO_REGBASE 0x1000000 /* 16MB */ | |
54 #define S3_NEWMMIO_REGSIZE 0x0010000 /* 64KB */ | |
55 #define S3_NEWMMIO_REGSIZE_SAVAGE 0x0080000 /* 512KB */ | |
56 | |
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57 #define BASE_FREQ 14.31818 |
26096 | 58 |
59 /* | |
60 * There are two different streams engines used in the S3 line. | |
61 * The old engine is in the Trio64, Virge, | |
62 * Savage3D, Savage4, SavagePro, and SavageTwister. | |
63 * The new engine is in the Savage2000, SavageMX, | |
64 * SavageIX, and SuperSavage. | |
65 */ | |
66 | |
67 /* Old engine registers */ | |
68 #define PSTREAM_CONTROL_REG 0x8180 | |
69 #define COL_CHROMA_KEY_CONTROL_REG 0x8184 | |
70 #define SSTREAM_CONTROL_REG 0x8190 | |
71 #define CHROMA_KEY_UPPER_BOUND_REG 0x8194 | |
72 #define SSTREAM_STRETCH_REG 0x8198 | |
73 #define COLOR_ADJUSTMENT_REG 0x819C | |
74 #define BLEND_CONTROL_REG 0x81A0 | |
75 #define PSTREAM_FBADDR0_REG 0x81C0 | |
76 #define PSTREAM_FBADDR1_REG 0x81C4 | |
77 #define PSTREAM_STRIDE_REG 0x81C8 | |
78 #define DOUBLE_BUFFER_REG 0x81CC | |
79 #define SSTREAM_FBADDR0_REG 0x81D0 | |
80 #define SSTREAM_FBADDR1_REG 0x81D4 | |
81 #define SSTREAM_STRIDE_REG 0x81D8 | |
82 #define OPAQUE_OVERLAY_CONTROL_REG 0x81DC | |
83 #define K1_VSCALE_REG 0x81E0 | |
84 #define SSTREAM_VSCALE_REG 0x81E0 | |
85 #define K2_VSCALE_REG 0x81E4 | |
86 #define SSTREAM_VINITIAL_REG 0x81E4 | |
87 #define DDA_VERT_REG 0x81E8 | |
88 #define SSTREAM_LINES_REG 0x81E8 | |
89 #define STREAMS_FIFO_REG 0x81EC | |
90 #define PSTREAM_WINDOW_START_REG 0x81F0 | |
91 #define PSTREAM_WINDOW_SIZE_REG 0x81F4 | |
92 #define SSTREAM_WINDOW_START_REG 0x81F8 | |
93 #define SSTREAM_WINDOW_SIZE_REG 0x81FC | |
94 #define FIFO_CONTROL 0x8200 | |
95 #define PSTREAM_FBSIZE_REG 0x8300 | |
96 #define SSTREAM_FBSIZE_REG 0x8304 | |
97 #define SSTREAM_FBADDR2_REG 0x8308 | |
98 | |
99 /* New engine registers */ | |
100 #define PRI_STREAM_FBUF_ADDR0 0x81c0 | |
101 #define PRI_STREAM_FBUF_ADDR1 0x81c4 | |
102 #define PRI_STREAM_STRIDE 0x81c8 | |
103 #define PRI_STREAM_BUFFERSIZE 0x8214 | |
104 #define SEC_STREAM_CKEY_LOW 0x8184 | |
105 #define SEC_STREAM_CKEY_UPPER 0x8194 | |
106 #define BLEND_CONTROL 0x8190 | |
107 #define SEC_STREAM_COLOR_CONVERT1 0x8198 | |
108 #define SEC_STREAM_COLOR_CONVERT2 0x819c | |
109 #define SEC_STREAM_COLOR_CONVERT3 0x81e4 | |
110 #define SEC_STREAM_HSCALING 0x81a0 | |
111 #define SEC_STREAM_BUFFERSIZE 0x81a8 | |
112 #define SEC_STREAM_HSCALE_NORMALIZE 0x81ac | |
113 #define SEC_STREAM_VSCALING 0x81e8 | |
114 #define SEC_STREAM_FBUF_ADDR0 0x81d0 | |
115 #define SEC_STREAM_FBUF_ADDR1 0x81d4 | |
116 #define SEC_STREAM_FBUF_ADDR2 0x81ec | |
117 #define SEC_STREAM_STRIDE 0x81d8 | |
118 #define SEC_STREAM_WINDOW_START 0x81f8 | |
119 #define SEC_STREAM_WINDOW_SZ 0x81fc | |
120 #define SEC_STREAM_TILE_OFF 0x821c | |
121 #define SEC_STREAM_OPAQUE_OVERLAY 0x81dc | |
122 | |
123 /* Savage 2000 registers */ | |
124 #define SEC_STREAM_COLOR_CONVERT0_2000 0x8198 | |
125 #define SEC_STREAM_COLOR_CONVERT1_2000 0x819c | |
126 #define SEC_STREAM_COLOR_CONVERT2_2000 0x81e0 | |
127 #define SEC_STREAM_COLOR_CONVERT3_2000 0x81e4 | |
128 | |
129 /* Virge+ registers */ | |
130 #define FIFO_CONTROL_REG 0x8200 | |
131 #define MIU_CONTROL_REG 0x8204 | |
132 #define STREAMS_TIMEOUT_REG 0x8208 | |
133 #define MISC_TIMEOUT_REG 0x820c | |
134 | |
135 /* VGA stuff */ | |
136 #define vgaCRIndex 0x3d4 | |
137 #define vgaCRReg 0x3d5 | |
138 | |
139 /* CRT Control registers */ | |
140 #define EXT_MEM_CTRL1 0x53 | |
141 #define LIN_ADDR_CTRL 0x58 | |
142 #define EXT_MISC_CTRL2 0x67 | |
143 | |
144 /* Old engine constants */ | |
145 #define ENABLE_NEWMMIO 0x08 | |
146 #define ENABLE_LFB 0x10 | |
147 #define ENABLE_STREAMS_OLD 0x0c | |
148 #define NO_STREAMS_OLD 0xf3 | |
149 | |
150 /* New engine constants */ | |
151 #define ENABLE_STREAM1 0x04 | |
152 #define NO_STREAMS 0xF9 | |
153 | |
154 #define VerticalRetraceWait() \ | |
155 do { \ | |
156 VGAIN8(0x3d4); \ | |
157 VGAOUT8(0x3d4, 0x17); \ | |
158 if (VGAIN8(0x3d5) & 0x80) { \ | |
159 int i = 0x10000; \ | |
160 while ((VGAIN8(0x3da) & 0x08) == 0x08 && i--) ; \ | |
161 i = 0x10000; \ | |
162 while ((VGAIN8(0x3da) & 0x08) == 0x00 && i--) ; \ | |
163 } \ | |
164 } while (0) | |
165 | |
166 /* Scaling operations */ | |
167 #define HSCALING_Shift 0 | |
168 #define HSCALING_Mask (((1L << 16)-1) << HSCALING_Shift) | |
169 #define HSCALING(w0,w1) ((((unsigned int)(((double)w0/(double)w1) * (1 << 15))) << HSCALING_Shift) & HSCALING_Mask) | |
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170 |
26096 | 171 #define VSCALING_Shift 0 |
172 #define VSCALING_Mask (((1L << 20)-1) << VSCALING_Shift) | |
173 #define VSCALING(h0,h1) ((((unsigned int) (((double)h0/(double)h1) * (1 << 15))) << VSCALING_Shift) & VSCALING_Mask) | |
174 | |
175 /* Scaling factors */ | |
176 #define HDM_SHIFT 16 | |
177 #define HDSCALE_4 (2 << HDM_SHIFT) | |
178 #define HDSCALE_8 (3 << HDM_SHIFT) | |
179 #define HDSCALE_16 (4 << HDM_SHIFT) | |
180 #define HDSCALE_32 (5 << HDM_SHIFT) | |
181 #define HDSCALE_64 (6 << HDM_SHIFT) | |
182 | |
183 /* Window parameters */ | |
184 #define OS_XY(x,y) (((x+1)<<16)|(y+1)) | |
185 #define OS_WH(x,y) (((x-1)<<16)|(y)) | |
186 | |
187 /* PCI stuff */ | |
188 | |
189 /* PCI-Memory IO access macros. */ | |
190 #define VID_WR08(p,i,val) (((uint8_t *)(p))[(i)]=(val)) | |
191 #define VID_RD08(p,i) (((uint8_t *)(p))[(i)]) | |
192 | |
193 #define VID_WR32(p,i,val) (((uint32_t *)(p))[(i)/4]=(val)) | |
194 #define VID_RD32(p,i) (((uint32_t *)(p))[(i)/4]) | |
195 | |
196 #ifndef USE_RMW_CYCLES | |
197 | |
198 /* Can be used to inhibit READ-MODIFY-WRITE cycles. On by default. */ | |
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199 #define MEM_BARRIER() __asm__ volatile ("" : : : "memory") |
26096 | 200 |
201 #undef VID_WR08 | |
202 #define VID_WR08(p,i,val) ({ MEM_BARRIER(); ((uint8_t *)(p))[(i)]=(val); }) | |
203 #undef VID_RD08 | |
204 #define VID_RD08(p,i) ({ MEM_BARRIER(); ((uint8_t *)(p))[(i)]; }) | |
205 | |
206 #undef VID_WR16 | |
207 #define VID_WR16(p,i,val) ({ MEM_BARRIER(); ((uint16_t *)(p))[(i)/2]=(val); }) | |
208 #undef VID_RD16 | |
209 #define VID_RD16(p,i) ({ MEM_BARRIER(); ((uint16_t *)(p))[(i)/2]; }) | |
210 | |
211 #undef VID_WR32 | |
212 #define VID_WR32(p,i,val) ({ MEM_BARRIER(); ((uint32_t *)(p))[(i)/4]=(val); }) | |
213 #undef VID_RD32 | |
214 #define VID_RD32(p,i) ({ MEM_BARRIER(); ((uint32_t *)(p))[(i)/4]; }) | |
215 #endif /* USE_RMW_CYCLES */ | |
216 | |
217 #define VID_AND32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)&(val)) | |
218 #define VID_OR32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)|(val)) | |
219 #define VID_XOR32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)^(val)) | |
220 | |
221 #define VGAIN8(addr) VID_RD08(info->control_base+0x8000, addr) | |
222 #define VGAIN16(addr) VID_RD16(info->control_base+0x8000, addr) | |
223 #define VGAIN(addr) VID_RD32(info->control_base+0x8000, addr) | |
224 | |
225 #define VGAOUT8(addr,val) VID_WR08(info->control_base+0x8000, addr, val) | |
226 #define VGAOUT16(addr,val) VID_WR16(info->control_base+0x8000, addr, val) | |
227 #define VGAOUT(addr,val) VID_WR32(info->control_base+0x8000, addr, val) | |
228 | |
229 #define INREG(addr) VID_RD32(info->control_base, addr) | |
230 #define OUTREG(addr,val) VID_WR32(info->control_base, addr, val) | |
231 #define INREG8(addr) VID_RD08(info->control_base, addr) | |
232 #define OUTREG8(addr,val) VID_WR08(info->control_base, addr, val) | |
233 #define INREG16(addr) VID_RD16(info->control_base, addr) | |
234 #define OUTREG16(addr,val) VID_WR16(info->control_base, addr, val) | |
235 | |
236 #define ALIGN_TO(v, n) (((v) + (n-1)) & ~(n-1)) | |
237 | |
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238 #endif /* MPLAYER_S3_REGS_H */ |